JPS6118901B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a TV image display device using a matrix panel such as a thin film electroluminescent panel (hereinafter referred to as thin film ELP) or a plasma display panel, and more specifically, to a control method for writing and erasing display signals. First, we investigated the emission extinction mechanism of the matrix panel display of the present invention and its hysteresis characteristics using a thin film.
This will be explained using ELP as an example. Figure 1 shows the structure of the thin film ELP. Glass substrate 1
A striped transparent electrode 2 is arranged in parallel thereon, and on top of this, a dielectric material layer 3 such as _Y2O3 , a fluorescent material layer 4 such as Mn-doped ZnS, and the same as above _. A dielectric material layer 3' having a three-layer structure formed by a thin film production technique such as vapor deposition sputtering is provided, and a striped transparent electrode 5 orthogonal to the transparent electrode 2 is further provided in parallel thereon. In such a structure, when an appropriate AC voltage is applied to one of the first electrode group 2 and one of the second electrode group 5, only the minute area where both electrodes intersect will emit light. This corresponds to one picture element on the screen. When the applied voltage remains unchanged, light is emitted with constant brightness each time the applied voltage is applied, but when the applied voltage, pulse width, or frequency changes, the brightness exhibits hysteresis characteristics. The case where this hysteresis characteristic is changed by changing the applied voltage will be explained with reference to FIG. first second
When a pulse of voltage amplitude V ₁ as shown in Figure a is applied, the brightness is at the level B ₁ as shown in Figures b and c. Here, if the luminescence threshold voltage is Vth, then V ₁ is
V ₁ >Vth. When an appropriate write voltage V ₂ is applied to this, the brightness increases all at once to B ₃ , and from then on,
Even if the voltage value is returned to the maintenance voltage _V1 again, the brightness settles to _B2 , which is greater than _B1 . When the erase voltage _V3 is applied to this, the brightness level decreases rapidly, and when it is returned to the sustaining voltage _V1 again, the brightness settles to _B1 . These temporal relationships are indicated by the symbols t ₁ , t ₃ ,
. . . t ₂₁ is shown by corresponding to the positions of the same symbols in the same figure c. Since such a hysteresis phenomenon can take any small loop as shown by the thin line in FIG. 2b depending on the amplitude or pulse width of the write voltage, halftone display is also possible. When displaying using a light-emitting display mechanism with a memory function, especially when overwriting is not performed, each pixel has an erase pulse and a subsequent a non-emission period TN maintained by the application of successive sustain pulses;
The light emitting period TB maintained by application of a write selection pulse and a subsequent sustain pulse is alternately repeated. Therefore, when the number of frames of an image is regulated, such as on a TV display, the larger the ratio of the light-emitting period TB to the non-light-emitting period TN, the brighter the image will be, making the display device suitable for large-screen display. become. Furthermore, as one of the human visual characteristics, the relationship between the brightness B of the display and the critical fusion frequency CFF at which the human eye perceives flickering changes depending on the afterglow time τ of the display, as shown in Figure 3. As the afterglow time becomes longer, the critical fusion frequency becomes lower for the same luminance, and the area where no flicker is perceived increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a TV image display device using a matrix panel that can significantly increase screen brightness despite a simple circuit configuration. The TV image display device of the present invention is characterized in that, when displaying a TV video signal, one field is divided into a write field period and an erase field period. Hereinafter, an embodiment of the present invention in which interlaced scanning is performed using a thin film ELP will be described in detail. FIG. 4 shows a circuit block diagram of an embodiment of the present invention. The composite video signal introduced into the video signal input terminal 6 is separated into a video signal and a synchronization signal by a signal separation circuit 7, and each is guided to a signal processing circuit 8 and a timing control circuit 9. The signal processing circuit 8 is composed of a sample and hold circuit and an A-D converter, and sequentially samples the video signal based on a clock signal and converts the video signal into, for example, eight gradations of brightness levels B ₀ , B ₁ , . . . Convert to a 3-bit digital signal representing _B7 . The signal holding circuit 10 connects the X-column electrode group X ₁ to Xm of the matrix display panel 18.
This is a shift register that holds the above-mentioned 3-bit luminance signals corresponding to each of the three bits. The display signal pulse generating circuit 1 is a circuit that generates a display signal pulse whose pulse width is modulated in accordance with the above-mentioned digital luminance signal, and FIG. 5 shows an example of the circuit related to one electrode line. In FIG. 5, reference numeral 19 denotes various pulse width signal generation circuits, which generate modulation pulse width signals t ₀ , t ₁ ,
...outputs _t7 and strobe signal ts. As shown in FIG. 8, a specific example of this circuit is composed of nine monostable multivibrators 21, 22, . . . , 29, and each output pulse width can be adjusted independently. 20 is a multiplexer which outputs pulses corresponding to the contents of the 3-bit luminance signals Ai, Bi, and Ci from its output terminal. X electrode drive circuit 12
is the electrode group of the panel 18 by the display signal pulse.
This is a circuit for driving X ₁ , X ₂ , . . . Xm, and a specific example of the circuit is shown in FIG. On the other hand, sustain pulses, erase pulses, and row selection pulses from the sustain pulse generator 14, erase pulse generator 15, and row selection pulse generator 16 are sent to the electrode groups Y ₁ , Y ₂ , . . . through the Y electrode drive circuit 17, respectively. Given to Yn. The timing at which the erase pulse and row selection pulse are applied will be explained in detail later. In addition, as explained in FIG. 2a, the sustain pulse includes a non-emission period,
The alternating current pulse is always the same voltage regardless of the light emitting period or brightness, and is always applied continuously except when an erase pulse or selection pulse is applied. The timing control circuit 9 generates various control signals based on the clock signal from the clock generation circuit 13 and the TV periodic signal, among which the most important one is the field control signal. That is, based on the synchronization signal, the odd field erase period signal EFO, the odd field write period signal
Four field signals including WFO, even field erase period signal EFE, and even field write period signal WFE are sequentially generated within one frame. A concrete example of this circuit is shown in FIG. In the figure, 21 is a vertical synchronizing pulse input terminal, 22 and 23 are D flip-flops, and 24, 25, 26, and 27 are AND gates. Various control signals output by the timing control circuit 9 are transmitted to the signal processing circuit 8 and the signal holding circuit 1.
0, the display signal pulse generation circuit 11, the X electrode drive circuit 12, the sustain pulse, erase pulse, and row selection pulse pulse generators 14, 15, and 16, and the Y electrode drive circuit 17 are controlled as described in the operation description below. are doing. Now, as shown in FIG.
Electrodes Xi, Yj and the picture element when a display signal is written to the picture element (i, j) intersected by the electrode Xi in the column and the electrode Yj in the j-th row, and the display signal is emitted for a while and then erased. Voltage waveforms Vxi, Vyj, applied to (i・j)
The time chart of V(i・j) is shown in Figure 7 a, b,
Shown in c. FIG. 7d shows the light emission waveform of picture elements (i and j) corresponding to the above applied voltage when ELP is used. In FIG. 7, A is a write pulse, B is a sustain pulse, C is an erase pulse, D is a display signal pulse applied to a column electrode, and E is a row selection pulse.
Further, the write pulse I is a pulse generated between the electrodes due to the potential difference between the display signal pulse D and the row selection pulse E. In the embodiment, a row scanning method is used, and a write signal pulse is simultaneously applied to each column of X ₁ to Xm.
Vw is applied, erase pulse and row selection pulse Vp
and VE are sequentially selected row by row, and each row is sequentially driven to emit light. Next, the display signal pulse generation system will be explained.
As shown in the table, the A-D converter of the signal processing circuit 8
It is assumed that signal processing is performed to represent 8 gradations using an ABC 3-bit digital signal. Furthermore, if the various pulse width signal generation circuits 19 of the display signal pulse generation circuit 11 generate pulse widths from t ₀ to t ₇ for eight gradations of luminance level, as shown in FIG. For gray levels represented by A=1, B=0, C=1, multiplexer 20 generates a display signal pulse signal equal to the pulse width of _t5 .

【table】

[Table] Next, control of the erase pulse and write selection pulse, which is the most characteristic feature of the present invention, will be explained. For convenience of explaining the case of interlaced scanning in the embodiment, Y ₁ , Y ₂ , . . . , Yn in FIG. 4 are replaced with odd-numbered electrode lines Yo ₁ , Yo ₂ , .
YoN and even-numbered electrode lines YE ₁ , YE ₂ ,…
..., YEN and change the symbol display. That is, Y ₁ = Yo ₁ , Y ₂ = YE ₁ , Y ₃ = Yo ₂ , ..., Yn−
₁ = YoN, Yn = YEN, and n = 2N. By this, the electrodes X ₁ , X ₂ , ..., X _n and the electrodes
The display area formed by using the intersection of Y ₁ , Y ₂ , ..., Y _o as picture elements is divided into two, Y ₀₁ , Y ₀₂ , ..., Y _0N
The first area corresponding to the odd line of Y _E1 , Y _E
2 , ..., _YEN can be understood as the sum of the second regions corresponding to even lines. In the case of normal TV broadcasting, an odd field and an even field are constructed every 1/60 second, and the fields are scanned using a 2:1 interlaced scanning method, so one screen is formed at a speed of 30 frames per second. In contrast, in the embodiment of the present invention, the writing speed is 15 frames per second, and each field is composed of a writing field WF and an erasing field EF. Figure 10 shows the 4-field EFO explained in Figure 6,
WFO, EFE, WFE and the light emitting period and non-light emitting period of each row are shown. In the figure, the O mark indicates the timing at which the write pulse is applied, and the X mark indicates the timing at which the erase pulse is applied. Also,
The solid line shows the light emitting period TB, and the dotted line shows the non-light emitting period TN. First, odd field write period
X ₁ to WFO horizontal scanning period (1H=63.5μS)
The contents of the sampled video signal of Xm are stored one after another in the signal holding circuit 10, and when sampling for 1H is completed, display signal pulses are given to the electrodes X ₁ , X ₂ , ..., Xm all at once, Since a row selection pulse is given from scan electrode Yo ₁ in synchronization,
m on scanning electrode Yo ₁ due to the cooperative action of both pulses.
A write pulse is applied to some of the picture elements, and they emit light with a brightness according to the input signal. In the following horizontal scanning period, the video signal related to Yo ₂ is sampled and stored in the signal holding circuit, and the scanning electrode Yo ₂
The upper picture element emits light. In this way, the scanning electrodes are sequentially selected up to YoN and emit light. Once a write pulse is applied to these picture elements, their light emission is sustained by a sustain pulse until an erase pulse is applied thereafter. Odd-numbered scanning electrode Vo ₁ ,
The erase pulse is given to Yo ₂ , ..., YoN during the odd field write period WFO to 3×1/6
During the next odd field erasing period EFO after 0 seconds, erasing is performed by selecting rows in the order of Yo ₁ , Yo ₂ , . . . , YoN, as in the case of writing described above. Odd field write period WFO during which the erased odd-numbered scan electrodes Yo ₁ , Yo ₂ , ..., YoN emit light according to the next image signal
is the field immediately after the erasing period EFO, that is, after 1/60 seconds, so in the end, the pixels related to the odd-numbered scanning electrodes emit light for 3 x 1/60 seconds and disappear for 1/60 seconds. , this operation is repeated at a cycle of 1/15 seconds, and the frames of the image advance. On the other hand, even-numbered scanning electrodes YE ₁ , YE ₂ ,...
..., YEN is written during the even field write period WFE, and the generation is maintained for 3 x 1/60 seconds, and then erased during the even field erase period EFE, and the erase is maintained for 1/60 seconds. The next image is written in the next even field write period WFE. In this way, all picture elements are 3
A field's light-emitting period and a field's non-light-emitting period are alternately repeated. According to this embodiment, since the ratio of the non-emission period to the emission period is 1:3, the emission time can be made larger than the non-emission time, making it easy to realize a large display device with bright brightness. Also, every second
Since the TV image sent in 30 frames can be emitted for 3 x 1/60 seconds, the critical fusion frequency is lowered and visual flicker is reduced, as explained in conjunction with Figure 3. Even in the test, 15 per second
Despite the frame speed, the flicker effect was significantly reduced and a good TV image was obtained. Although the ELP has been described above, the present invention can be similarly implemented in a matrix panel using a plasma display. According to the present invention, the drive circuit and the control circuit are simplified because the write field and the erase field are alternately repeated and the row scanning etc. are commonly configured. Further, since write pulses and erase pulses are not mixed in the same field, the number and time width of each pulse can be easily adjusted, allowing a greater degree of freedom. Therefore, image quality adjustment becomes easy.

[Brief explanation of the drawing]

1A and 1B are a partially cutaway perspective view and a sectional view of a thin film ELP, FIG. 2 is an explanatory diagram showing the history phenomenon of the applied voltage versus luminance of the thin film ELP, and FIG. 3 is a human visual characteristic diagram. FIG. 4 is a circuit block diagram of an embodiment of the present invention, FIG. 5 is a circuit example of the display signal pulse generator 11 and electrode drive circuit 12 in the above embodiment, and FIG. 6 is a timing control circuit 9 in the above embodiment.
A circuit example showing a part of the circuit, FIG. 7 is an explanatory diagram of the operation regarding light emission of the above embodiment, and FIG. 8 is a circuit diagram showing a specific example of the various pulse width signal generation circuits 19 of FIG. 5.
FIG. 9 is an explanatory diagram of interlaced scanning of the matrix panel of the above embodiment, and FIG. 10 is an explanatory diagram of the operation regarding the light emitting period and non-light emitting period of the above embodiment. 7: Signal separation circuit, 8: Signal processing circuit, 9: Timing control circuit, 10: Signal holding circuit, 11:
Display signal pulse generation circuit, 12: X column electrode drive circuit, 13: Clock generation circuit, 14: Sustain pulse generator, 15: Erase pulse generator, 16: Row selection pulse generator, 17: Y row electrode drive circuit, 18:
matrix panel.

Claims (1)

[Claims] 1. In a method for driving an image display device that emits and displays a television video signal using a display panel that exhibits a hysteresis characteristic between the amplitude, pulse width, or frequency of an applied pulse and luminance, the display area of the display panel is and the second area, and the first
After applying an erase field period and a subsequent write field period to the second area and driving the display, an erase field period and a subsequent write field period are applied to the second area and display driving is performed, and the second area The display of the first area is sustained during the display driving period of , and the display of the second area is maintained during the display driving period of the first area, thereby making the light emitting period of the display panel relative to the erasing period. 1. A method of driving an image display device, characterized in that the image display device is enlarged.