JPS6131437B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mechanism for checking the operation of a pulse waveform generator such as an electronic watch with an alarm mechanism implemented in a semiconductor integrated circuit.

As shown in FIG. 1, a conventional electronic watch with an alarm mechanism receives continuous pulses obtained from a pulse oscillator (not shown) at a terminal 7, and divides the pulses into a frequency dividing circuit 8 as a waveform at point e in FIG. It is converted into continuous pulses with a predetermined period as shown below and sent to the gate 12. At a predetermined time set in advance, a signal of a predetermined level as represented by the waveform at point a in FIG. 4 is applied to the terminal 1 and transmitted to the gate 12. The output of frequency divider 8 is blocked by gate 12 unless a signal of a predetermined level is received at terminal 1. Terminal 1
When a signal of a predetermined level is received in the frequency divider 8, the output of the frequency divider 8 is applied to the pattern generation circuit 4, and
A pattern signal shown as a dot waveform is output to terminal 3.
is derived. This pattern signal controls the oscillation time of an oscillator (not shown) to achieve the alarm function of the electronic timepiece.

In other words, the oscillator oscillates at the high level of the waveform at point c in Figure 4, and stops at the low level. For example, this oscillation first oscillates for 15 seconds, then oscillates for 15 seconds after 75 seconds. then 15 after 45 seconds
It oscillates for seconds, and after another 15 seconds, it is set to continue oscillating until it is stopped externally.

In order to confirm the operation of such a circuit after it is formed into a semiconductor integrated circuit, it is necessary to check the operation at either stage, whether it is at the semiconductor wafer stage or at the stage where it is placed in a container. Also, the time T when a predetermined pattern is completed (Figure 4, waveform at point c)
It takes a little longer than that. In the above example, this time is 3 minutes and 15 seconds or more. Furthermore, considering the quality of semiconductor chips on semiconductor wafers and the yield rate in the bonding process and other processes in which chips are placed in containers, in order to reduce manufacturing costs, it is necessary to check the operation of semiconductor wafers at the wafer stage and after placing them in containers. It is necessary to confirm the operation twice. Therefore, the time required for operation confirmation becomes extremely long, resulting in poor mass productivity and increased manufacturing costs.

A circuit as shown in FIG. 2 has also been proposed as a circuit configuration for reducing the time required for confirming operation. That is, the continuous pulse is received at the terminal 27 and the first frequency divider 28
The second frequency divider 29 converts the pulse into a continuous pulse as shown in the waveform at point d in FIG. The output of the first frequency divider 28 and the output of the second frequency divider 29 are added. This cycle switching gate 33
is normally set to output the output of the second frequency divider 29, for example, when the terminal 35 is at a high level. The output of the period switching gate 33 is gate 3
2 is applied to the pattern generating circuit 24 in response to a signal generated at a preset time at the terminal 21, and a pattern such as the waveform at point c in FIG. 4 is generated at the terminal 23.

When checking the operation, when a low level signal is applied to the terminal 35, the signal inverted by the inverter 36 and the non-inverted signal are applied to the period switching gate 33, which changes the output of the first frequency divider 28. The signal is transmitted to the gate 32. The frequency of the output pulse of the first frequency divider 28 is short as shown in the waveform at point d in FIG. This short cycle pulse is generated by the pattern generation circuit 2.
4, the time T of the pattern occurring at the terminal 23 becomes shorter than during normal operation.

However, in such a circuit configuration, it is necessary to provide extra measurement terminals on the semiconductor chip.
Another drawback is that an extra measuring terminal must be provided on the container. This not only increases the semiconductor chip area and lowers the yield, but also requires a larger container, leading to an increase in manufacturing costs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a pulse waveform generator that requires less time to confirm operation without increasing the number of terminals beyond the number required for normal operation.

According to the present invention, in a pulse waveform generator that outputs an output signal of a predetermined pulse waveform to an output terminal in response to a control signal applied to a control terminal, a continuous pulse generation circuit and a continuous pulse a first frequency divider that divides the output of the first frequency divider; a second frequency divider that further divides the output of the first frequency divider;
a switching circuit that switches between the output of the frequency divider and the output of the second frequency divider and outputs the output of the second frequency divider in a normal state; a gate circuit that inputs the output of the switching circuit; and a gate circuit. a control signal input terminal for applying a control signal to take out the output of the switching circuit from the gate circuit; a pattern shaping circuit for shaping the output signal of a predetermined pulse waveform according to the output of the gate circuit; and an output of the pattern shaping circuit. An output terminal that takes out a signal, a pulse generation circuit that generates a pulse based on a control signal when the output terminal is at a voltage level different from that when there is no signal, and a pulse generation circuit that generates this pulse when the output terminal is at a voltage level that is different from when there is no signal. A pulse waveform generating device is provided that includes a switching signal generator that switches the switching circuit so that the output of the first frequency divider is output as the output of the switching circuit in response to pulses generated in the circuit.

Next, one embodiment of the present invention will be described in more detail with reference to the drawings.

FIG. 3 is a block diagram of an electronic clock with an alarm mechanism implemented in a semiconductor integrated circuit.

A first frequency divider 48 receives continuous pulses at a terminal 47
The frequency is divided by the second frequency divider 49 to obtain a pulse having the waveform shown in FIG. 4d, and this pulse is further divided by the second frequency divider 49 to obtain the waveform shown in FIG. 4e. These first frequency dividers 48
and the output of the second frequency divider 49 are respectively applied to a switching circuit 53. The output of the second frequency divider 49 is taken out from the output of the switching circuit 53 during normal operation, that is, when the operation is not confirmed. The output of switching circuit 53 is applied to gate 52. The gate 52 controls the output of the switching circuit 53 unless a predetermined signal (in this embodiment, a high level voltage generated at a preset time as shown by the waveform at point a in FIG. 4) is applied to the terminal 41. No output. When a predetermined signal is applied to the terminal 41, the output of the second frequency divider, which is the output of the switching circuit, is sent from the gate 52 to the pattern generation circuit 4.
A pulse signal shown as a waveform at point c in FIG. 4 is output to terminal 43 via gate 50 and inverter 51, and this output operates an oscillator (not shown). The oscillator emits when the output of the pattern generation circuit 44 is at a high level, so for example, it oscillates for 15 seconds, stops for 75 seconds, oscillates for 15 seconds, stops for 45 seconds, oscillates for 15 seconds, stops for 15 seconds, and then starts oscillating from the outside. It oscillates until it stops.

One pulse generation circuit 42, inverter 54,
The gate 50, the inverter 51, the flip-flop 46, and the automatic recovery circuit 45 are circuits for checking the operation, but even during the above-mentioned normal operation, the terminal 4
When a predetermined signal is applied to the flip-flop 46, one pulse a is generated as shown in the waveform at point b in FIG. However, at this point, the potential at the terminal 43 is at a low level as shown by the waveform at point c in FIG. 4, so the flip-flop 46 does not operate. Further, since the output of the one-pulse generating circuit 42 is applied to the gate 50 via the inverter 54 and makes the gate 50 a low level, no signal is generated at the terminal 43 by this pulse d.

Next, when checking the operation, first apply a high-level voltage to the terminal 43 (pulse A of the waveform at point c in Figure 5), and then apply a high-level voltage signal to the terminal 41 (point a in Figure 5). Waveform). In response to the voltage signal at the terminal 41, a pulse β as shown in the waveform at point b in FIG. 5 is generated from the one-pulse generating circuit 42 and applied to the flip-flop 46. At this time, since the terminal 43 is at a high level, the flip-flop 46 operates and switches the switching circuit 53 to take out the output of the first frequency divider 48. The voltage at terminal 43 is then removed. The output of the first frequency divider 48 is transmitted to the pattern generation circuit 4 via a switching circuit 53 and a gate 52.
4 to produce a pattern of a predetermined shape, but the period of the output pulse of the first frequency divider 48 (the fifth
Since the waveform at point d in the figure) is shorter than the period of the output pulse of the first frequency divider 49 (the waveform at point e in Figure 5), the pattern generated at the terminal 43 is similar to the waveform at point c in Figure 5.
The period is short as shown by t ₁ and t ₂ . This pattern is controlled by an automatic return circuit 45 so that a predetermined pattern is repeated twice, and the flip-flop 46 is reset. After that, the steady operation described above is performed. This automatic reset circuit 45 can also count the output pulses of the pattern generation circuit 44 and reset the flip-flop 46, and can generate an output pulse of a predetermined time width to reset the flip-flop 46 after a predetermined time. It's okay.

As described above, according to the present invention, the operation can be confirmed in a short time without requiring a measurement terminal for confirming the operation. Therefore, the chip area does not increase, and therefore the yield does not decrease or the cost increases. Further, since there is no increase in the number of terminals in the container, a container that is correspondingly cheaper can be used. In addition, operation confirmation can be easily performed in a short time, and mass productivity can be improved.
In this way, a pulse waveform generator can be obtained at low cost and with high mass productivity.

Although the present invention has been described above regarding an electronic watch with an alarm mechanism, the present invention is not limited to the above, but can be similarly applied to a pulse waveform generator that generates pulses of a predetermined shape in response to one control signal. It is.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing conventional examples, respectively. FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a waveform chart showing the operation of FIGS. 1 to 3 during normal operation. FIG. 5 is a waveform diagram showing the operation at the time of operation confirmation in FIG. 3. 1, 21, 41, 3, 23, 43, 7, 27,
47, 35... terminal, 8, 28, 29, 48, 4
9... Frequency divider, 12, 32, 50, 52... Gate, 4, 24, 44... Pattern generation circuit, 3
3, 53...Switching circuit, 36, 51, 54...
...Inverter, 42...One pulse generation circuit, 4
5... Automatic return circuit, 46... Flip-flop.

Claims (1)

[Scope of Claims] 1. A pulse waveform generation circuit that generates an output signal with a preset pulse waveform at an output terminal in response to a control signal applied to a control terminal; A pulse waveform generator including an operation check circuit that shortens the period of the output signal by applying a control signal to a control terminal. 2. The pulse waveform generation circuit includes a continuous pulse input terminal, a first frequency divider that divides the frequency of the continuous pulse applied to the continuous pulse input terminal, and further divides the frequency of the output of the first frequency divider. a second frequency divider, a switching circuit that switches between the output of the first frequency divider and the output of the second frequency divider and derives the output of the second frequency divider in a steady state; a control terminal for inputting a signal; a gate for deriving the output of the switching circuit when the control signal is input to the control terminal; and a pulse waveform shaping device for deriving the preset pulse waveform from the output of the gate. the operation check circuit includes a pulse generation circuit that generates one pulse in response to the control signal, and a switching circuit that receives a pulse from the pulse generation circuit and when the output terminal is in a voltage state different from a steady state. 2. The pulse waveform generating device according to claim 1, further comprising a switching signal generator for switching the switching circuit to derive the output of the first frequency divider from the switching circuit.