JPH0252232B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse waveform generation circuit implemented in a semiconductor integrated circuit, and in particular to a pulse waveform generation circuit with a short operation confirmation time (hereinafter referred to as a test mode, and modes other than the test mode as normal modes). It is related to circuits.

In order to reduce the time required to check the operation of a conventional electronic watch with an alarm mechanism, the terminal 1 receives continuous pulses as shown at point a in FIG. 4 obtained from a pulse oscillator (not shown) as shown in FIG. This is sent to the first frequency dividing circuit 2 and the switching circuit 4. The first frequency dividing circuit 2 converts this into a continuous pulse of a predetermined period as shown by the waveform at point b in FIG. 4, and sends it to the switching circuit 4. At a predetermined time set in advance, a signal of a predetermined level as represented by the waveform at point e in FIG. 4 is applied to the terminal 5 and transmitted to the switching circuit 4. The switching circuit 4 is configured to send continuous pulses of a predetermined period to the second frequency dividing circuit 6, as represented by the normal mode waveform at point c in FIG. 4, unless a signal of a predetermined level is received at the terminal 5. There is.

The second frequency dividing circuit 6 converts this into a continuous pulse of a predetermined period as shown by the waveform at point d in FIG. 4, and sends it to the terminal 3. On the other hand, the second frequency dividing circuit 6 sends a signal at a predetermined level as shown by the waveform at point f in FIG. 5 to the alarm control circuit 8. A signal of a predetermined level as shown in the waveform at point g in FIG. 5 is received at the terminal 7 and sent to the alarm control circuit 8. When a predetermined level signal as represented by the waveform at point g in FIG. 5 changes from a high level to a low level, a signal at a predetermined level as represented by the waveform at point i in FIG. , a signal 50 of a predetermined level as represented by the waveform at point j in FIG.
and then converted into audio as an alarm sound. This signal accomplishes the alarm mechanism of the electronic watch. When checking the operation of this alarm mechanism (test mode), when a signal of a predetermined level is received at the terminal 5, the switching circuit 4 generates continuous pulses of a predetermined period as shown as the test mode waveform 51 at point c in FIG. The signal is sent to the second frequency dividing circuit 6.
Below, these signals repeat the above operation,
The signal is converted into a signal with a shortened period, such as the test mode waveform 52 at point d and the test mode waveform 55 at point j in FIG. Waveform 5 of this shortened signal
By measuring 5, the time required for checking the operation can be reduced.

When such a circuit is formed on a semiconductor integrated circuit, there are disadvantages in that extra measurement terminals 5 must be provided on the semiconductor chip, and additional measurement terminals must also be provided on the container. As a result, the semiconductor chip area increases, which not only lowers the yield but also requires a larger container, leading to an increase in manufacturing costs.

Furthermore, when checking the operation, the signal applied to the terminal 1 does not pass through the frequency divider circuit 2, so there is a drawback that the operation of the frequency divider circuit 2 cannot be checked.

A circuit as shown in FIG. 2 has also been proposed as a circuit configuration for reducing the time required for confirming operation.

That is, a continuous pulse as represented by the waveform at point a in FIG. The first frequency dividing circuit 12 converts this into a continuous pulse of a predetermined period as shown by the waveform at point b in FIG. 6, and sends it to the switching circuit 14. At a predetermined time set in advance, a signal 53 at a predetermined level as represented by the test mode waveform at point e in FIG. 6 is sent from the test speed up circuit 22 and transmitted to the switching circuit 14. Unless the switching circuit 14 receives a signal of a predetermined level as shown in the test mode waveform 53 at point e in FIG. The signal is configured to be sent to the frequency dividing circuit 16 of No. 2.

The second frequency dividing circuit 16 converts this into a continuous pulse of a predetermined period as shown by the waveform at point d in FIG. 6, and sends it to the terminal 13. On the other hand, the second frequency dividing circuit 1
6 sends a signal at a predetermined level as represented by the waveform at point f in FIG. 7 to the alarm control circuit 18.
A signal of a predetermined level as shown by the waveform at point g in FIG. 7 is received at the terminal 15 and sent to the alarm control circuit. When a signal at a predetermined level, as represented by the waveform at point g in FIG. 7, goes from a high level to a low level, a signal at a predetermined level, as represented by the waveform at point i in FIG. A signal of a predetermined level as shown in the waveform at point j in FIG. 7 is sent to the terminal 17 and converted into an alarm sound. When checking the operation of such an alarm mechanism, connect the seventh terminal to terminal 17.
A forced high level signal is applied to the test speed up circuit 22 from the terminal 17 as shown by the waveform at point j in the figure. When a signal of a predetermined level as represented by the waveform at point g in FIG. A signal of a predetermined level appearing as a waveform at point h in Fig. 7 is tested by the speed up circuit 22.
send to In response to this signal, the test speed up circuit 22 sends a signal of a predetermined level, which appears as a waveform at point e in FIG. 7, to the switching circuit 14.

When the switching circuit 14 receives a signal of a predetermined level as shown in the waveform at point e in FIG. 6, the switching circuit 14 transmits continuous pulses of a predetermined period as shown in the waveform at point c in FIG. 6 to the second frequency dividing circuit. Send to 16th. Hereafter, these signals repeat the above-mentioned operation, and the sixth
Test mode waveform 52 at point d in the figure and j in Figure 7
As shown in the test mode waveform 55 at the dot, the signal is converted into a signal with a shortened period. By measuring this shortened signal using a cathode ray tube or the like, it is possible to shorten the time required to confirm the operation.

However, even in such a circuit configuration, the function of the first frequency dividing circuit 12 cannot be confirmed because the first frequency dividing circuit 12 is bypassed in order to shorten the time for checking the operation. In order to confirm the function of the first frequency divider circuit 12, it is necessary to switch to the normal mode and observe its output, which has the disadvantage that it takes a long time to confirm the frequency divider circuit 12.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to completely check the operation without increasing the number of terminals beyond the number required for normal operation, and to shorten the time required for checking the operation.

According to the present invention, a pulse generation circuit generates a preset pulse waveform at a first output terminal according to a control signal applied to a control terminal, a first frequency division circuit that frequency divides a reference signal, a second frequency dividing circuit that divides the output of the first frequency dividing circuit; and a second output terminal that takes out the output of the second frequency dividing circuit; 1st
and the reference signal is divided by a second frequency dividing circuit and outputted from the second output terminal, and when confirming the operation, an operation confirmation signal different from that in the steady state is applied to the first output terminal, so that the reference signal is After passing through the first frequency dividing circuit, the signal is taken out as an output signal from the second output terminal without passing through the second frequency dividing circuit, and after the operation confirmation signal is removed, the signal is output from the reference signal for a predetermined time. There is obtained a pulse waveform generation circuit characterized in that a signal is extracted as an output signal from the second output terminal via the second frequency dividing circuit without passing through the first frequency dividing circuit.

Next, one embodiment of the present invention will be described in more detail with reference to the drawings.

FIG. 3 is a block diagram of an electronic clock with an alarm mechanism implemented in a semiconductor integrated circuit. A continuous pulse as represented by the waveform at point a in FIG. 8 is received at the terminal 19 and sent to the first frequency dividing circuit 22 and the first switching circuit 24. First frequency divider circuit 2
2 converts this into a continuous pulse of a predetermined period as represented by the waveform at point b in FIG. 8, and sends it to the first switching circuit 24. k in Figure 8 at a predetermined time set in advance to generate an alarm sound.
Predetermined level signals, represented as a point waveform and a point l waveform, are sent from the test speed up circuit 34 and transmitted to the first switching circuit 24 and the second switching circuit 28.

Unless the first switching circuit 24 and the second switching circuit 28 receive a signal at a predetermined level as shown by the waveform at point k and the waveform at point l in FIG.
A continuous pulse of a predetermined period as shown as the normal mode waveform at point c in FIG.
and the second switching circuit 28, the second frequency dividing circuit 26 converts it into a continuous pulse of a predetermined period as shown as the normal mode waveform at point d in FIG.
A signal of a predetermined level as represented by the normal mode waveform at point e in FIG. 8 is transmitted to the terminal 21.

On the other hand, the second frequency divider circuit 26 sends a signal of a predetermined level to the alarm control circuit 30 as represented by the normal mode waveform at point f in FIG. g in Figure 9
A signal of a predetermined level expressed as a dot waveform is received at the terminal 23, and is sent to the alarm control circuit 30.
send to When a signal at a predetermined level, as shown by the waveform at point g in the test mode in Fig. 9, goes from a high level to a low level, a signal at a predetermined level, as shown by the waveform at point i in Fig. 9, goes to the alarm generating circuit. 32, and a signal of a predetermined level as represented by the waveform 50 at point j in FIG. 9 is transmitted to the terminal 25.
and is converted into an alarm sound. In this way, the alarm mechanism of the electronic watch is achieved. To confirm the operation of this alarm mechanism, a forcible high-level signal is applied to the test speed up circuit 34 at the terminal 25 as shown by the waveform at point j in FIG. When a signal of a predetermined level (transitioning from a high level to a low level) as represented by the waveform at point g in FIG. The signal is sent to the test speed up circuit 34. In response to this signal, the test speed up circuit 34 sends a signal at a predetermined level as shown by the waveform at point k in FIG. 9 to the second switching circuit 28. Second switching circuit 28
receives a signal of a predetermined level as shown in the waveform at point k in FIG. 4, and sends continuous pulses of a predetermined period to terminal 21, as shown in the waveform at point e in FIG. Thereafter, these signals repeat the above-described operations and are converted into signals with shortened periods as shown as the normal mode waveform at point e in FIG.

Next, after the measurement of this shortened signal is completed and the forced high level signal applied to the terminal 25 is removed, the test speed up circuit 34 generates a predetermined waveform as shown in the waveform at point l in FIG. A level signal is sent to the first switching circuit 24, and at the same time, the control signal shown as the waveform at point k in FIG. 9 sent to the second switching circuit 28 is cut off. The first switching circuit 24 receives a signal of a predetermined level as shown in the waveform at point l in FIG. is sent to the second frequency dividing circuit 26.
As explained above, the signal is converted into a signal with a shortened period as shown by the waveform at point e in FIG. 8 and the waveform at point j in FIG. 9.

By measuring this shortened signal with a cathode ray tube or the like, it is possible to shorten the time required to confirm the operation, and to perform the operation confirmation completely.

In this way, according to the present invention, the operation of the frequency divider circuit can be checked in parts without requiring a measurement terminal for checking the operation, so it is possible to check the operation of the entire circuit in a short time. Become. Therefore, there is no need to increase the chip area, thereby preventing a decrease in yield or an increase in cost.

Further, since there is no increase in the number of terminals in the container, a container can be used which is correspondingly cheaper.Furthermore, operation confirmation can be easily performed in a short time, and mass productivity can be improved.

In this way, it is possible to obtain an electronic timepiece with an alarm mechanism that is low-cost and highly mass-producible.

Although the present invention has been described above regarding an electronic timepiece with an alarm mechanism, the present invention is not limited to the above, but can be similarly applied to a pulse waveform generation circuit that generates a pulse of a predetermined shape in response to a single control signal. It is.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing conventional examples, respectively. FIG. 3 is a block diagram showing one embodiment of the present invention. Fourth
5 are waveform diagrams showing the operation of FIG. 1.
6 and 7 are waveform diagrams showing the operation of FIG. 2. 8 and 9 are waveform diagrams showing the operation of FIG. 3. 1, 3, 7, 9, 11, 13, 15, 17, 1
9, 21, 23, 25... terminal, 2, 6, 12, 1
6, 22, 26... Frequency divider circuit, 4, 14, 24, 2
8...Switching circuit, 8,18,30...Alarm control circuit, 10,20,32...Alarm generation circuit, 2
2, 34...Test speed up circuit.

Claims (1)

[Claims] 1 depending on the control signal applied to the control terminal.
a pulse generating circuit that generates a preset pulse waveform at the output terminal of the circuit, a first frequency dividing circuit that divides the frequency of the reference signal, and a second frequency dividing circuit that divides the output of the first frequency dividing circuit. and a second output terminal for taking out the output of the second frequency dividing circuit, and in a steady state of operation, the reference signal is frequency-divided by the first and second frequency dividing circuits and outputted to the second output. By applying an operation confirmation signal different from that in the steady state to the first output terminal during operation confirmation, the reference signal passes through the first frequency division circuit and then passes through the second frequency division circuit. The second
The reference signal is taken out as an output signal from the output terminal of , and for a predetermined period of time after the operation confirmation signal is removed, the reference signal passes through the second frequency divider circuit without passing through the first frequency divider circuit. Second
A pulse waveform generation circuit characterized in that an output signal is extracted from an output terminal of the pulse waveform generator.