JPS6133490B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization guarantee method, and more particularly to a synchronization guarantee method for guaranteeing synchronization between devices in a system for operating graphic display terminal devices using optical cables.

When a central processing unit exchanges data with a graphic display terminal device via a communication control processing device, two modem devices are generally installed between the communication control processing device and the graphic display terminal device. A method is used in which these two modulation and demodulation devices are connected via a communication line. This data transfer method uses a graphic terminal adapter and an optical cable instead of a modem and a communication line to achieve a high data transfer rate (specifically, 9.600 baud when using a communication line and 76.700 baud when using an optical cable)
For example, a control signal (signal transmission/reception status between the communication control processing unit and the graphic terminal adapter) is sent from the graphic display terminal device via the graphic terminal adapter and the optical cable. When a synchronization error occurs and an error notification is received, the communication is considered to be impossible and the communication is terminated. Also, if there is a synchronization error in the timing signal and the signal does not change for a certain period of time, communication will be terminated in the same way.
The problem arises of closing communications.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a synchronization guarantee method that allows communication to occur without causing an abnormality on the interface signal line, that is, without generating an error even if a synchronization error occurs. This is the purpose.

To that end, the present invention is located between a central processing unit and a terminal device, and provides at least a data signal.
In a transmission system including a transmitting device and a receiving device that convert parallel signals including timing signals and control signals into serial signals and transmit the same, the transmitting device synchronizes each time one transmission unit of the parallel signal is converted into the serial signal. After detecting synchronization using the synchronization pattern, the receiving device restores and outputs the parallel signal from the serial signal, and if asynchronization is detected using the synchronization pattern, the receiving device restores the parallel signal from the serial signal and outputs the parallel signal. The signal and the control signal are held at a constant polarity indicating a non-communication state, and the timing signal is forcibly generated and output.

A specific embodiment most suitable for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a system embodying the present invention.
1 is a central processing unit, 2 is a communication control processing unit, 3-
1 and 3-2 are graphic terminal adapters, 4 is an optical cable, and 5 is a graphic display terminal device. As shown in the figure, the configuration includes a central processing unit 1, a communication control processing unit 2, a graphic terminal adapter 3-1 (hereinafter referred to as GRA ₁ ), an optical cable 4, and a graphic terminal adapter 3-2 (hereinafter referred to as GRA ₂ ). and graphic display terminal device 5 (hereinafter referred to as GDT)
) are connected in a linear relationship, and GRA ₁ and the communication control processing unit are connected to CCiTT's V35 interface (control signal D ₀ of the signal transferable signal between the GRA and communication control processing unit, timing signal D, and data Connected by signal D). Communication control processing device 2
exchanges data with GDT 5 via two GRA ₁ and GRA ₂ and optical cable 4, and even if the signal from GRA ₂ occurs out of synchronization, GRA ₁ does not detect it as an error and sends it to GDT ₅ . If the optical cable remains in a non-communication state, that is, a data error occurs on the optical cable, the GRA
sends data, but turns the control signal "on",
The timing signal is changed at regular intervals and the data signal is kept at a logical value of "1" to make it appear as if there is no communication. Therefore, according to the present invention, the communication control processing device treats the data as no signal since there is no start bit/stop bit in the data of logical value "1".

Prior to explaining the embodiments, the format of the signals used in this system will be described. FIG. 2 is a signal diagram showing the signal format. The signal is composed of 12 bits and is sent serially from GRA ₂ . In the figure, 1 bit to 4 bits, 6 bits, 8 bits and
The 10th and 12th bits _F0 to _F3 , _F4 , _F5 , F6, and _F7 are used as signals to establish synchronization, and the remaining 4 bits, that is, 5 bits, 7 bits, and 9 bits, are used as signals for establishing synchronization _. and the 11th bit are used for data as D ₀ , D ₁ , D ₂ , and D ₃ , respectively. However, D ₃ is not used.

FIG. 3 is a block diagram showing an embodiment according to the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.
10 is an asynchronous detection circuit, 11 to 18 are inverter circuits, 19 to 23 are NAND circuits, 24 is an AND circuit, 25 is an OR circuit, 26 is a counting circuit,
27 is a transmission data register, and 28 is a serial/parallel conversion circuit. In the figure, GRA ₂ 3−
The serial signal sent from 2 is serial/
The signals _F0 to _F7 for establishing synchronization among the signals shown in FIG. 2 are converted into parallel signals by the parallel conversion circuit 28 and input to the asynchronous detection circuit 10 of GRA ₁ 3-1 after completion of 12-bit reception. be done. However, the signals of F ₀ to F ₇ are “1, 0, 1, 0, 1,
0, 1, 0'', then F ₁ , F ₃ ,
The signals of F ₅ and F ₇ are transmitted to the inverter circuit 13 and
After 14, 15, 16, other F ₀ , F ₂ , F ₄ , F ₆
The signals are directly input to the AND circuit 24, respectively. The output of the AND circuit 24 is branched into three branches; one branch is input to one end of each of the NAND circuits 19 to 21, the second branch is input to the inverter circuit 18, and the second branch is input to one end of the OR circuit 25. GRA ₁ 3-1 and communication control processing unit 2 are CCiTT
Since they are connected by the V35 interface, DRA ₂ 3 with D ₀ as DR, D ₁ as ST, and D ₂ as data.
Signals D ₀ to D ₂ in Figure 2 sent from -2
are each inverter circuit 1 except for D ₁ signal.
1 and 12 to the other terminals of the NAND circuits 19 and 21, and the _D1 signal is directly input to the other terminal of the NAND circuit 20. The outputs of the NAND circuits 19 and 21 are directly input to the transmission data register 27. The output of the NAND circuit 20 is input to the transmission data register 27 via the NAND circuit 22. The output of the transmission data register 27 is input to the communication control processing device 2. The output of the inverter circuit 18 that is input to the second branch of the asynchronous detection circuit is further branched into two branches, one branch is input to the counting circuit 26, and the other branch is input to one end of the NAND circuit 22 via the NAND circuit 23. Ru. An output corresponding to the D ₁ signal among the outputs of the transmission data register 27 is inputted to the other end of the NAND circuit 23 via the inverter circuit 17 . The output of the counting circuit 26 is input to the other terminal of the OR circuit 25 to which the third branch of the output of the asynchronous detection circuit 10 is input, and the output of the OR circuit 25 is input to the transmission data register 27. When the output of this OR circuit 25 becomes "1", data is set in the transmission data register 27, and the output of the OR circuit 25 becomes "0".
When , the transmission data register 27 keeps the state of the transmission data register 27 in the previous state.
This is the control signal. The circuit is configured as described above. Synchronized signals i.e. F ₀ to F ₇
are “1, 0, 1, 0, 1, 0, 1, 0” respectively
A normal state in which a signal is input to the asynchronous detection circuit 10 will be explained using FIGS. 3 and 4. When the synchronized signal is input to the asynchronous detection circuit 10 of GRA ₁ 3-1, the AND circuit 24 outputs "1". On the other hand, the signals D ₀ to D ₂ are each input in the waveform shown as O ₁ in FIG. 4. This O ₁ shows the waveform at the point O shown in FIG. 3, and the same applies to the other P ₁ to R ₁ . For example _, to explain the waveform of _{the D1} signal at Q in FIG. 1” is input, NAND circuit 2
The output of 0 is inverted as shown in Q ₁ of the D ₁ signal in FIG. That is, in the case of synchronized signals, the signals are reversed in the NAND circuit. Therefore D ₀ and D ₂
The signals are reversed twice in inverter circuits 11 and 12, and further in NAND circuits 19 and 21, and finally
The D ₀ and D ₂ signals are sent to the transmit register 27 with their original waveforms.
leading to. On the other hand, the synchronized signal “1” is inverter 1
8, the NAND circuit 23 outputs "1" and inputs it to the NAND circuit 22. Therefore, as mentioned above, the signal is generated by the NAND circuit 22.
Q ₁ is reversed and becomes the R ₁ signal, and the D ₁ signal also reaches the transmission register 27 with its original waveform. The synchronized signal is further input as "1" to the OR circuit 25, and the OR circuit 25 outputs "1" and is input to the transmission data register 27, regardless of the input of other terminals, and as mentioned above, each of D ₀ to D ₂ A signal is set in the transmission data register 27, and the signal is sent to the communication control processing device 2. This state is a synchronized normal state.

Next, the asynchronous case will be explained below. When a signal with a synchronization difference is input to the asynchronous detection circuit 10, the output of the AND circuit 24 becomes "0", and is input to one end of each of the NAND circuits 19 to 21, and the third The signal Q ₁ at Q in the figure becomes "1" as shown in FIG. 5, Q ₁ . Similar to the pre-synchronized signal, D ₀ ,
The _D2 signal is set to “1” and sent to the transmission data register 27.
leading to. The output “0” of the AND circuit 24 is changed to “1” by the inverter circuit 18 and is input to one end of the NAND circuit 23. Therefore, the output of the NAND circuit 23 is the inverted version of the input at the other terminal. For example _, the existing D ₁ signal _{S 1} in FIG _. Q ₁ (“1”) is input and reversed, becoming R ₁ of the D ₁ signal in FIG. 5 and reaching the transmission data register 27. Therefore, the _R1 signal shown in FIG. 5 is waiting in the transmission data register 27. On the other hand, the output "0" of the AND circuit 24 is changed to "1" by the inverter circuit 18 and is input to the counting circuit 26. The counting circuit 26 receives "1", outputs "1" after the required time has elapsed, passes through the OR circuit 25, and inputs "1" into the transmission data register 27. The _R1 signal shown in FIG.
It will be sent to Like the R ₁ signals in FIGS. 4 and 5, the D ₀ signals are both "1" and the D ₁ signals are both "0" and "1" at regular intervals, thereby preventing line blockage. Since R ₂ of the D ₂ signal serving as data is fixed at "1", the communication control device 2 is in a state in which the same data is being transmitted when out of synchronization, and is in a non-communication state without being out of synchronization. Note that the D ₀ signal used here is the communication control processing unit and GRA ₁
This signal is “1” indicating that it is possible to exchange signals with
The D ₁ signal is a signal in which "0" and "1" are repeated, and the D ₂ signal is a data signal. FIG. 6 is a timing diagram when the communication control processing device receives data, and the data is received at the dotted line in the figure, that is, at the falling edge of the _D1 signal.

As is clear from the above explanation, the present invention provides a synchronization guarantee method that allows communication without showing any abnormality on the interface signal line even if a synchronization error occurs, which has many advantages in communication control using optical cables, etc. becomes.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram summarizing the present invention, FIG. 2 is a schematic diagram showing signal forms, FIG. 3 is a block diagram of an embodiment according to the present invention, FIG.
FIG. 5 shows a signal state diagram in synchronous and asynchronous cases of the present invention, and FIG. 6 shows a reception timing diagram of the communication control processing device. In the figure, 1 is a central processing unit, 2 is a communication control processing unit, 3-1 and 3-2 are graphic terminal adapters, 4 is an optical cable, 5 is a graphic display terminal device, and 10 is an asynchronous detection circuit.

Claims (1)

[Claims] 1. In a transmission system having a transmitting device and a receiving device located between a central processing unit and a terminal device and converting parallel signals including at least data signals, timing signals, and control signals into serial signals and transmitting the serial signals, the transmitting device adds a synchronization pattern for synchronization each time one transmission unit of the parallel signal is converted to the serial signal, and after detecting synchronization based on the synchronization pattern, the receiving device restores the parallel signal from the serial signal and outputs it. At the same time, when asynchronization is detected by the synchronization pattern, the data signal and the control signal are held at a constant polarity indicating a non-communication state, and the timing signal is forcibly generated and output. A synchronization guarantee method.