JPS6135629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a clearing function itself.

FIG. 1 shows a conventional semiconductor memory device, for example, a one-transistor/cell type dynamic MOS/RAM. This semiconductor memory device includes memory cells 10,
11, 12..., sense amplifier 20, 21...,
Precharge gates 30, 31..., precharge circuits 40, 41..., X decoders 50, 5
1, Y decoder 60, 61, data amplifier 70,
It is composed of data gates 80, 81, . . . , dummy cells, timing circuits, etc. (not shown). In such a semiconductor memory device, when clearing the contents, it is common to write to all cells. Therefore, it is normal for the information in each cell to be completely random, especially immediately after power is turned on, and before the storage device is accessed, a write operation called initial clear is performed on all cells to clear all cells. It was necessary to keep the data at a constant value. This requires extra hardware and extra controls.

Furthermore, in conventional storage devices, for diagnosis purposes, data is written to a specific address and then read, the expected value is compared with the read information, and the location of the failure is detected based on the results. was. However, if there is a failure in the write system circuit and writing cannot be performed, the initial clear cannot be performed as a matter of course, so even if such a diagnostic method is adopted, the results will be meaningless.

An object of the present invention is to provide an improved semiconductor memory device that eliminates these drawbacks.

To achieve the above object, a semiconductor memory device according to the present invention is capable of writing to and reading from a memory cell at an arbitrary address, and has a refresh function. a precharge control circuit that controls an output level of a precharge gate using the synchronization circuit output, a clear timing circuit that creates a clear timing using the synchronization output, and a counter that operates at the timing of the timing circuit; Either the counter output or the address from the address circuit can be selected, and a clear circuit is provided which includes a selector that selects the counter output according to the synchronization circuit output and inputs it to the X decoder, and the Y control line The contents of the storage device are cleared by simultaneously controlling the potentials of the storage device.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a reference example of a semiconductor memory device according to the present invention. This semiconductor memory device adds a clear terminal 1 and a clear circuit 2 to the conventional semiconductor memory device shown in FIG. 170.

The semiconductor memory device shown in FIG. 2 is configured such that when a clear signal is applied to clear terminal 1 from the outside, clear circuit 2 sends a clear enable signal to Y decoders 160, 161 and data amplifier 170.

During a normal write operation, the Y decoders 160 and 161 operate under control to turn on only a selected pair of data gates, for example, data gates 80 and 81, for a predetermined period of time, similar to a conventional memory device. . On the other hand, when the clear enable signal is sent from the clear circuit 2, the Y decoders 160 and 161 turn on all data gate pairs for a predetermined period of time, regardless of external read, write, refresh, etc. commands. It operates in a controlled manner. Such a decoder can be realized with a configuration similar to a known decoder with a control terminal. In the conventional semiconductor memory device shown in FIG. 1, the Y decoders 61, 61 are controlled by a timing circuit (not shown) to control the on-time of the data gate, and this point is also the same in the semiconductor memory device shown in FIG. , in the storage device of the present invention, the clear circuit 2
The difference is that when the Y decoders 160 and 161 are energized, the timing circuit controls the on-timing of the data gate regardless of an external operation command.

Next, regarding the data amplifier 170, during a normal write operation, one of the data lines 210 and 211 is set to a high potential and the other is set to a low potential according to external data, whereas the clear circuit 2 When energized, the data lines 210 and 211 are maintained in a predetermined state, for example, the data line 210 is maintained at a high potential and the data line 211 is maintained at a low potential, regardless of external data. be done.

When a refresh operation is commanded from the outside, the X address is decoded by the X decoders 50 and 51, and, for example, the X-ray 310 is energized. Then, the cells 10, 12 connected to the X-ray 310...
The contents of all the cells are read out, each data is amplified by the sense amplifiers 20, 21, etc., and the same data that was read out is rewritten into each cell. Regarding such a refresh operation, this semiconductor memory device is no different from conventional ones. However, in this memory device, when a clear signal is applied to clear terminal 1, all data gates are turned on, and furthermore, assuming that data line 210 is maintained at a high potential as described above, cell 1 , 12 . . . , etc., “1” is rewritten to all cells connected to the X line 310 (when the one with more charge is set as “1”). Therefore, after performing a refresh operation for all refresh addresses (X addresses) with a clear signal applied to the clear terminal, all cells located on the left side of the sense amplifier (where the data line is on the high potential side) “1”
Also, all cells located on the right side of the sense amplifier (where the data line is on the low potential side) are cleared to "0". Note that "1" and "0" of a cell refer to the amount of charge accumulated in the cell. data amplifier 170
is configured to be able to drive a heavy load because multiple cells are simultaneously written during clear operation.

Note that the data amplifier 170 is configured so that it does not receive a signal from the clear circuit 2, and commands a write operation to the storage device during the clear operation, so that a desired "1" or "0" can be written from outside. Clearing can also be done by providing data and scanning for all X addresses. this is,
In other words, during a normal write operation, only one pair of data gates is turned on, but when clearing, all data gate pairs are turned on and the same data is simultaneously written to all cells connected to the selected X line. That's true.

Further, the X address and activation timing at the time of clearing do not necessarily have to be given from outside the storage device, and both or one of them may be generated inside the storage device.

Next, an embodiment of the present invention will be described with reference to FIG. In this embodiment, the clear circuit 3 receives the clear signal from the clear terminal 1 and synchronizes the clear signal with the clock from the internal oscillator 5.The clear circuit 3 is cleared by the control of the synchronizing circuit 4 and the internal oscillator 5. A clear timing circuit 8 that generates the necessary timing, a counter 7 that operates according to the timing from the clear timing circuit 8, and a signal from the synchronization circuit 4 combine signals from an address circuit (not shown) and a signal from the counter 7. a selector 9 for selectively selecting the precharge control circuit 6;
Contains.

The precharge control circuit 6 can have a circuit configuration as shown in FIG. 4, for example. This circuit has terminals T ₀ connected to the synchronization circuit 4 in FIG.
It includes a terminal T ₁ connected to the control line 410 and a terminal T ₂ connected to the control line 411, MOST-Q ₀ ,
Resistor MOST - consists of R ₁ and R ₂ . Terminal T ₀
When MOST-Q ₀ is not energized, MOST-Q 0 is off, so terminals T ₁ and T ₂ are at the same potential, and the control lines 410 and 411 in FIG. 3 connected thereto are at the same potential. When a clear signal is given to clear terminal 1 and terminal T ₀ is energized, MOST-Q ₀ is turned on, so the potential of terminal T ₂ becomes lower than the potential of terminal T ₁ , and therefore the control line The potential of the control line 411 is lower than that of the control line 410.

In the semiconductor memory device shown in FIG. 3, when a clear signal is applied to the clear terminal 1 and a clear operation is started, the precharge control circuit 6 causes potential imbalance between the control lines 410 and 411, and the selector 9 is connected to the counter 7 side. After selecting the signal, the clear timing circuit 8 sends a refresh operation request signal to a timing circuit (not shown) at a predetermined period, and counts up the counter 7 at a predetermined timing. As a result, the cells 10 and 1 selected by the X decoders 50 and 51 and connected to the X-ray 410, for example,
All cells such as 2 and 2 are refreshed, but since the potential of the control line 410 is higher than that of the control line 411, the precharge potential of the Y lines 510 and 511 is that the precharge potential of the Y line 510 is higher than that of the control line 411. It is in an equilibrium state, and regardless of the memory contents of cells 10, 12, etc., the results amplified by sense amplifiers 20, 21, etc. are always "1" and fed back to the cells, and when rewriting, X-rays are emitted. “1” is written into all cells of 310. In this way, when all X-ray scanning is completed, all cells are cleared.

Note that the potentials of the control lines 410 and 411 can be controlled externally; for example, the precharge circuit may be controlled by data applied to the write data terminal of the storage device.

Further, the X address and activation timing at the time of clearing do not necessarily have to be configured to be generated internally, and both or one thereof can be given from the outside.

As described above, since the semiconductor memory device according to the present invention is equipped with a clear circuit itself, clearing can be achieved without requiring any extra hardware or control for clearing.

Furthermore, even if there is a fault in the write circuit, each cell is cleared by the device's clear circuit, so the fault in the write circuit can be detected from the fact that the read information is fixed to a known value. You can also do that.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional semiconductor memory device, Figure 2 is a circuit diagram of a conventional semiconductor memory device.
3 is a circuit diagram showing a reference example of the present invention, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of a precharge control circuit in the embodiment of FIG. 3. 1... Clear terminal, 2, 3... Clear circuit, 4
... Synchronization circuit, 5 ... Internal oscillator, 6 ... Precharge control circuit, 7 ... Counter, 8 ... Clear timing circuit, 9 ... Selector, 10, 1
1, 12... memory cell.

Claims (1)

[Claims] 1. In a semiconductor memory device that is capable of writing to and reading from memory cells at arbitrary addresses and has a refresh function, there is provided a synchronization circuit that synchronizes a clear signal from a clear terminal, and a precharge gate using the output of the synchronization circuit. a precharge control circuit that controls the output level of the synchronization circuit, a clear timing circuit that creates a clear timing based on the output of the synchronization circuit, a counter that operates at the timing of the timing circuit, and one of the counter output and the address from the address circuit. A clear circuit is provided, which includes a selector that selects the counter output based on the output of the synchronization circuit and inputs it to the X decoder, and simultaneously controls the potential of the Y control line. A semiconductor storage device characterized in that it is configured to clear the following.