JPS6135634B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for driving a charge coupled device (CCD).

Recently, CCDs have been widely used in various fields of imaging devices, for example. FIG. 1 shows a frame transfer type two-dimensional CCD device. In this frame transfer method, the light receiving section 1 converts light into electric charge;
It is made up of three regions: a storage section 2 that stores charges from the storage section 2, and a readout section 3 that reads out the charges from the storage section 2. The optical signal charge obtained by the light receiving section 1 is temporarily stored in the storage section 2, and sequentially read out line by line through the reading section 3. Transfer electrodes are provided in each of these regions to transfer optical signal charges, and are driven by four-phase pulses.
In Figure 1, φ _I1 ~ φ _I4 , φ _S1 ~ φ _S4 , and φ _R
1 to _φR4 represent four-phase electrodes in the light receiving section 1, storage section 2, and readout section 3, respectively, _φBG represents the bottom gate electrode, and _φRS represents the reset electrode, respectively. This CCD device requires 12 transfer pulses and 2 control pulses to operate one CCD. The transfer efficiency of the CCD is greatly influenced by the waveform of the transfer pulse. Generally, the transfer pulse waveform for efficient CCD operation is a waveform with a fast rise and a slow fall.
A drive circuit that can supply such transfer pulses is absolutely necessary. Furthermore, when looking at the CCD load from the drive circuit, the CCD can be treated as a capacitive load. For example, vertical
CCD with 512 x 340 horizontal pixels has 1500~
It has a capacitance of 5000pF (picofurad).

The configuration of the above drive circuit is a CMOS that can charge up to the power supply voltage and discharge down to ground level.
(complementary insulated gate field effect transistor) circuit is effective. This CMOS circuit allows the drive circuit and logic circuits necessary for CCD operation to be constructed on the same chip. Here, an example of a CCD drive circuit using a CMOS inverter circuit is shown in FIG.
In the figure, transistor _Q1 is a P-channel MOS
-FET, transistor _Q2 is N-channel MOS-
In FET, these transistors Q ₁ , Q ₂ ,
It constitutes a CMOS inverter circuit. Further, the load capacitance (C) connected between the output terminal (OUT) and the ground represents a transfer electrode. In this drive circuit, the factor that determines the rise time of the circuit is the time constant due to the on-resistance of transistor Q ₁ and the load capacitance (C〓), and the factor that determines the fall time is the on-resistance of transistor Q ₂ and the load It is a time constant due to the capacitance C〓.

The element design of the drive circuit shown in Figure 2 above is expressed by the following equation (1) ~
It is given by equation (3).

τ _o = t _r /α _o or t _f /α _o ...(2) α _o = |V _th |-0.1V _p /V _p -|V _th | +1/2・ln[20(1-| V _th |/V _p )−1]
...(3) Here, W is the channel width of the MOS-FET, and L is the channel width of the MOS-FET.
Channel length of MOS-FET, C〓 is load capacity, ε _p
x is the dielectric constant of the gate oxide film, t _px is the thickness of the gate oxide film, μ is the mobility of the MOS-FET, and V _th is the MOS
-FET threshold voltage, V _p is the charging voltage of the load capacitor, _tr is the rise time of the output waveform, t _f is the fall time of the output waveform, and t _r and t _f are both the 10% value of the output waveform and represents the 90% value.

Now, let's design a circuit that drives the light receiving section 1 and the storage section 2. As an example, assume that the CCD electrode capacitance is C = 500 [pF] per unit. Also, the charging voltage V
_p = 12 [V], the rise time and fall time of the transfer pulse waveform are t _r = 50 [ns], t _f = 300 [ns], respectively.
shall be. In addition, dielectric constant ε _px = 3.45×10 ^-13 [F/
cm], thickness t _px = 1200 [Å], P channel and N
The threshold voltages of the channel transistors are −1.3 [V] and 1.3 [V], respectively, and the P channel and N
Channel MOS-FET mobility μ is 180 respectively.
[cm ² /V·sec], 400 [cm ² /V·sec]. Here, P channel and N channel MOS-FET
If the channel lengths of both are 10 μ [1 μ = 10 ^-4 cm], the channel width/channel length of MOS-FET is (1)
From the formula, in P channel [W/L] _P = 17110/
10. In N channels, (W/L) _N = 3850/10.

In this way, the MOS-FET of the drive circuit that drives the light receiving section 1 and the storage section 2 has a very large size, and the electrodes φ _I1 to φ _I4 and φ _S1 shown in FIG.
~8 drive circuits are required corresponding to φ _S4 . Therefore, if these circuits were to be constructed on the same chip, the overall chip size would become even larger, causing yield and packaging problems. From this point of view as well, it is desirable to realize a drive circuit with a small chip size.

Next, consider the circuit that drives the reading section 3. The electrode capacitance of the reading section 3 is smaller than that of the light receiving section 1 and the storage section 2. However, since the operating frequency is high, power consumption becomes a problem in the circuit that drives the reading section 3. Let us calculate the power consumption when the reading section 3 is driven by the circuit shown in FIG. For example, the electrode capacitance per unit C = 150 [pF], the operating frequency is 6
[MHz] and charging voltage V _p is 12 [V],
Power consumption is determined by ・C〓・(V _p ) ²¹³⁰
[mW].

In addition to the above-mentioned power consumption, a problem with the circuit that drives the reading section 3 is the power consumed by charging and discharging the capacity of the drive circuit itself. In order for the drive circuit to meet the given specifications, a MOS-FET with certain dimensions is required, and there is a capacitance determined by the geometric dimensions of the MOS-FET. The capacitance possessed by this drive circuit itself is determined by the P channel MOS-FET and the N
There are gate capacitance and diffusion capacitance of channel MOS-FET. The power consumed by the gate capacitance is assumed to be the power consumed by the preceding inverter for driving the circuit shown in FIG. 2.

Next, the power consumed in charging and discharging these gate capacitances and diffusion capacitances will be determined. for example,
Load capacitance C=150 [pF], output waveform rise time t _r and fall time t _f are 16 [ns] and 40, respectively.
[ns], the charging voltage V _p is 12 [V], and the other design parameters are the same as those used in the light receiving section 1 and storage section 2 described above. When the dimensions of the MOS-FET are determined in accordance with equations (1) to (3) above, the P-channel MOS-FET becomes (W/
L) _P = 4810/10, and (W/L) _N = 866/10 for N-channel MOS-FET. If we calculate the gate capacitance and diffusion capacitance from the geometric dimensions of this MOS-FET, they will total approximately 45 [pF], and the power consumed in charging and discharging this capacitance will be 40 [mW].

Therefore, the power consumed by the drive circuit shown in Figure 2 is the power consumed by charging and discharging the external load capacitor (130 mW) and the power consumed by charging and discharging the capacity owned by the internal circuit itself (40 mW). ) total 170
[mW]. In other words, the power consumed by charging and discharging the capacity owned by the drive circuit itself corresponds to about 24% of the total power consumed.

The circuit that drives the reading section 3 in this way consumes a large amount of power, and moreover, the circuit that drives the readout section 3 consumes _a large amount of power.
This reading section 3 requires four drive circuits corresponding to _R4 . Therefore, if all of these drive circuits were to be constructed on the same chip, the overall power consumption would become even greater and may exceed the allowable range of the package. From this point of view, it is desired to realize a circuit that reduces the power consumed by the capacity of the drive circuit itself as much as possible and reduces the power consumed as a whole.

The present invention was made in view of the above circumstances, and
When driving a CCD with a large number of pixels by configuring a circuit with first and second CMOS inverter circuits and bipolar transistors driven by these first and second CMOS inverter circuits, the rise time or It is an object of the present invention to provide a charge-coupled device drive circuit that can provide a transfer pulse waveform with a fast fall time, has a small chip size, and consumes little power.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows the CCD drive circuit of the present invention. In the figure, 11 is a P _channel MOS-FET Q ₁ and N
Channel MOS - 1st CMOS consisting of FET Q ₂
Inverter circuit, 12 is a similar P channel
This is a second CMOS inverter circuit consisting of MOS-FET Q ₃ and N-channel MOS-FET Q ₄ , and the input terminals of these first and second CMOS inverter circuits are commonly connected to the circuit input terminal IN. .
Further, Q ₅ is an NPN type bipolar transistor, and the base of this transistor Q ₅ is connected to the first
The emitter is connected to the output terminal of the inverter circuit 11, the emitter is connected to the output terminal of the second inverter circuit 12 and the circuit output terminal OUT, and the collector is connected to the power supply _VDD . Also, this circuit output terminal OUT
A load capacitor C is connected between the ground and the ground.

To explain the operation of the above drive circuit, the input terminal
When a low level “0” signal is applied to IN, transistors Q ₁ and Q ₃ are turned on, and transistors Q ₂ and Q ₄ are turned on.
is turned off. When the transistor _Q1 turns on, current flows from the power supply _VDD to the base of the NPN transistor _Q5 through the transistor _Q1 ,
This transistor _Q5 is turned on. Therefore, the charging current flows from the power supply V _DD through the transistors Q ₃ and Q ₅ to the load capacitor C. At this time, the on-resistance of the NPN transistor Q ₅ is lower than that of the transistor Q ₃ which is a MOS-FET, so the charging current is large. A portion will flow to transistor _Q5 .

Normally, the characteristics of the NPN transistor _Q5 include, for example, a low power transistor, a collector-emitter saturation voltage V _{CE (sat)} of about 0.2 to 1.5 (V). Also, the base current of NPN transistor _Q5 is
Since it is supplied from the power supply V _DD through the MOS transistor Q ₁ , the output voltage of the NPN transistor Q ₅ is determined by the voltage drop caused by the MOS transistor Q ₁ and the base-emitter saturation voltage of the NPN transistor Q ₅ (approximately 0.6~ _0.7V )
It will be lower than _D. On the other hand MOS transistor Q ₃
serves to compensate for the drop in output voltage caused by the NPN transistor _Q5 , and the output capacitance is charged to the power supply voltage _VDD by the transistor _Q3 . Therefore, the circuit element size of the MOS transistor _Q3 can be smaller than the element size of the circuit shown in FIG. 2 described above, making it possible to reduce the chip size. Furthermore, since most of the charging current flows through the NPN transistor _Q5 , the output waveform can have a steep rise characteristic even with a large load capacity.

Next, when the input power is at a high level "1" (V _DD ), transistors Q ₂ and Q ₄ are turned on, and transistors Q ₁ and Q ₃ are turned off.
By turning on transistor _Q2 , NPN
The charge stored in the base of transistor _Q5 is discharged through transistor _Q2 , turning off NPN transistor _Q5 . On the other hand, by turning on the transistor _Q4 , the charge accumulated in the load capacitance C is discharged through the transistor _Q4 . At this time, the fall time of the output waveform is
It is determined by the time constant of the on-resistance of _Q4 and the load capacitance C〓. Therefore, by appropriately designing the size of the transistor _Q4 for a given load capacitance C, a desired falling characteristic can be obtained.

Next, the effect of improving the rise time of the output waveform in the circuit of the above embodiment will be explained by comparing it with a conventional circuit (FIG. 2). 4a and 4b are experimental circuits of the circuit shown in FIG. 2 and their input/output waveform diagrams, and FIGS. 4c and d are experimental circuits of the circuit of the present invention shown in FIG. 3 and their input/output waveform diagrams. be. A comparison of the output waveforms shown in Figures 4b and 4d shows that the rise time of the circuit shown in Figure 4c is very fast, about 1/10 of the rise time of the circuit shown in Figure 4a. I know that there is. Further, FIG. 5 shows the effect of improving the rise time according to the present invention through another experiment. In other words, if the circuit of FIG. 5a were to achieve the same rise time as the output waveform shown in FIG. 4d with the circuit configuration of FIG. This means that you will need more than one. From the experimental results shown in FIGS. 4c and d and FIGS. 5a and 5b, it can be seen that the rise time improvement effect of the present invention is approximately 10 times greater.

Based on the above experimental results, the third
Let's consider the chip size when driving the light receiving section and storage section using the circuit shown in the figure. Here, the channel width/channel length of MOS-FETQ ₃ in Figure 3 is approximately 1/10 of the value designed in Figure 2 (W/L) _P =
It becomes 1710/10. However, in the circuit of FIG. 3 according to the present invention, most of the charging current flows through the NPN transistor _Q5 , so the size of the MOS-FET _Q3 may be smaller than (W/L) _P = 1710/10. .
The circuit shown in FIG. 3 of the present invention has an increased number of elements compared to the conventional circuit shown in FIG. 2 by adding new MOS-FETs _{Q 1} and Q ₂ and an NPN transistor Q ₅ .
The chip size with the circuit configuration of FIG. 3 can be reduced to about 1/10 of that of FIG. 2.

Similarly, let us consider the power consumption when driving the reading section (FIG. 1, 3). The circuit in Figure 3
The size of MOS-FET Q ₃ is approximately 1/10 of the conventional MOS-FET Q ₁ in the circuit shown in Fig.
-The size of FET Q ₄ is compared to the conventional MOS shown in Figure 2-
If the value is the same as FETQ ₂ , the MOS-FET in Figure 3
The size of Q ₃ and Q ₄ is (W/L) _P = 480/1
0, (W/L) _N = 866/10. These MOS-
The capacitance required by FETs Q ₃ and Q ₄ is approximately 15 [pF] due to their geometric dimensions. The power consumed in charging and discharging this capacity is 13 [mW], and the load capacity C
Including the power consumption due to charging and discharging (130mW as in the design example above), the total is 143
[mW]. That is, MOS-FETQ ₃ , Q ₄
The power consumed by charging and discharging the capacity owned by the battery is approximately 9% from the above 143mW. In addition, here, for simplicity, it is shown in Figure 3.
The power consumed by MOS-FETQ ₁ , Q ₂ and NPN transistor Q ₅ is ignored. In addition, the power consumed by the entire circuit in Figure 3 is MOS-FET.
The power consumption of Q ₁ , Q ₂ and NPN transistor Q ₅ must be considered. However, from a comparison with the conventional circuit shown in Fig. 2, the MOS of the circuit shown in Fig. 3 is
Focusing on the power consumed by FETQ ₃ and Q ₄ , in the circuit shown in Figure 3, most of the charging current flows to the NPN transistor Q ₅ , so the size of MOS-FETQ ₃ is the above value (W/L) _P It may be smaller than =480/10. Therefore, the proportion of power consumed by the capacity possessed by MOS-FETs Q ₃ and Q ₄ is equal to the above value 9.
It can be expected that it will be even smaller than [%].

In the circuit shown in FIG. 3 described above, the NPN transistor _Q5 can be formed on the same substrate without changing the CMOS manufacturing process. That is, when considering a CMOS structure using an N-type semiconductor substrate, the collector of the NPN transistor _Q5 is the above-mentioned N-type semiconductor substrate, the base is the P-well layer formed on this N-type semiconductor substrate, and the emitter is connected to this P-well layer. Formed N ⁺
By making it a diffusion layer, NPN transistor
_Q5 can be formed.

FIG. 6 shows a CCD drive circuit according to another embodiment of the invention. The circuit shown in FIG. 6 is intended to slow down the rise time and quicken the fall time of the output waveform. This circuit is similar except that a PNP transistor _Q'5 is used in place of the NPN transistor _Q5 of FIG. 3 described above. The base of this PNP transistor _Q'5 is the first CMOS
At the output end of the inverter circuit 11, a second emitter is connected.
The collectors of the output terminals of the CMOS inverter circuits 12 are respectively connected to ground. This sixth
The circuit operation shown in the figure is that the input terminal IN is set to low level “0”.
When an input voltage of Q ₁ ,
Q ₃ turns on, transistors Q ₂ , Q ₄ and
PNP transistor _Q'5 is turned off. When the transistor Q ₃ is turned on, charging current flows from the power supply V _DD to the load capacitor C through the transistor Q ₃ . Next, when the input voltage applied to the input terminal IN is at a high level "1" (V _DD ), transistors Q ₁ and Q ₃ are turned off, and transistors Q ₂ and Q ₄ and PNP transistor Q' ₃ are both turned on. Become. Therefore, the charge stored in the load capacitor C is discharged through the transistor _Q4 and the PNP transistor _Q'5 . At this time, since the on-resistance of PNP transistor Q′ ₅ is lower than that of MOS transistor Q ₄ , most of the discharge current flows through PNP transistor Q′ ₅
It will flow to Therefore, the fall time of the output waveform is fast and steep characteristics can be obtained.

In the circuit shown in FIG. 6 described above, the PNP transistor _Q'5 can be formed on the same substrate without changing the CMOS manufacturing process. In other words, when considering a CMOS structure with a P-type semiconductor substrate, a PNP transistor
The collector of _Q'5 is the P-type semiconductor substrate mentioned above, the base is the N-well layer formed on this P-type semiconductor substrate, and the emitter is the P ⁺ diffusion layer formed on this N-well layer. ' ₅ can be formed.

In the above CCD drive circuit, as shown in Fig. 1,
When driving a CCD device, a transfer pulse waveform with a fast fall time and a slow rise time can be applied to the light receiving section 1, storage section 2, and readout section 3.
Improves the efficiency of CCD transfer.

As explained above, according to the CCD drive circuit of the present invention, since the load is driven through a fast bipolar transistor, the rise time or fall time of the output waveform can be made faster. Therefore, the number of pixels is relatively large.
Not only can the CCD be driven, but the rise time or fall time of the CCD transfer pulse can be made faster. Furthermore, since most of the charging or discharging current is made to flow through the bipolar transistor, the MOS transistor can be made smaller and the chip size of the drive circuit can be reduced. Furthermore, since the self-capacitance of the drive circuit can be reduced, power consumption can be significantly reduced. Furthermore, since bipolar transistors can be formed on the same substrate without changing the CMOS manufacturing process, they have the advantage that there are no inconveniences in circuit manufacturing.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a general frame transfer CCD device, and Figure 2 is a conventional CCD.
FIG. 3 is a block diagram of a CCD drive circuit according to an embodiment of the present invention, and FIG. 4 is a diagram for comparing the circuit of the present invention with a conventional circuit. Figures a and b show an experimental circuit diagram of a conventional circuit and its input/output waveforms, Figures 4c and d show an experimental circuit diagram of the circuit of the present invention and its input/output waveforms, and Figures 5a and 5.
b is P in the conventional experimental circuit shown in Figure 4a.
A circuit diagram and its input/output waveform diagram when ten channel MOS-FETs are connected in parallel, and FIG. 6 is a configuration diagram of a CCD drive circuit according to another embodiment of the present invention. 11...First CMOS inverter circuit, 12...Second CMOS inverter circuit, _Q1 , _Q3 ...P channel MOS-FET, _Q2 , _Q4 ...N channel MOS-
FET, _Q5 ...NPN transistor, _Q'5 ...PNP transistor, C〓load capacitance.

Claims (1)

[Claims] 1. Each transistor is composed of complementary insulated gate field effect transistors, the input terminals of each transistor are connected in common, the source of each P-channel transistor is connected to a first power supply, and the source of each N-channel transistor is connected to a first power supply. first and second inverter circuits connected to a second power supply, a base connected to the output terminal of the first inverter circuit, an emitter connected to the output terminal of the second inverter circuit, and a collector connected to the output terminal of the second inverter circuit. a bipolar transistor connected to the first power supply or the second power supply,
A drive circuit for a charge-coupled device, characterized in that the charge-coupled device is driven by an output terminal signal of a second inverter circuit. 2. The drive circuit for a charge-coupled device according to claim 1, wherein the bipolar transistor is an NPN transistor, and a collector thereof is connected to a first power source. 3. The field effect transistor is formed on the N substrate, and the bipolar transistor has the N substrate as the collector, the P well layer formed on the N substrate as the base, and the N ⁺ diffusion layer formed on the P well layer as the emitter. 2. A drive circuit for a charge-coupled device according to claim 1, wherein the drive circuit is of an NPN type. 4. The drive circuit for a charge-coupled device according to claim 1, wherein the bipolar transistor is a PNP transistor, and a collector thereof is connected to a second power supply. 5. The field effect transistor is formed on a P substrate, and the bipolar transistor has the P substrate as a collector, the N well layer formed on the P substrate as a base, and the P ⁺ diffusion layer formed on the N well layer as an emitter. 2. A drive circuit for a charge-coupled device according to claim 1, wherein the drive circuit is of a PNP type.