JPS6136389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a planar double-diffused vertical insulated gate field effect transistor.

FIG. 1 is a sectional view of a conventional planar type double diffusion type vertical insulated gate field effect transistor, and FIG. 2 is a top view thereof as seen from the - line. The illustrated example shows an N channel type case, in which N
A semiconductor substrate 2 constituting a type drain region 1 is provided, and a P-type base region 3 and an N-type source region 4 are formed facing the surface 1a of this region 1, that is, one main surface of the substrate 2. . These base region 3 and source region 4 have at least the edge on the side constituting the gate portion in common and are sequentially diffused by so-called double diffusion through a diffusion window of a diffusion mask made of SiO ₂ , for example. It is formed by Furthermore, prior to the diffusion of these regions 3 and 4, a base frame region 5 is formed in contact with the bottom of at least a portion of the base region 3 by, for example, selective diffusion. The base frame region 5 is provided with an annular outer frame portion having an appropriate shape such as a square ring shape, and an inner frame portion having a comb-like shape or a lattice shape in a portion surrounded by the outer annular frame portion. The base region 3 is selectively formed by the above-mentioned double diffusion method so that the frame region 5 protrudes inwardly facing each other along the mutually opposing portions of the outer circumferential annular portion and the inner frame portion. Then, the source region 4 is selectively diffused by a shallower diffusion than the base region 3.

In this way, the surface 1a of the drain region 1 faces the portion surrounded by the base region 3, and the drain region 1 on the surface of the base body
and source region 4 are arranged to face each other with base region 3 interposed therebetween, and a gate portion is formed in this opposing portion. That is, a gate insulating layer 6 made of SiO ₂ having a required thickness is deposited on the base region 3 sandwiched between the source region 4 and the drain region 1.
A gate electrode 7 is deposited on top of this.

Further, on the opposite side of the source region 4 from the gate portion, a source electrode 8 is ohmicly deposited so as to extend over the adjacent source regions 4, including over the base region 3 and its frame region 5. To take out the electrode from the rain region 1, a high concentration region 9 is provided on the other main surface side of the substrate 2, and a drain electrode (not shown) is arranged here. D, G and S are drains, respectively;
Gate and source terminals are shown.

The insulated gate field effect transistor having such a structure has a planar structure and has the advantage that it can be mass-produced. Furthermore, since the base region 3 and source region 4 have a so-called double diffusion type structure, the channel length can be defined by the difference in the depth of diffusion between the two, so a sufficiently small channel length can be obtained, and the high frequency characteristics can be improved. You can measure your improvement. Furthermore, by adopting a vertical structure, it is possible to configure a field effect transistor with so-called triode characteristics, but the above-mentioned structure has the disadvantage that secondary breakdown may occur. There is.

That is, in the device having the above-mentioned structure, a depletion layer is formed in each grid-like or comb-like base region by applying a reverse voltage between the base region and the drain region. Since it spreads within the region from both sides, the electric field inside the base is relatively weakened and its withstand voltage is high. , its pressure resistance is easily broken. Now, for example, in Fig. 2, there is a symbol A.
Considering the case where breakdown occurs at the point shown by , the current due to this plater down flows to the source electrode 8 following the path shown by the broken line B.
Therefore, if a distributed resistance R exists in this path B, a voltage drop will occur with the flow of this breakdown current, and this will cause a voltage drop in the base region 3.
A portion of the PN junction between the drain region 1 and the source region 4 is forward biased, and the drain region 1 and the base region 3 are forward biased.
A parasitic NPN transistor is generated by the source region 4 and the source region 4, and this transistor is turned on by the current injected from the base region 3 to the source region 4. That is, a two-state breakdown occurs.
That is, the drain-source voltage V _DS -drain current I _D characteristic is as shown in FIG.

The present invention is intended to effectively avoid the occurrence of this secondary breakdown in the semiconductor device as described above.

FIGS. 4 and 5 show a sectional view of an example of the device of the present invention and a top view thereof taken along the line V-V. The illustrated example is applied to a case having an N-channel field effect transistor configuration similar to that explained in FIGS. 1 and 2, and in FIGS. Corresponding parts are given the same reference numerals.

In the present invention, the first semiconductor region of the first conductivity type, in this example, the N type, that is, the drain region 1
selectively a second conductivity type, that is, a P-type second semiconductor region, that is, a base region 3, facing the surface 1a of the
A double diffusion region with a third semiconductor region, ie, source region 4, of the first conductivity type, ie, N type, which is shallower than this, is provided. Also, in this case, as explained in FIGS. 1 and 2, for example, the outer peripheral frame part has an annular pattern and the inner frame part has a bent pattern shape such as a lattice shape or a comb tooth shape existing inside the outer peripheral frame part. A frame area 5 of a base area 3 is provided. Further, as described above, a gate electrode 7 is provided on the second semiconductor region 3 between the first and second semiconductor regions 1 and 4 via a gate insulating layer 6, and a drain electrode (not shown) is provided on the surface of the region 1. Electrodes are arranged. In particular, in the present invention, the outer peripheral edge of the base region 3, that is, the frame region 5
Along the entire circumference of the outer peripheral edge 5a of the base region 3 or region 5, as shown with diagonal lines in FIG.
An electrode 10 is ohmicly deposited thereon and given the same potential as the source region 4. For this purpose, for example, the electrode 10 is brought into contact with the ohming, at least in part, over the outer source region 4 . Alternatively, as shown in FIG. 5, electrode 10 may be deposited in ohmic contact on region 5 or regions 5 and 3, and electrically connected to source electrode 10 by an external conductor. You can also do it.
Further, if necessary, a layer may be formed on the surface of the base body 2 so as to span the entire circumference of the peripheral edge 5a of the region 5.
As shown in FIG. 6 or 7, an extension of the electrode 10 or the gate electrode, or an electrode electrically connected to the gate electrode 7 is extended through an insulating layer 11 for surface passivation such as SiO _{2 .} It is also possible to further improve the withstand voltage by substantially widening the depletion layer from the PN junction in the peripheral portion 5a by the electric field effect caused by the source or gate voltage applied thereto.

As described above, according to the present invention, the peripheral edge of the base region and the source region are made to have the same potential, so even if breakdown occurs on the peripheral surface 5a, this will prevent the base from breaking down as described at the beginning. Since the phenomenon in which a forward voltage is applied to the PN junction between the region and the source region can be avoided, the phenomenon of secondary breakdown as shown in FIG. 3 can be effectively avoided.

[Brief explanation of the drawing]

FIG. 1 is an enlarged sectional view of an example of a conventional semiconductor device, FIG. 2 is a sectional view along the - line, and FIG. 3 is a characteristic curve diagram for explaining secondary breakdown.
FIG. 4 is an enlarged sectional view of one example of the device of the present invention, FIG. 5 is a top view taken along the line V-V, and FIGS. 6 and 7 are enlarged sectional views of other examples of the device of the present invention. 1 is a first semiconductor region, 3 is a second semiconductor region, 4
1 is a third semiconductor region, 5 is a frame region of the second semiconductor region, 2 is a semiconductor substrate, 6 is a gate insulating layer, 7 is a gate electrode, 8 is a source electrode, and 10 is an electrode.

Claims (1)

[Claims] 1. A second semiconductor region of second conductivity selectively facing the surface of the first semiconductor region of first conductivity type, and a third semiconductor region of first conductivity type shallower than the second semiconductor region.
a heavy diffusion region; and a gate portion in which a gate electrode is deposited on the second semiconductor region between the first and third semiconductor regions via a gate insulating layer; contacting a fourth semiconductor region of the second conductivity type consisting of an annular outer peripheral frame portion and a comb-like or lattice-like bent pattern portion surrounded by the annular outer peripheral frame portion; A semiconductor device having an electrode electrically short-circuited to the third semiconductor region along the entire outer periphery.