JPS6138866B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor memory element having an SOS MOS FET structure in which charges are injected into a floating substrate and the substrate bias effect is utilized.

An island-shaped silicon semiconductor layer is formed on an insulating substrate such as sapphire, and a MOS FET is formed on the silicon layer.The device shown in FIG. ) has been proposed as a cell. In this figure, 10 is a sapphire substrate, 12 is a low impurity concentration p-type silicon layer formed in the form of an island on the substrate, 14 is a gate insulating film formed on the silicon layer, and 16 is a polycrystalline silicon layer further formed on it. Gate electrodes 18 and 20 were formed on the floating silicon substrate 12.
These are n ⁺ type source and drain regions, and these constitute an n-channel silicon gate MOS field effect transistor (FET). This MOS
In the FET device, a positive voltage is applied to the gate electrode 16 to form an n-inversion layer, that is, a channel, on the surface of the lower substrate of the gate oxide film 14.
If a voltage is applied between 8 and 20 to cause a current to flow, and then the positive voltage applied to the gate electrode 16 is suddenly brought to zero, the channel will naturally disappear and the current will be cut off. The flowing charges, in this case electrons, are injected into the substrate 12.
This is called a charge pumping phenomenon. Electrons injected into the substrate 2 due to this charge pump phenomenon recombine with holes in the substrate 12 and disappear, but as a result, the number of holes in the substrate 12 decreases (in this device, the substrate concentration is 10 ¹⁶ The depletion layer at the source/drain ¹⁸ , 20 junction expands, and the potential of the substrate 12 decreases to the negative side. When the substrate becomes negative, the threshold voltage V _th of this MOS FET is driven to the enhancement side. Therefore, if we look at the current that flows when a voltage is applied between the source and drain, we can see that if charge pumping is performed (for example, information "1" is written), and if it is not performed (for example, information "0" is written). ), the drain current becomes smaller, and it is possible to determine whether the memory contents of the MOSEET are "1" or "0" based on the magnitude of this current. Use Avalanche Breakdown to erase the memory contents. That is, reading is performed by applying approximately +5V to the drain 20, but for erasing, this is increased to approximately +16V to cause avalanche breakdown near the drain. As a result, electron and hole pairs are generated, the electrons are absorbed by the drain at positive potential, and the holes are injected into the substrate 12, returning the negatively charged substrate 12 to zero potential. When excessive holes are injected into the substrate, the substrate becomes at a positive potential, which forward biases the pn junction formed between the substrate and the source, causing the holes to flow out to the source, which is at zero potential. Therefore, there is no excessive injection of holes into the substrate. Details of this memory element can be found in Japanese Patent Application Laid-Open No. 54-5635, 1978 IEEE IEDM
Disclosed in Extended Abstracts 146, etc.

It is considered that the charges injected into the substrate 12 are stored in the gate capacitance Cox and the junction capacitance C _J between the source, drain and the substrate, as shown in FIG.
In terms of an equivalent circuit, the capacitance C _J created by the substrate 12, the source, and the drains 18 and 20 includes a pn junction (shown as a diode) D created by the substrate and the source and drain in parallel, and the semiconductor of the SOS structure element. Since the layers have many defects, a further low resistivity R will be attached in parallel to them. The charge is discharged by the resistor R, and the time constant τ ₀ of this discharge is τ ₀ = (Cox +
2C _J )·R/2, specifically about 100 [μS] when the epitaxial growth layer 12 is about 1 [μ]. In other words, this memory element has a short storage time of about 100 [μS] in terms of time constant, and must be refreshed in short cycles.

The present invention aims to improve these points and make it possible to retain write charges for a long time.The present invention is characterized by an island-like single conductivity type semiconductor layer epitaxially grown on an insulating substrate. opposite conductivity type source,
A field effect transistor is configured by forming drain regions separated from each other and depositing a gate electrode on a semiconductor layer between the source and drain regions via an insulating film. This is blocked by a voltage and a carrier is injected into the semiconductor layer, and the semiconductor layer potential changed by this carrier injection changes the threshold voltage of the transistor, and a current is passed between the source and drain to increase this threshold voltage. In a semiconductor device that reads stored information by detecting voltage changes, the thickness of the semiconductor layer is selected to be 3 [μm] or more.

In order to increase the time constant, as is clear from the above equation, it is possible to increase the gate capacitance Cox, increase the source-drain junction capacitance C _J , or increase the leakage resistance R. But the gate capacitance Cox
This can be increased by reducing the thickness of the gate insulating film 14 and increasing the area of the gate electrode, but the thickness of the gate insulating film 14 is 200 to 300 mm.
The limit is about [Å], and it is impossible to make it thinner than this in terms of dielectric strength, and since the area affects the degree of integration, it is not a good idea to make it larger. The same applies to the source and drain junction capacitances, and increasing the source and drain area will reduce the degree of integration. Therefore, a preferable method is to increase the leakage resistance R.

Such leakage resistance R corresponds to the energy generation current in the depletion layer of the source and drain parts, and if there are many crystal defects, the lifetime of the carrier will be short, the current will be large, and the resistance R will be small. Become.
In the SOS structure, the closer the semiconductor layer is to the sapphire substrate, the worse the crystallinity becomes, and the farther away it is, the better the crystallinity becomes. Conventionally, the thickness of the semiconductor layer in SOS base is 1.0
[μm], currently the standard is 0.6 [μm],
At this level, the depth of the source and drain diffusion layers is 0.3 [μm], and the depth of the depletion layers 18a and 20a is 0.3 [μm].
If it is 0.5 [μm], the depletion layer will extend to the vicinity of the surface of the sapphire substrate, which has poor crystallinity, and its lifetime will be shortened.

Therefore, in the present invention, the thickness of the silicon layer 12 is set to 3.
[μm] or more. In this way, the lifetime is improved exponentially; when the thickness of the silicon layer is 1 [μm], it is about 1 [n sec], but when the thickness of the silicon layer is 3 [μm], it is about 100 [n sec]. , it is improved by about two orders of magnitude.

Further, leakage current can also be suppressed by operating the device at a low temperature. That is, the leakage current J _R is expressed as J _R ≈qn _i W/τ _e ∝ni _∝exp (-Eg/2kT). Here, q is the electron charge, n _i is the carrier concentration of the intrinsic semiconductor, W is the depletion layer width, τ _e is the effective lifetime, Eg is the forbidden band width, k is Boltzmann's constant, and T is the absolute temperature. As is clear from this equation, when the temperature T is lowered (reduced), the carrier concentration n _i decreases, and the current J _R decreases. It is easy to reduce the temperature to below 90 [〓] by cooling it with easily available liquid nitrogen, which makes it possible to reduce the temperature to room temperature (300
The current J _R when cooling to 90 [〓] is _{J R /} J _R '≒2×10 ^-22 , which is a value that can be almost ignored.

As described above, according to the present invention, the lifetime of a carrier injection type memory element into a floating substrate can be extended, and the refresh period can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a memory element to which the present invention is applied, and FIG. 2 is an equivalent circuit diagram thereof. In the drawing, 10 is a sapphire substrate, 12 is a silicon layer, 18 and 20 are source and drain regions, 14 is an insulating film, and 16 is a gate electrode.

Claims (1)

[Claims] 1. Source and drain regions of opposite conductivity types are formed separated from each other in an island-shaped semiconductor layer of one conductivity type epitaxially grown on an insulating substrate, and on the semiconductor layer between the source and drain regions. A current is passed through the source and drain of a field effect transistor, which is constructed by depositing a gate electrode through an insulating film, and is interrupted by a gate voltage to inject a carrier into the semiconductor layer. In a semiconductor device, the threshold voltage of the transistor is changed depending on the semiconductor layer potential changed by the change in the semiconductor layer, and a current is passed between the source and drain to detect this threshold voltage change and read stored information. A semiconductor device characterized in that the thickness is selected to be 3 [μm] or more. 2. The semiconductor device according to claim 1, wherein the semiconductor device operates at a temperature of 290 [〓] or less.