JPS623588B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor memory device having a memory cell in which information is written by accumulating charges in a floating semiconductor substrate by charge pumping.

Conventionally, the type of semiconductor memory device shown in FIG. 1 has been known.

In the figure, 1 is a single crystal insulating substrate such as sapphire, 2 is an epitaxially grown p-type silicon semiconductor layer, 3 is a gate insulating film of silicon dioxide, and 4 is a silicon dioxide gate insulating film.
5 represents a gate electrode, 5 represents an n ⁺ type source region, 6 represents an n ⁺ type drain region, and V _G represents a power source.

To write information in this device, after grounding the source and applying a positive voltage V _DD to the drain, a positive voltage equal to or higher than the threshold voltage Vth is applied to the gate electrode 4 to remove the voltage below the gate insulating film 3. Semiconductor layer 2 on the side
A channel is formed on the surface of the cell, and then the gate voltage is suddenly lowered below the threshold voltage Vth. Then,
Due to the charge pumping effect, some of the electrons in the channel enter the semiconductor layer 2, which is in an electrically floating state, and stay there. The voltage applied to the gate electrode 4 is preferably applied repeatedly in a pulsed manner. By the above operation, the floating semiconductor layer 2 is biased negatively with respect to the source region 5. At this time, since the bias is a reverse bias with respect to the p-n junction between the semiconductor layer 2 and the source region 5, the inside of the semiconductor layer 2 is maintained as being negatively biased with respect to the source region 5. This state is
When a back gate bias is applied to the MIS FET and the threshold voltage Vth becomes high, when a voltage V _DD is applied to the drain and a flowing current is detected, the floating semiconductor layer 2 is connected to the source region 5. The amount of current decreases when compared with the state before charge pumping, that is, when the potential is equal to that of the current state. Therefore, with this, information “1”
Alternatively, "0" is written.

Further, in order to erase the written information, the negative bias of the semiconductor layer 2 may be removed. Specifically, the reverse leakage current of the p/n junction is increased by increasing the temperature of the semiconductor memory device or by irradiating it with light. These measures are
Effective in erasing all information stored in the device's memory cell array. In addition, a positive voltage is applied to the gate electrode 4 to collect negative charges in the floating semiconductor layer 2 in the channel region, and then the voltage applied to the gate electrode 4 is slowly lowered to zero. Then, charge pumping does not occur and the electric charge disappears. Furthermore, a high voltage is applied to the drain region 5 or the source region 4 to cause avalanche breakdown,
Information can also be erased by injecting electrons into the semiconductor layer 2. These means are effective for erasing information stored in specific memory cells making up a memory cell array.

Now, semiconductor storage devices with memory cells as described above can be manufactured at low cost using the same method as conventional MIS/FETs, and the memory cells can also be rewritten, but there is still room for improvement. There are many left behind.

For example, in the above device, a single crystal insulator such as sapphire is used as the substrate 1, but this is to make the semiconductor layer 2 in a floating state, so if the semiconductor layer 2 is p-type, The same effect can be obtained by replacing the substrate 1 with an n-type silicon semiconductor, and a device having such a structure is illustrated in FIG.

In FIG. 2, 1' indicates an n-type silicon semiconductor substrate, 7 and a silicon dioxide insulating layer, respectively.
Note that the same parts as those explained with reference to FIG. 1 are indicated by the same symbols.

As is clear from the above, in this type of device, electrons injected from the inversion layer into the semiconductor layer 2
The charge must be trapped in the semiconductor layer 2 before it flows into the n ⁺ type drain region 6, n ⁺ source region 5, etc. and become an accumulated charge, but the potential in the semiconductor layer 2 is shown in the distribution as shown in Figure 3. Because of the curve, electrons cannot be trapped efficiently, and a considerable amount of electrons flow into the drain region 6 or return to the source region 5.

The present invention improves the charge storage efficiency by only making slight modifications to the structure of the memory cell in a semiconductor memory device having a charge pumping type memory cell as described above. will be explained in detail.

FIG. 4 is a side sectional view of a main part of an embodiment of the present invention, and the same parts as those explained in connection with FIG. 2 are indicated by the same symbols.

This embodiment ^differs from the device in FIG. This is because it is surrounded by a ⁺ -type semiconductor layer 2'.

By adopting such a configuration, the potential becomes distributed as shown in FIG. 5, so that most of the injected electrons are trapped in the region 8 and become accumulated charges.

As can be seen from the above description, the semiconductor memory device of the present invention is a semiconductor memory device having a memory cell that utilizes the fact that the threshold voltage changes depending on the presence or absence of charge accumulation in an electrically floating semiconductor layer. a charge storage region formed in a portion of the semiconductor layer directly below the gate electrode and having the same electric type and low concentration as the semiconductor layer; By having a source region and a drain region which are formed in the semiconductor layer and have a conductivity type opposite to that of the semiconductor layer, carriers, such as electrons, injected into the charge storage region can be trapped and stored with high efficiency. It is something that can be done.

[Brief explanation of the drawing]

1 and 2 are side sectional views of the main parts of the conventional example, FIG. 3 is a diagram showing the potential distribution in the conventional example shown in FIG. 2, and FIG. 4 is a side sectional view of the main parts of an embodiment of the present invention. FIG. 5 is a diagram showing the potential distribution of the embodiment shown in FIG. In the figure, 1 and 1' are substrates, 2 and 2' are semiconductor layers, 3 is a gate insulating film, 4 is a gate electrode, 5 is a source region, 6 is a drain region, 7 is an insulating layer, and 8 is a charge storage It is an area.

Claims (1)

[Claims] 1. In a semiconductor memory device having a memory cell that utilizes the fact that the threshold voltage changes depending on the presence or absence of charge accumulation in an electrically floating semiconductor layer, a portion of the semiconductor layer directly below the gate electrode is used. a charge storage region formed to have the same conductivity type and low concentration as the semiconductor layer; a source region opposite to the charge storage region and formed apart from the charge storage region and having a conductivity type opposite to that of the semiconductor layer; A semiconductor memory device comprising a drain region.