JPS6139655B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for setting and displaying photographic information such as shutter speed and aperture value in a camera, etc., and particularly relates to a photographing information device in which information is set and changed electrically by operating a push button switch or the like. be. In a camera equipped with an exposure control circuit, conventionally, in order to set photographing information in the variable elements of the circuit, the variable elements are linked to these by manual operation of a mechanical information setting mechanism such as a shutter dial, aperture ring, etc. I was doing this by changing the position of the Therefore, the conventional method has drawbacks such as not only poor operability but also a large amount of space. A method to overcome the above drawback is to supply pulses to a digital signal forming means such as a counting circuit by disposing it at an appropriate location on the camera and operating a push button, etc., and causing the counting circuit to perform a counting operation. A possible method is to set the exposure information as a count value of a counting circuit. However, this method has the disadvantage that, unlike the conventional setting method using a dial, it is not possible to directly set an arbitrary seconds value or aperture value. That is, when a counting circuit is used as a digital signal forming means, the counting circuit is
If it is formed by a bit counter, the counter will contain "0, 0, 0, 0" to "1,
You can set 16 digital values up to ``1, 1, 1'', and update the contents of the counter one step at a time from ``0, 0, 0, 0'' by pressing the button as shown above. Although it is possible to set a digital value corresponding to the seconds or aperture value, when setting the information, the contents of the counter must always be updated one step at a time from the initial value of "0, 0, 0, 0". The disadvantage is that information cannot be set quickly. One possible solution to this problem is to set the contents of the counter to a specific value (a frequently used value) when the power switch is turned on. If you apply this method to make the initial settings, this specific value will always be set when the power is turned on, and the above "0, 0, 0, 0" will not be set as the initial value, but the desired setting value will be set. If the value is far from the specific value, the specific value must be updated to the desired value one step at a time, and in this case, quick setting is not possible. In addition, in a so-called dual-priority camera, it is necessary to set the shutter speed for shutter priority and the aperture value for aperture priority, and the above specific value is different for shutter priority and aperture priority, and the above specific value is 2. It becomes necessary to be able to set different types of values, and it becomes necessary to provide a plurality of specific value forming circuits. The present invention has been made in view of the above-mentioned matters, and includes an operation switch (example, shown in FIG. 1) that is operated when setting information for shutter priority and aperture priority.
Equivalent to SW ₂ . ), and a digital forming circuit (embodiment, FIG. 2), the digital value formed by the forming circuit when giving priority to shutter is used as a preset seconds value to calculate the aperture value together with the brightness information, and the digital value formed by the circuit when giving priority to aperture is calculated. An arithmetic circuit (embodiment, corresponding to 3 in FIG. 9) that calculates a shutter speed value along with brightness information as a preset aperture value, and a preset circuit that presets a specific digital value in the forming circuit in response to power-on. a circuit, and the specific digital value is a digital value indicating a value approximately halfway between the digital values representing the lower limit and the upper limit,
Further, the digital value representing the intermediate value is made to correspond to the shutter speed value and aperture value representing a value approximately intermediate between the lower and upper limits of the setting information that are frequently used among the shutter speed and aperture value, Even if the specific value is far from the desired setting value, the desired setting can be made quickly, and even in the case of both priority settings, the same specific value can be set. The present invention will be explained in detail below with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of an electronic photographic information setting and display method according to the present invention. The figure is a block diagram of a device for setting and displaying photographic information in a camera, and each input and output terminal in the figure indicates a transmission terminal for input and output signals from each part of the digitally controlled camera. In the figure, the Vc attached to each terminal indicates one pole of the camera's power supply, and the other poles are connected to the part indicated by the ground symbol. Ia is the input terminal of the circuit for switching the direction of increasing or decreasing the set value, and becomes logic “1” when switch Sw1 is on.
is sent to the transmission path 9, and "0" is sent out when it is off.
When the up/down counter 2 constituting the digital signal forming means receives the input from this 9, it is counted up in steps when it is "1", and in the down direction when it is "0". Terminal Ib is a terminal for controlling the clock pulse of the count, and switch Sw
2 is turned on, a "0" signal is sent to the transmission path 17, and when it is turned off, a "1" signal is sent to the transmission path 17. The clock pulses are generated by a clock pulse generator of 7, and set values and other values change stepwise at the cycle. The clock pulse generated at step 7 is passed through the clock input controller 1 to the CP of the up/down counter 2.
It is applied to the input and is counted in steps according to the up/down direction indication from line 9. Also
A clock input control signal from Ib is passed through a line 17 to a counter control device 4 and a display control device 5.
It is also transmitted to The terminal Ic constitutes the power supply circuit of the up/down counter 2, and the self-holding action of the timer 8 inserted into this allows the power supply to the counter 2 to be maintained for a certain period of time even if the power to the device is turned off. It's summery. Reference numeral 3 denotes a central control unit CPU that constitutes an exposure calculation circuit, into which brightness information from a photometer including a light receiving element, a priority command signal from a terminal Id, and an output signal 15 from a counter 2 are inputted, and the brightness information and the output signal 15 from a counter 2 are input. Exposure calculations are performed based on the set exposure information, and control signals to the shutter control and diaphragm control sections as well as various signals as shown are sent to the display control device 5 as outputs.
Switch Sw3 of the Id circuit is a priority mode changeover switch. When Sw3 is on, the camera operates in shutter priority mode, and when it is off, the camera operates in aperture priority mode.
Among the signals sent from the CPU 3 to the display control device 5, the shutter digit signal and the aperture digit signal passing through the lines 10 and 11 are transmitted through a gate controlled by a signal from the terminal Ie, and are displayed by turning Sw4 on and off. stops or flashes. Note that a warning signal (“1” signal) for displaying various warnings such as that the calculated output value has reached the control limit for camera exposure etc. is sent directly to the display control device 5 via the line 12, and the display segment signal is sent directly from the CPU to the display device 6. The output 15 of the up/down counter 2 is input to the CPU as well as to the counter control circuit 4, and the circuit 4 is also applied with the clock control signal 17 to the clock input control device 1 and outputs the counter to its output. It outputs a control signal which is sent to the parallel presetable input terminal of the up/down counter 2. The output 16 of 4 is also sent to the clock input control device 1 and the display control device 5 to turn on and off their control operations. The display control device 5 receives clock pulses from a clock pulse generator 7 and a signal 16 from the counter control device 4 as shown.
In addition, signals from the line 17 are inputted, and control actions for various displays are performed according to various commands 10, 11, and 14 from the CPU, and a shutter seconds signal 18 and an aperture signal 19 are outputted. . These display signals are input to the display device 6,
Various information displays are displayed in the finder, for example, according to display segment commands from the CPU.
The display device is composed of a combination of known segment and digit drivers, 7-segment LEDs, and other display elements. The configuration and operation of the electronic photographing information setting and display device according to the present invention have been explained above with reference to FIG. This will be explained in detail below. In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals. FIG. 2 is a circuit diagram showing an embodiment of the clock input control device 1 in FIG. 1, and FIG. 3 is a curve diagram showing an example of a timing chart of the device shown in FIG. In the figure, the pulses from the clock pulse generator 7 have a waveform as shown in FIG. 3A. Reference numeral 23 denotes a frequency divider composed of a circuit such as a flip-flop, and a signal having a waveform as shown in FIG. 3B is obtained at its output. All clocks are synchronized at the falling edge of the pulse, and the output of counter 21
Q ₄ is connected to AND gate 24 via inverter 27
21 outputs _Q4 and at the same time inhibits clock input. FIG. 3C shows the input of the clock input control device 1 and the switch Sw2.
When it is off, it is “1” and when it is on, it is “0”. This signal also serves as the reset input of counter 21 and
It becomes the CP input of the up/down counter 2 via the OR gate 25 and the AND gate 26. The _Q4 output of the counter 21 becomes the second input of the AND gate 22, which is ANDed with the divided output of the clock and input to the CP of the up/down counter 2 via OR25 and AND26 to control the count of the up/down counter 2. A control signal from the counter control device shown at 4 in FIG. 1 is input as the second input of the AND 26, and the clock to the counter 2 is turned on and off. In Fig. 3, ho shows a case where the clock input control switch Sw2 is on for a long time. In this case, when the _Q4 output of the counter 21 becomes "1" (Fig. Down counter 2 starts counting. This shortens the time between each step after the second step when continuing to operate the set value, and the operation switch
If Sw ₂ is kept in the operating state (on), the contents of the counter as a digital signal forming means will be updated sequentially, and the digital value as the output will be updated sequentially. Figure 4 shows the counter control device 4 in Figure 1.
FIG. 2 is a circuit configuration diagram showing one embodiment of the present invention. In the figure, the outputs C ₁ to _{C 5} of the up/down counters 2 are input to the CPU 3 via a line 15 and are also sent to the OR gates 28 and 29 of the counter control device. The outputs of OR gates 28 and 29 are output from OR gate 3 along with the up/down direction switching signal from line 9.
0 and 31, and the outputs of OR gates 30 and 31 are ANDed by AND gate 33 and output to line 16 as a counter control output via OR gate 34. Note that a clock input control signal (C or H in FIG. 3) is input from the line 17 to the OR 34. Assuming that the output of the up/down counter 2 has now reached "00000", that is, the upper limit of the setting range, and the direction command from the track 9 is "0" indicating down, the output of the OR 28 is "0",
The output of OR29 becomes "1". At this time, the signals input to OR30 and 31 are “0” in 30,
“0” and 31 become “1” and “1”, and the output of OR30 becomes “0”, and the output of OR31 becomes “1”, so the output of AND33 becomes “0”, and the line 1
When the signal from 7 becomes "0", the counter control output 16 becomes "0", which is sent to the clock input control device 1, and the input of the clock to the up/down counter 2 is stopped. Also, when the output of the counter 2 reaches "1, 0, 0, 0, 1", that is, the lower limit of the setting range, and the command from the line 9 is "1" indicating up, then the OR gate 2
The output of 8 is "1", the output of 29 is "0",
Counter control output 16 in the same way as in the above case
becomes "0" and the clock is stopped. In all other cases, the counter control output is "1" and the clock changes stepwise in response to an UP or DOWN command from the line 9.

[Table] Table 1 shows the output of up-down counter 2 and
This shows the correspondence between shutter priority and aperture priority control outputs in the CPU, and uses 18 of the 5-bit counter output combinations _C5 to _C1 to determine the shutter speed or aperture step required for actual shooting. You're getting a change. FIG. 5 is a circuit diagram showing an embodiment of the display control device 5 in FIG. 1. As shown, the device is
Consisting of AND, OR, NAND gates and inverters, the clock pulse generator 7 generates clock pulses, the line 16 generates a counter control output, the line 17 generates a clock input control signal, and the line 1
0, 11, 12, and 14 input command signals from the CPU for shutter digit, aperture digit, warning, and priority setting, respectively, to device 5, and the output from 5 is transmitted to the display device via lines 18 and 19. The shutter speed, aperture value, etc. are displayed. To explain an example of the operation of the device shown in the figure,
When the counter output input to the CPU 3 is within the appropriate exposure setting range, the input from the CPU 16 becomes "1", and the warning input 12 from the CPU becomes "0". Now considering the case where the priority setting is set to shutter priority mode, the line 14 becomes "1", the outputs of AND gates 30 and 31 become "0" due to these inputs, and the output of AND gate 34 becomes "0". Because track 16 is “1”
The output of the NAND gate 33 becomes "1". Also
The output of the NAND gate 32 also becomes “1”, and the AND
Since the inputs of gate 36 are all "1" except shutter digit signal 10, the input to output 18 of AND35 is
A shutter digit signal 10 from the CPU is output and sent to the display device 6 to display the shutter seconds. Similarly, in the case of aperture priority mode, the inputs of the AND gate 46 are all "1" except for the aperture digit signal 11, and the output 19 of the AND gate 45 is sent to the CPU's aperture digit signal 11.
is output. Next, the setting value of up/down counter 2 is
When the limit value of the setting range is reached, 16 becomes "0", and the output of the OR circuit 50 changes to "0" and "1" in accordance with the output of the clock generator 7, that is, the clock cycle, so the display is controlled accordingly. Device output 18,1
Since the signal 9 also periodically repeats "0" and "1", the display on the display device 6 repeatedly blinks. As described above, each input line in the display control device of FIG.
When the combination of the signals 4 changes in various ways, the shutter digit signal 10 or the aperture digit signal from the CPU is controlled in various ways by the display control device 5 and is generated at the output 18 or 19. The display on the display device 6 changes in various ways depending on these outputs.

【table】

[Table] × is arbitrary Table 2 shows changes in display corresponding to various logic inputs to the display control device as described above. In the figure, the numbers in the columns of outputs 18 and 19 indicate the shutter digit as 10 and the aperture digit as 11.
A number surrounded by a circle indicates continuous lighting, and a number surrounded by a cross indicates blinking. Note that "0" indicates off. Next, a few examples of the various operations of the display control device shown in FIG. 5 shown in Table 2 will be explained. Logic "0011" shown in the second and third rows of Table 2
"0010" indicates the control of information display during setting of priority setting information, and "0011" indicates a case where both the setting value and the calculation result during setting of priority setting information are within the control range. In this case, each input signal in FIG. 5 is such that 17 is "0", 12 is
is "0", 16 is "1", and 14 is "1".
The output of NAND 33 is "1", and if the clock 7 is outputting "1", NAND 32 outputs "1". Also, since the output of OR50 is “1”, AND
All other inputs of 36 except the shutter digit signal are "1", and signal 10 passes through 36. Since the AND35 also has inputs "1" and "1", the signal 10 is sent to the output 18 of the device. Next, NAND43 outputs "0" and NAND42 outputs "1". This allows AND46 to pass the aperture digit signal.
Since AND 45 is turned off, signal 11 does not appear on output 19. Therefore, the display in this case is 1
Only the shutter digit signal 10 (setting value) from 8 is displayed, and the aperture digit signal 11, which is the calculation result, is not displayed. Next, the setting of the priority setting information is stopped, and if both the set value and the calculated value at this time are within the control range, the logic becomes "101x" as shown in the first row of Table 2. × can be arbitrarily set, so if the information is set to give priority to the shutter, the logic will be “1011”. In this case, both NAND33 and NAND43 will output “1”, and the input from clock 7 will be “1011”. Both NAND32 and NAND42 output "1" even if they are "1" or "0". Therefore AND36, 35 and AND4
6 and 45 are all on, and both the shutter digit signal 10 (setting value) and aperture digit signal 11 (calculated value) from the CPU are sent to the display device through outputs 18 and 19, and these two pieces of information are Is displayed. Next, logic "0001" and "0000" in the 4th and 5th rows of Table 2 are cases where the set value exceeds the control range while setting the priority information, and in this case, the logic "0001" and "0000" in the 4th and 5th rows The 16 inputs of the logic become "0". Shutter digit signal 10 and aperture digit signal 11 are both generated at outputs 18 and 19, and AND 36 and 46 repeat on and off states when the input from clock 7 is "1" and when it is "0". Therefore, the display by 18 and 19 becomes a blinking display. That is, in this case, both the set value (limit value) and the calculated value are displayed blinking. Next, logic "0111" and "0110" in the 7th and 9th rows of Table 2 are cases where the calculated value from the calculation result exceeds the limit value of the control range while setting the priority information. Warning signal 12 from the CPU becomes "1". "0111" if priority is given to the shutter now
When the value is taken, both NANDs 33 and 43 output "1". Also, NAND32 always outputs “1”.
NAND 42 outputs "0" when the output of clock 7 is "1" and "1" when the output is "0". Therefore, the set value (shutter digit signal) that passes through AND36 and 35 always appears at output 18, but AND4
The calculated value (aperture digit signal) passing through 6 and 45 flashes at the cycle of clock 7. As described above, by providing the respective logics shown in Table 2 to the display control device of FIG. 5, the display of the display device can be varied in various ways as shown. Figures 6a and 6b illustrate the configuration of a logic circuit for a specific operation among the various operations in the display control device in Figure 5. With such a configuration, Figure a shows a set value as a display control output. When the set value reaches the set limit value, the predetermined limit value and the calculated value are displayed by continuous lighting, unlike the embodiment in Fig. 2. Figure b shows the case when the set value reaches the set limit value. This is a case where at least an example of the set value is displayed by blinking seven segments. In FIG. 6a, the signal on line 16 that warns that the set value has reached the limit value becomes a "0" signal, so
The outputs of both NANDs 33 and 43 become "1", and the shutter digit input 10 and aperture digit input 11 from the CPU are both sent to the display device 6 as outputs 18 and 19. That is, since one of the inputs 10 and 11 is a set value and the other is a calculated value, this circuit configuration outputs both the set limit value and the calculated value. FIG. 6b shows that when the set value reaches its limit value, 16 becomes "0" and 17 becomes "1" via the inverter 52, and the on/off signal from the clock signal generator 7 is sent to the line of 16.
Since it is input through an OR gate, if 14 is "1", that is, shutter priority, then at a cycle of 7
The output of AND35' is on, the set value from off line 10 is displayed blinking, and the calculated value from the other 11 is
It is turned off by AND gate 45'. Next, FIG. 7 is a circuit configuration diagram showing another embodiment of the counter control device in FIG. 1, and the output 20 from 4 in FIG. It is designed to send signals. In the figure, assuming that counter 2 has now reached the set limit value of "1, 0, 0, 0, 1", if line 9 is up count command "1", in the next state it will be "1, 0, 0, 0, 1". , 0, 0, 1, 0'', the output of the NAND gate 62 is “0”, and the output of the OR 64 is also “0”. In addition, since the clock input control signal from line 17 is "0", the output of NOR 66 becomes "1", which is sent to the reset terminal of counter 2, and all counters are reset. Contrary to the above, the counter is now “0, 0,
Assuming that the set limit value is "0, 0, 0", a down command "0" is input from 9, and in this state, the counter counts down by 1 pulse, and the output of NOR65 becomes "1", which is the counter The counter 2 receives the values "1, 0, 0, 0, ₁ " of the preset inputs _P1 to P5. FIG. 8 is a block circuit diagram showing another embodiment of the photographing information setting display method according to the present invention, in which the same parts as in FIG. 1 are indicated by the same symbols, and switches of each input circuit are omitted. . The difference between the embodiment shown in FIG. 1 and that in FIG. This is what is being communicated. According to the circuit arrangement as shown in the figure, the warning 12 indicating that the calculated value is out of the control range can be considered to be completely equivalent to the signal 16 when the set value reaches the limit value range. In other words, when the calculated value is out of the control range, the warning output 12 of the CPU 3 is "1", which inputs "0" to the AND gate 72 via the inverter 71, and the output of the AND 72 becomes "0". The information is input to the display control device 5 to display a warning. The operations of the other circuits have been explained in detail with reference to FIG. 1 and the detailed drawings in and after FIG. 2, so they will not be repeated here. Note that the display control device in FIG.
If the circuit shown in FIG. 6A is used, the priority setting value and the calculated value can be displayed simultaneously, and the circuit shown in FIG. In this case, the clock input control signal 17 must always be kept at “1”.
Since the outputs of NAND circuits 30' and 40' are "1", 16' becomes "0", and the signals 10 and 11 become 1 due to the period of clock signal 7.
8 and 19, respectively, are output as blinking signals. Next, FIG. 9 is a block circuit diagram showing an embodiment of a preset device according to the present invention applied to the information setting system shown in FIG. In this circuit, the preset inputs _P5 to _P1 of up/down counter 2
is set to the state of "0, 0, 1, 0, 0". That is, when the power of the device is turned on in the state of this circuit, the signal from the monostable multivibrator which is linked to the power switch and constitutes the signal forming means is transmitted to the parallel preset input enable terminal of counter 2, and the above logic value "0, The counter will be automatically preset to 0,1,0,0''. In other words, in the case of shutter priority, this preset value "0, 0, 1, 0, 0" is 1/125 seconds, and in the case of aperture priority, it is F11, so according to the circuit in Figure 9, when the device is powered on, , the frequently used shutter speed or aperture value can be preset in the counter 2. In the example, F11 is preset with the aperture value of 1/125 seconds as the shutter time, but
As the preset value, an intermediate value of frequently used exposure information is adopted, for example, a shutter time of about 1/250 to 1/60 second, an aperture value of about F11 to F2.8, and the like. Furthermore, the monostable multivibrator constitutes a power-on signal forming means, and a preset information circuit is constituted by the connection configuration of the preset inputs _P1 to _P5 of the counter, the inverter, and the ground, and these power-on signal forming means and information A preset circuit is constructed from the circuits. FIG. 10 is a perspective view showing the appearance of an embodiment of a camera using the photographing information setting display method according to the present invention.
Sw1 to Sw4 are arranged on the top and front surface of the camera body, and it is desirable to arrange them optimally for the photographing operation. FIGS. 11 and 12 are perspective views showing one embodiment of the configuration of the operation button (or lever) provided on the camera body and each switch inside the camera body in the method of the present invention. In the figure, reference numeral 101 denotes an operation button for setting information, which is rotatably supported by a switch board 102 by a mechanism not shown. Sw1 and Sw2 are up and down shown in Figure 1.
This is a down direction command switch and a clock input control switch, and by pressing the right or left protrusion of the button 101, setting information is stepped up or down. 103 is a push button for operating the display control switch Sw4. In the arrangement shown in Figure 12, this display control switch
Sw4 can be activated either by operating the button 103 or by operating the setting button 101. The first stroke of the button 101 turns on the display switch Sw4, and
The configuration is such that Sw1 and Sw2 are turned on at the second stroke of 01. In addition, the power of the camera in the embodiment is turned on by a power switch (not shown), or the power switch is the switch shown in FIGS. 11 and 12.
Of course, a switch linked to SW ₂ may be provided, or a switch linked to the first stroke of the release button may be provided. or,
Although a counter is shown as the digital signal forming means, a register may be provided instead of the counter. As described above, in the present invention, a digital signal is formed by the digital signal forming means by operating the operating member, and while the operating member is operated, the digital value is sequentially updated, and a conventional dial or the like is used. Exposure information is set as a digital value without any need to set the camera, and when the camera is turned on, the initial settings are automatically preset to frequently used values such as intermediate exposure values, making it possible to quickly set information. It is something that can be done.

[Brief explanation of the drawing]

1 is a block circuit diagram showing an embodiment of a camera system to which the photographing information setting device according to the present invention is applied; FIG. 2 is a circuit configuration diagram showing an embodiment of the clock input control device in FIG. 1; 3 is a curve diagram showing an example of the timing chart of the circuit in FIG. 2, FIG. 4 is a circuit configuration diagram showing an example of the counter control device in FIG. 1, and FIG. 5 is a diagram showing the display control device in FIG. 1. 6 is a circuit configuration diagram showing one embodiment of the display control device shown in FIG. 5, and FIG. 7 is a circuit configuration diagram showing another embodiment of the counter control device. , FIG. 8 is a block circuit diagram showing another embodiment of the camera system to which the present invention is applied, FIG. 9 is a circuit diagram showing an embodiment of the information setting device according to the present invention, and FIG.
1 is a perspective view showing the external appearance of a camera to which the present invention is applied, and FIGS. 11 and 12 are perspective views showing an example of the configuration of operation buttons and changeover switches provided on the outer surface of the camera. 1... Clock input control device, 2... Up/down
Down counter, 3...Central control unit (CPU), 4...Counter control device, 5...Display control device, 6...Display device, 7...Clock signal generator, 8...Self-holding timer.

Claims (1)

[Claims] 1 A digital value is set between the operating switch operated when setting information for shutter priority and aperture priority, and the digital value representing the lower limit value and the digital value representing the upper limit value of the setting information in response to the operation signal of the switch. a digital forming circuit that performs forming and updating operations, and a digital value formed by the forming circuit when giving priority to the shutter, and calculates the aperture value by calculating the digital value formed by the forming circuit as a preset second value, together with brightness information, and when giving priority to the aperture, and a preset circuit that presets a specific digital value in the forming circuit in response to turning on the power. And, the specific digital value is set to be a digital value approximately halfway between the digital values representing the lower limit and upper limit, and the digital value representing the intermediate value is set approximately to the lower limit and upper limit of the setting information. An information setting device for a dual-priority arithmetic circuit, characterized in that it corresponds to frequently used shutter seconds and aperture values that indicate intermediate values.