JPS6145383B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a wiring structure, and more particularly, to a method for manufacturing a wiring structure that can easily and accurately form a wiring structure with a small required area. Regarding the manufacturing method.

[Background of the Invention] A conventional method for manufacturing multilayer wiring and the resulting structure will be explained with reference to FIG.

FIG. 1a shows Al or Al on the semiconductor substrate 11.
A lower wiring 12 made of an alloy of Si, Cu, etc. is formed, and an interlayer insulating layer 1 made of SiO ₂ etc. is formed.
3, and then insert the connection opening 14 in the predetermined position.
A and 14B are formed, and the connecting portion 1 of the lower wiring is formed.
9A and 19B are shown exposed. The widths of these connecting portions 19A and 19B are W _A ,
Let it be W _B. In this way, in the conventional method, the widths W _A and W _B of the connection portion are determined by the connection opening 14 formed in the interlayer insulator.
It is equal to the width of A and 14B. As shown in FIG. 1B, an upper wiring conductor 15 is deposited thereon, and a photoresist pattern 16 is formed at a predetermined position to form an upper wiring. This photoresist pattern 1
Let the widths of 6 be _WC and _WD , respectively. As the upper wiring conductor 15, Al or an alloy of Al and Si or Cu is used. Next, photoresist pattern 1
By etching the upper wiring conductor 15 using etching solution 6 as a mask, and then removing the photoresist pattern, a multilayer wiring structure having upper wirings with widths W _C and W _D as shown in FIG. 1c is obtained. is formed. If three or more layers of wiring are to be formed, the above method may be repeated.

In such conventional multilayer wiring, one connection opening is required for each of the connection portions 19A and 19B of the upper and lower wiring, as shown as connection openings 14A and 14B. Furthermore, the widths W _C and _WD of the upper wiring were always larger than the widths W _A and W _B of the connection portions 19A and 19B. This means that when W _C and W _D are smaller than W _A and W _B , the upper wiring conductor 15 above the connection opening 14 is coated with a photoresist pattern 1, as shown in FIG. 1d.
There will be a part not covered by 6,
After etching, the photoresist pattern 16
This is because the etching solution may permeate through the portions not covered by the etching solution, etching the lower wiring 12 as well, resulting in a decrease in reliability as in the section 18A or a disconnection as in the section 18B.

Therefore, as shown in the cross-sectional view shown in FIG. 1c and the top view shown in FIG. 1e, the distance L between the centers of the adjacent connecting parts 19A and 19B is (where S is the wiring interval of the upper wiring). The distance L between the centers is restricted by the widths W _C and W _D of the upper wiring and the minimum value of the wiring spacing S. For example, if W _A = W _B = 10 μm, W _C
=W _D =14μm is required, and the wiring spacing S is 6μm.
m, the distance L between the centers cannot be narrowed to 20 μm or less. To reduce L, W
Although it is necessary to reduce _C and W _D , the connection opening 1
It is difficult to reduce the widths W _A and W _B of 4A and 14B to 7 μm or less and form them stably.

Therefore, as stated above, the distance L between the centers is
It is difficult to reduce the thickness to 20 μm or less.

[Purpose of the invention]

The present invention provides the above-described adjacent connecting portion 19
The object of this invention is to easily and accurately form a wiring structure in which the distance L between the centers of A and 19B can be made much narrower than in the past.

[Summary of the invention]

In order to achieve the above object, an insulating film having an opening is formed on the conductive film which will become the lower layer wiring so that portions of the conductive film separated from each other are exposed through the opening. In this method, an intermediate conductor layer and a wiring conductor layer having different resistances to etching solutions are laminated and then selectively etched as desired.

The structure of the multilayer wiring formed according to the present invention is as follows:
FIG. 2a shows its top view, and FIG. 2b shows its sectional view.
If necessary, connect two or more connecting parts, e.g. 29
A, 29B, and 29C are included in one connection opening 24A. In the method of the present invention, there is no need to make the connection opening 24A small, and the distance L between the centers of the adjacent connection parts 29A and 29B is determined only by the accuracy of the upper wiring. In other words, if the minimum pattern size that can be formed for the upper wiring is 4 μm, then W _A , W _B , and S are all 4 μm.
In this case, the distance L between the centers of adjacent connecting portions 29A and 29B can be narrowed to 8 μm. Note that the connection opening 24D has the connection portion 29D placed therein.
The figure shows a conventional structure that includes only 1. In addition, 21
22 represents a first wiring, and 25 represents a second wiring.

[Embodiments of the invention]

Example 1 If the etching liquid for the upper wiring conductor does not soak the lower wiring conductor, or if there is a conductor layer between the upper and lower wiring conductors that is not immersed in the etching liquid for the upper wiring conductor, the photo-etching method is used. The structure of the present invention can also be realized by the following. Figure 3a
1 shows a state in which a connection opening 44 is formed in an insulating layer 43 covering a lower wiring 42 on a semiconductor substrate 41. FIG. There are two connection parts 49 inside the connection opening 44.
A and 49B are included. As the lower wiring 42
Al or an alloy of Al and Si, Cu, Cr, Mn, etc. is used. The insulating layer 43 is made of SiO ₂ or Phosphor-
Silicate Glass, Boro-Silicate Glass, or
PIQ resin, polyimide resin, etc. Use polymer materials, etc. As shown in FIG. 3b, an upper wiring conductor 45 and an intermediate conductor layer 48 are formed on the semiconductor substrate 41. The upper wiring conductor 45 is made of Al or Al.
The intermediate conductor layer 48 may be made of an alloy of Si, Cu, Cr, Mn, etc., but the intermediate conductor layer 48 needs to be made of Cr, Ti, polysilicon, or the like. A photoresist pattern 46 for photoetching is formed thereon. Next, as shown in Figure 3c, the upper wiring conductor 4
9 to form an upper wiring pattern,
The intermediate conductor layer 48 is exposed. A mixed solution of phosphoric acid, nitric acid, and glacial acetic acid is used as the etching solution for the conductor 45, but Cr and Ti are not etched. Next, as shown in FIG. 3d, the conductor 48 is etched using the conductor 45 with the upper wiring pattern formed thereon as a mask, and then the photoresist pattern 46 is removed to form the wiring structure of the present invention. A ceric ammonium nitrate aqueous solution may be used for etching Cr, and a dilute hydrofluoric acid aqueous solution or Freon gas plasma may be used for etching Ti. For etching polysilicon, a mixture of hydrofluoric acid and nitric acid or Freon gas plasma may be used.

〔Effect of the invention〕

It is clear from the above description that the present invention is effective in improving the degree of integration of upper wiring. Furthermore, in the above embodiment, Cr or Cr is used as the upper wiring conductor.
By also using Ti and Poly-Si, the insulating layer 43
It also improves the adhesive strength with the semiconductor device, and improves the reliability of the semiconductor device.

Further, the present invention can also be applied to the case where a ceramic substrate or the like is used as the substrate and a wiring structure is also produced.

[Brief explanation of the drawing]

1A to 1D are process diagrams showing a conventional method for manufacturing a wiring structure, FIG. 1E is a front view of a wiring structure formed by the conventional manufacturing method, and FIG. FIG. 3 is a diagram illustrating an embodiment of the present invention, showing a top surface and a cross section of a multilayer wiring structure formed in this manner.

Claims (1)

[Claims] 1. A step of forming a conductive film having a desired shape on a semiconductor substrate, and forming an insulating film having an opening so that at least a portion of the mutually spaced portions of the conductive film and a portion of the surface of the semiconductor substrate are formed as described above. a step of forming an intermediate conductor layer on the conductor film so as to be exposed through the opening; a step of laminating an intermediate conductor layer and a wiring conductor layer having different resistance to an etching solution from the intermediate conductor layer and forming the same over the entire surface; , selectively forming a photoresist film at a position above the portion of the conductor film exposed through the opening, and using the photoresist film as a mask to form the exposed portion of the wiring conductor layer and A method of manufacturing a semiconductor device, comprising the step of sequentially removing the intermediate conductor layer below the exposed portion.