JPS6146919B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides semiconductor lead-on memory (hereinafter referred to as
In particular, the present invention relates to a so-called vertical ROM in which a plurality of insulated gate field effect transistors (hereinafter referred to as MISFETs or simply FETs) are connected in series to one output line.

In recent ROMs, ROMs with the above-mentioned vertical configuration are used for the purpose of improving the degree of integration.
However, such a vertical ROM has the disadvantage of slow operation speed. The reason for this is that when a plurality of FETs are connected in multiple stages to one output line, the impedance becomes large and pre-charge and de-charge become slow.

For this reason, the applicant of the present application previously proposed a circuit as shown in FIG. 1A (Japanese Patent Application No. 156493/1983). That is, as shown in Fig. 1A, the output lines are divided into eight lines, which are connected in parallel every four lines (l ₁ to l ₄ ) and (l ₁ ′ to _{l 4} ′), and these parallel-connected lines are The devices are arranged above and below, and until now they have been connected to one output line.
A method is adopted in which the FET is divided into eight equal parts and connected to the eight output lines (this is called vertical division). In addition, the output line L ₁ connected in parallel above
Make both outputs two inputs on the output side of ~l ₄ and l ₁ ′ ~ l ₄ ′
A NOR gate circuit _G0 is provided and the output is taken from this output point. Further, each line is connected to a power supply V _DD (or V _GG ) via a FET driven by a precharge clock pulse φ _B . A column select line is provided on the power supply side of each line, and a ROM address line is provided on the ground side. These lines and the output line are connected by appropriate FETs (marked with ○ in the figure). For example, as shown in Figure 1B, the ○ mark in A is connected to the output line _l1 in series. The electrical connection is made by a connected FETM ₀ and a line l ₆ connected to the gate of this FET. In the ROM having the above configuration, first, the output lines _l1 to _l4 and _l1 ' to _l4 ' are precharged by setting the clock pulse _φB to a high level;
Next is the discharge FET installed on the ground side.
(not shown), selects an appropriate row by a signal applied to the address line, and selects an appropriate column by a signal on the select line, and then the gate circuit
The desired ROM output can be obtained from G ₀ . If such a configuration is used, FETs can be connected to a single output line, compared to a conventional configuration in which an extremely large number of FETs had to be connected to a single output line.
Since the number of FETs can be reduced to 1/8, impedance is reduced and speed can be improved. However, since the same number of select lines and address lines are required in both the upper and lower directions, the overall capacity becomes large, and this has the drawback of hindering an increase in speed.

In order to eliminate the above-mentioned drawbacks, the applicant of the present application considered a circuit as shown in FIG. 2 prior to the present invention. In other words, the output lines are divided into 8 lines, and every 4 lines are connected in parallel (l ₁ to _{l 4} ), (l ₁ ′, to l ₄ ′), and these are further arranged in the horizontal direction (referred to as horizontal division). , select lines _l5 to _l10 and ROM address lines are arranged in common. Then, a NAND gate circuit is provided that receives two input signals from each output line connected in parallel, and a ROM output is obtained from the NAND gate circuit. The operation of the ROM with such a configuration is the same as in the case of vertical division. By adopting such a configuration, the wiring capacitance can be reduced, so that the speed can be increased even more than the above-mentioned vertically divided configuration.

By the way, in order to improve the operating speed of ROM, in addition to reducing the impedance and capacitance as mentioned above, it is also possible to increase the speed by limiting the precharge level and shortening the charging/discharging time. One possible method is to do so.

FIG. 3 is a circuit diagram of a pre-charge limiting circuit previously proposed by the applicants of the present invention focusing on the above points (Japanese Patent Application No. 65777/1982). As shown in the figure, 4
In a device in which two output lines are connected in parallel and their common connection point is connected to a power supply via a precharge FETM ₁ driven by a precharge clock pulse φ _B , the connection point between the common connection point and the precharge FET is Switching FETM ₂ is installed in
This switching FETM ₂ is connected to an inverter driven by the precharge level of the output line.
Controlled by G ₂ . The operation of the circuit having such a configuration is as follows. Before precharging starts, precharging FETM ₁ is off, the output line is at ground level, and the inverter output is at power supply level, so switching FETM ₂ is on. Next, when the clock pulse φ _B reaches the power supply level, precharging starts and the level of the output line rises. Then, when the precharge level of the output line becomes equal to or higher than the inversion level of inverter _G2 , the inverter is inverted and FETM ₂ is turned off. As a result, the precharge operation is stopped. Therefore, the output line is not charged above the threshold voltage of the inverter. As a result, discharge becomes faster and higher speeds can be achieved.

An object of the present invention is to provide a vertical ROM that can achieve high speed with a relatively simple configuration.

The gist of the present invention is to provide a plurality of series circuits each consisting of a plurality of MISFETs connected in parallel to each other between an output line and a reference potential line, each connected in series, and a power supply line for connecting a power supply. , comprising a precharge means and a precharge limiting means coupled in series between the power supply line and the output line, the precharge means limiting a precharge period during which the output line is precharged from the power supply line. , the precharge limiting means limits the precharge voltage between the output line and the reference potential line to be lower in absolute value than the power supply voltage supplied between the power supply line and the reference potential line. It is a semiconductor lead-on memory,
The precharge limiting means is comprised of a depletion type MISFET;
The semiconductor lead-on memory is characterized in that a predetermined voltage lower in absolute value than the precharge voltage is supplied between the gate of the MISFET and the reference potential line.

The present invention will be specifically described below with reference to the drawings along with examples.

FIG. 4 shows a circuit diagram of a vertical ROM to which the present invention is applied.

In the figure, MR is a group of memory matrices, which are configured by four output lines connected in parallel to each other, although not particularly limited thereto. This memory matrix has a structure similar to that shown in FIG. 1A or FIG. 3 above. That is, although not shown in the figure, a column select line is provided on the power supply line of each output line, and a ROM address line is provided on the ground side. Appropriate FETs are provided at the intersections of these column select lines, ROM address lines, and each output line, as shown in FIG. 1B.

In the same figure, IN ₃ is 4 connected in parallel with each other.
This is an inverter circuit connected to the common connection point of the main output lines. Further, Q _P is a pre-charge FET whose operation is controlled by a pre-charge pulse φ _B , and is constituted by an enhancement type FET. Q _D is a depletion type FET constituting a precharge limiting means, and its gate is connected to a ground potential line. As is clear from the figure, the precharge FET Q _P and the depletion type FET Q _D are connected in series between the power supply wiring V _DD and the common connection point.

As described above, according to this embodiment, a depletion type FET Q _D whose gate is grounded is connected in series to a precharge FET Q _P to which a clock pulse φ _B is applied. Therefore, each output line has V _th
It is precharged only up to _D (threshold voltage of FETQ _D ).

As a result, it is possible to limit the precharge voltage to a relatively low value with a relatively simple precharge limiting circuit while reducing impedance, and it is possible to improve the operating speed of the vertical ROM.

According to the present invention, it is possible to configure a precharge limiting circuit with a relatively small number of elements, and it is possible to prevent a semiconductor lead-on memory from becoming significantly large.

The present invention uses vertical ratioless ROM.
Widely available for MOSIC.

[Brief explanation of the drawing]

Figure 1A is a circuit diagram showing a vertically divided ROM configuration method, Figure 1B is a partially enlarged view thereof, Figure 2 is a circuit diagram showing a horizontally divided ROM configuration method, and Figure 3 is an example of a precharge limiting circuit. Circuit Diagram FIG. 4 is a circuit diagram showing an embodiment of a vertical ROM to which the present invention is applied. _M0 , _M1 , _M2 , _QP , _QD ...FET, _{G0, G1 ...} gate circuit, _IN3 ...inverter, MR...memory matrix group.

Claims (1)

[Claims] 1 A plurality of series circuits each consisting of a plurality of MISFETs connected in parallel to each other between an output line and a reference potential line, each connected in series, a power supply line for connecting a power supply, and the power supply line and comprising a precharge means and a precharge limiting means coupled in series between the output line, and the precharge means controls a precharge period for precharging the output line from the power supply line;
The precharge limiting means limits the precharge voltage between the output line and the reference potential line to be lower in absolute value than the power supply voltage supplied between the power supply line and the reference potential line. 1. A semiconductor lead-on memory, wherein the precharge limiting means comprises a depletion type MISFET whose gate is coupled to the reference potential line.