JPS6147020B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is applicable to digital speech (Digital Speech).
The present invention relates to a processor for an Interpolation (DSI) device. In a typical telephone conversation, one person is only listening while the other person is speaking, and both parties are often silent. Therefore, on a time-average basis, the transmission path is only used for about 1/2 or less of the time. Taking advantage of this fact, DSI equipment increases the efficiency of transmission path usage by transmitting only the portion where voice is present, approximately doubling the capacity of existing PCM lines. The theory of DSI equipment is explained in the publication “Digital Speech Interpolation” COMSAT
TECHNICAL REVIEW, Vol.6, No.1,
The configuration of such a DSI device is shown in Figure 1. Reference number 1 is the transmitting side DSI device, reference number 2 is the receiving side DSI device.
Showing DSI equipment. The transmitting DSI device 1 includes a voice detector 110, a transmitting voice memory 120, a transmitting assignment register 130, and an assignment processor 140, and is configured to transmit a PCM channel 2.
Compress to DSI channel 3 and PCM channel 2
New connection information with the DSI channel 3 is transmitted to the receiving DSI device via the allocation information signal line 4.
The receiving DSI device 2 includes an assignment information receiver 150, a receiving assignment register 160, and a receiving audio memory 170, and transmits PCM data from the DSI channel 3 and the assignment information signal line 4 to the PCM channel 5.
Replay the state of channel 2. In transmitting side DSI device 1, input PCM channel 2
Of the signals, only the channel with audio is written to the transmitting side audio memory 120 under the control of the transmitting side assignment register 130 and read out as the signal of DSI channel 3. The transmission side assignment register 130 indicates the correspondence between PCM channel numbers and DSI channel numbers. For convenience of explanation, suppose that the transmission side assignment register 130 has a correspondence relationship as shown in FIG.
The relationship between is shown in FIG. That is, assume that DSI channel number 2 is assigned to PCM channel number 1, DSI channel number 1 is assigned to PCM channel number 3, and DSI channel number 3 is assigned to PCM channel number 4. At this time, for example,
When PCM channel number 7 has audio (hereinafter referred to as active), the audio detector 110
detects that PCM channel number 7 is active. Assignment processor 140
searches for the DSI channel number that is not active (in the case of Figure 2, it is DSI channel number 4),
A new connection is determined, sent as assignment information, and the sending assignment register 130 is rewritten.
The allocation information consists of a part indicating connection or disconnection, a PCM channel number part, and a DSI channel number part. In the receiving DSI device 2, the contents of the receiving assignment register 160 are updated according to the assignment information received by the assignment information receiver 150 and track the contents of the transmitting assignment register 130. As a result, the received DSI signal obtains an output PCM signal by performing the reverse operation of the operation performed on the transmitting side. A PCM channel connected to a DSI channel remains connected even if it is no longer active unless assignment processor 140 assigns the DSI channel to another PCM channel. Since the number of DSI channels is fixed, sometimes more PCM channels than the number of DSI channels become active, making it impossible to transmit the first part of the audio. This situation can be greatly improved by temporarily reducing the accuracy of the PCM word (one sample value of PCM) from 8 bits to 7 or 6 bits and virtually increasing the number of DSI channels. For example, if the number of PCM channels is 8 as shown in Figure 3a and the number of DSI channels is 4 as shown in Figure 3b, the PCM transmitted on the DSI channel
If all words are 6 bits, there will be a total of 8 bits left over, so one new DSI channel can be added. DSI equipment is usually equipment that targets PCM60 channels or more. for example,
In a system that compresses 96 channels consisting of 4 PCM24 lines into 48 DSI channels, 6 new channels can be generated by changing the PCM word to 7-bit transmission, and 6 new channels can be added by changing to 6-bit transmission. can. These newly added channels are respectively called overload 1 channel (hereinafter abbreviated as OL1CH) and overload 2 channel (hereinafter abbreviated as OL2CH). In contrast, the original DSI channel will be referred to as a normal channel (hereinafter abbreviated as NCH). If an overload channel is used, assignment processor 140 may
If there is a channel with no audio (hereinafter referred to as inactive) and there is no new connection request,
In order to improve the accuracy of the PCM word, it is necessary to reallocate the PCM channel connected to the overload channel to the inactive NCH. Even after taking these measures, the channel cannot be assigned to a DSI channel even though it is active.
A PCM channel may also be present. The ratio of unallocated PCM channels to active PCM channels in a unit time is called the lockout rate, and if the DSI device shows an abnormally high lockout rate, the assignment processor can also inform the outside world of this. 140 additional functions. Allocation information only needs to be sent once every few frames.
One of the most important application fields of DSI equipment
One method is to use six frames as one assignment frame to suit TDMA satellite communications. Assignment processor 14 explained above
To summarize the functions of 0, (1) Acceptance of new allocation request PCM channel. (2) Detection of inactive DSI channels. (3) Overload channel management. (4) Decision on new allocation. (5) Organizing statistical data such as lockout rate. (6) Perform the above functions within 6 frames and in synchronization with peripheral circuits such as PCM. In particular, functions 1, 2 and 4 are DSI assignments.
This is the basic function of a processor. In conventional DSI equipment, the above functions are realized using dedicated hardware or mini-computers, and when they are implemented using dedicated hardware, the scale of the equipment becomes large due to the need to implement many functions such as those mentioned above. Moreover, it is complicated, and has the disadvantage that the initial adjustment required for production or the time required for repair in the event of a failure becomes long. Furthermore, if it is implemented using a mini-computer, although it is dramatically advantageous in terms of fault diagnosis, it is necessary to implement the function of the assignment processor using a fixed architecture, which poses a problem in terms of speed. new allocation request,
Many parts, such as the PCM channel reception section and the overload channel management section, are not implemented on a minicomputer, but are usually added to external hardware with complex functions capable of high-speed operation. . In addition, assignments and
Theoretically, it is possible to make a new assignment if you have a copy of the register and a table showing the output status of the audio detector. In addition to information on whether a DSI channel number corresponds, a reverse correspondence table that shows which PCM channel number corresponds to a certain DSI channel number also plays an important role, and without such a table, assignments cannot be made. - It is difficult to manage all new allocations and overload channels within a frame (125 μsec x 6 = 750 μsec) due to the speed of the minicomputer. However, it takes a considerable amount of time to create such an inverse correspondence table using software, and a method of re-creating all of these tables for each assignment frame is not currently in use.
On the other hand, with a method that updates the copy of the assignment register and the assignment register inside the minicomputer and the inverse correspondence table from new data determined for each assignment frame, once a malfunction occurs, the assignment If a discrepancy occurs in the registers and the internal tables of the minicomputer, there is a drawback that new assignments cannot be made correctly over several assignment frames. As described above, even if a minicomputer is used, the newly allocated function cannot be realized unless powerful external hardware is used. Therefore, when compared in terms of dedicated hardware and scale,
Compared to the decreasing rate of accessory hardware other than minicomputers, minicomputers have been increasing rapidly, and have been rapidly progressing in recent years. Even if a 1-chip micro CPU (central processing unit) is used as a substitute for a minicomputer, the processing speed is generally slower than that of a minicomputer, so the attached hardware needs to be more robust, and the overall scale is smaller than that of dedicated hardware. There is no difference in comparison. The purpose of the present invention is to maintain the ease of fault diagnosis and flexibility in changing specifications, which are the advantages of using a minicomputer, and to create an external hardware that has functions 1, 2, and 4 of the DSI assignment processor described above. The objective is to provide a hardware-free DSI assignment processor. Another object of the present invention is to provide an assignment processor that can generate a copy of an assignment register and its inverse correspondence table in a short time. The processor of the present invention includes a sequential program reading circuit, a program memory connected to the sequential program reading circuit, a data processing circuit controlled by the program memory, and a processor connected to the data processing circuit that independently performs address setting, data setting, and Two data memories from which data can be read,
a new connection register connected to an output terminal of the data processing circuit; means for receiving the outputs of the voice detection circuit and assignment register shown in FIG. 1 into the data processing circuit; means for changing the assignment register, creating a table that is a copy of the assignment register in one of two independent data memories, and storing the address and contents of the assignment register in the other data memory. It is characterized by creating a correspondence table in which the relationships are reversed. Next, the present invention will be explained in detail with reference to the drawings. First, one embodiment of the present invention will be described with reference to FIG. The processor of the present invention shown in FIG. 4 includes a sequential program reading circuit 200 and a program memory 21.
0, data processing circuit 220, memory address registers 230 and 240, memory data registers 250 and 260, data memories 270 and 280, data acquisition gate 290, new connection register 300, allocation information transmission circuit 310,
Assignment register change circuit 320, assignment register 130, voice detection circuit 110,
PCM channel number input terminal 400, PCM audio input terminal 410, DSI channel number output terminal 4
20, 1st PCM frame synchronization signal input terminal 43
0, new assignment output timing signal input terminal 440
and a clock signal input terminal 450. In FIG. 4, the voice detection circuit 110 includes, for example, U.S. Pat.
39723, and the sequential program readout circuit 200 is described in detail in, for example, the publication "FAIRCHILD BIPOLAR MICROPROCESSOR".
DATABOOK “MACRO LOGIC” P.3-71~P.3
-77, 1976”. Further, the data processing circuit includes a temporary storage memory and an arithmetic logic circuit,
"Advanced Micro Derices The Am 2900
Family Data Book P.5-P.21 1976". Also, assignment register 1
30 is a random access memory that outputs the DSI channel number to which the PCM channel is connected when a PCM channel number is input to the address; if a certain PCM channel is not connected to a DSI channel, the corresponding assignment register is output. It is assumed that the output of 130 is 0. In FIG. 4, considering the case where a PCM96 channel is compressed into a DSI48 channel, the program execution section consisting of a sequential program reading circuit 200, a program memory 210, and a data processing circuit 220 is as follows.
The following explanation assumes that 6 steps of operation are possible per 1 PCM channel (at this time, the program is 212 nsec).
One step will be executed in (na) seconds).
The program memory 210 stores instruction words constituting a program, and these instruction words are directly sequentially read out by the program reading circuit 200 and the data processing circuit 2.
20, memory address register 230 and 2
40, memory data registers 250 and 26
0, data memories 270 and 280, data capture gate 290 and new connection register 3
Controls 00. Sequential program reading circuit 200
determines the address of the program memory 210 where the next instruction to be executed is stored from some fields of the instruction read from the program memory 210 and flag information from the data processing circuit 220. The data processing circuit 220 is activated by a part of other fields of the instruction word read from the program memory 210.
The input data and the internal temporary storage memory of the data processing circuit 220 are calculated by the data processing circuit 220 and output. The output of the data processing circuit 220 is set to either the memory address register 230 or 240, the memory data register 250 or 260, or the new connection register 300, depending on the independent other fields of the instruction word read from the program memory 210. or can be stored in multiple registers. data memory 2
70 indicates that data stored in the memory data register 250 is written to the address stored in the memory address register 230 by part of other fields of the instruction word read from the program memory 210, or the data stored in the memory data register 250 is written to the address stored in the memory address register 230. - The contents of the address stored in the register 230 are connected to the input section of the data processing circuit 220. Similarly,
The data memory 280 writes data stored in the memory data register 250 to the address stored in the memory address register 240 according to part of other fields of the instruction word read from the program memory 210, The contents of the address stored in the memory address register 240 are connected to the input section of the data processing circuit 220 . In other words, the sequential program reading circuit 200,
Program memory 210, data processing circuit 22
0, memory address register 230, memory data register 250 and data memory 270
It becomes a general-purpose data processing device, and
Sequential program reading circuit 200, program memory 210, data processing circuit 220, memory address register 240, memory data register 2
60 and data memory 280 may also serve as a general purpose data processor. However, the memory address register 240 is
Unlike the memory address register 230,
A gate is added to disable one MSB (most significant bit) and is controlled by the program. The audio detection circuit 110 receives a PCM audio signal input from a terminal 410 and an input from a terminal 400.
Based on the PCM channel number signal, it is detected whether or not there is audio on the corresponding PCM channel and output.
Further, although the assignment register change circuit 320 normally simply passes the PCM channel number signal input from the terminal 400 and accesses the assignment register 130, the assignment register change circuit 320 accesses the assignment register 130.
When 0 is updated, the input PCM channel number signal and the PCM 300 in the new connection register are updated.
It has a function of writing the DSI channel number in the new connection register 300 to the assignment register 130 when the channel numbers match.
Details of the assignment register change circuit 320 will be described later. The PCM channel number signal input from terminal 400 is 768kHz (96ch x 8kHz),
The clock frequency input from 50 is
If it is 4.608 MHz (6 steps x 96 channels x 8 kHz), synchronization is performed so that the PCM channel number signal changes every time the sequential program reading circuit 200 changes its output six times (in other words, every time the program advances six steps). Since these signals are generated within the same device, this can be easily realized by providing a clock generation source whose fundamental frequency is a common multiple of these signals. A program as shown in FIG. 5 is stored in the program memory 210. FIG. 5 describes only the processing performed by the data processing circuit 220. Here, A is an internal register of the data processing circuit 220. The operation of the routine for creating a table showing the contents of the assignment register and its inverse correspondence table will be explained using the time chart shown in FIG. As will be explained later, by the end of the previous assignment frame, data memory 280 is filled from number 0 to number 46.
It is necessary to write 0 up to the address to clear it. First, when the first PCM frame synchronization signal (FRAMESYNC in FIG. 6) is input to the terminal 430, the program reading circuit 200 is sequentially reset and outputs 0 to the program memory 210. Therefore, the contents of the program memory address 0, that is, A=0 shown in FIG. 5, are output as an instruction and executed by the data processing section 220. terminal 430
The 1PCM frame synchronization signal is cut off just before the first PCM frame starts, and the program reading circuit 200 sequentially starts operating in accordance with the clock signal input from the terminal 450 from the start of the first PCM frame. First, from FIG. 5, A=1 in the first step.
This is the same as the PCM channel number signal input from terminal 400, and is taken into memory address register 230 and memory data register 260. In the step of FIG. 2, the output of the voice detection circuit 110 is MSB (most significant bit), and the assignment
Data with the output of the assignment register 130 (corresponding DSI channel number) accessed by the PCM channel number that has passed through the register change circuit 320 as the lower bit is loaded into the data processing circuit 220 via the data acquisition gate 290. . This data is sent to the data processing circuit 220
appears at the output of the memory data register 250 and the memory address register 240. At this time, the MSB of the memory address register 240 receives a mask command from part of the instruction word output from the program memory 210 and is invalidated (forced to 0). In other words, the memory address register 240 contains the voice detection circuit 1.
10 outputs are not captured. In the third step, data processing circuit 220 does not perform any calculations. Since a 6-step program can be executed per PCM channel, PCM
This step is placed for the purpose of synchronizing the channel and data processing circuit. Also, at this time, the data memories 270 and 280 receive a write command, and the contents of the memory data register 250 (audio detection circuit 110 The output of the memory address register 240 (in which the DSI channel number is input) is sent to the address indicated by the contents of the memory address register 240 (in which the DSI channel number is input), and the contents of the memory address register 240 (in which the PCM channel number is input) are ) is written. In the fourth step, the numerical value 96 is loaded into the data processing circuit 220 immediately (directly from the program). In the fifth step, the data processing circuit 220
Test if it is less than 96 and check if the PCM channel number has advanced to 96.
The check results are sequentially transmitted to the program reading circuit 200 as flag information. In the sixth step, the program reading circuit 2
00 is based on the flag information transmitted from the data processing circuit 200 in the fifth step, and if A is smaller than 96, that is, in this case, in the seventh step, it will jump to address 1. . After the seventh step, this loop is executed, and the output of the sequential program reading circuit 200 is as shown in FIG.
Run a loop during the first PCM frame in the assignment frame, as shown in SEQ.
2PCM frame by the processor of the present invention.
The process moves on to processing operation for DSI channel assignment (assignment processing), that is, program execution starting from the seventh address of the program memory 210. As a result, when the data memory 270 is accessed using a PCM channel number, it outputs the corresponding DSI channel number and whether or not there is audio on the corresponding PCM channel, and when the data memory 280 is accessed using the DSI channel number, the corresponding PCM channel number is output. can get. In other words, data memory 2
70 becomes a copy of assignment register 130, and data memory 280 becomes an inverse correspondence table of assignment register 130. This situation is shown in FIGS. 7 and 8. What should be noted is the problem of how the expression in the inverse conversion table will be when there is no connection between the PCM channel and the DSI channel, and the problem when a free space occurs in the DSI channel. First, as mentioned above, the former problem is that 0 is stored for unconnected PCM channels in the assignment register, so the unconnected PCM channel number is degenerated to address 0 in the inverse conversion table and is not displayed. However, this is not a problem as such items are not normally used. In the latter case, as mentioned earlier, the data memory 280 was cleared to all 0s towards the end of the previous assignment frame, so any unconnected DSI channels will cause the data memory 280 to
Nothing is written to the address position of that DSI channel number in the above process, so 0 remains.
No inconvenience will occur. The processing operation for DSI channel assignment (assignment processing) by the processor of the present invention will be briefly explained below. New assignment request
Only one PCM channel can be connected to a DSI channel in one assignment frame. Therefore, if there are a plurality of new assignment request PCM channels, the assignment processor must wait and perform the following functions. Became inactive during a meeting
PCM channels are removed from the queue. In the waiting queue, the first to arrive has a higher priority for allocation. A newly generated new allocation request PCM channel is added to the waiting queue. However, the length of the entire waiting queue may be up to 4. The waiting queue, as shown in FIG.
100). in a meeting
This can be determined by accessing the data memory 270 using the PCM channel number and checking the output data. If the MSB (in which the output of the audio detector 110 is stored) is 0, that is, it has become inactive. If so, remove that PCM channel from the queue and move the queue forward. The operation of pushing the matrix forward can be processed in conjunction with the second function described above, and since the entire matrix only needs to have a length of 4, it can be executed in about 100 program steps. To detect a newly generated new allocation request PCM channel, move the data memory 270 from address 1 to 96.
Search up to the address and output the data memory 270.
Detects the PCM channel number storing data in which the MSB (where the output of the audio detection circuit 110 is stored) is 1 and the other lower bits (where the DSI channel number is stored) are all 0. Also, it is checked that the channel number does not match the data in the queue that is already waiting, and the data is added to the queue. The search is continued until the length of the waiting queue as a whole reaches 4 or until the search for detecting a new allocation request PCM channel finishes checking up to PCM96 channels. Considering the worst case, the number of dynamic steps required to execute this program is about 900 steps. Therefore, detection and management of newly allocated PCM channels can be performed during the second and third PCM frames even in the worst case during the assignment frame. The following processing is required to select allocatable DSI channel numbers. Detection of unconnected DSI channels Detection of inactive DSI channels Detection of unconnected DSI channels or inactive DSI channels
Detection and selection of DSI channels can be accomplished using data memories 270 and 280.
The data memory 280 is searched from address 1 to address 46 (corresponding to the DSI channel number), and the output of the data memory 280 is the DSI address given as the address.
Since this is the PCM channel number that corresponds to the channel number, if this is 0, it means that the corresponding DSI channel number is not connected, and a non-connected DSI channel can be detected. On the other hand, data memory 2
If the output of 80 is non-zero, the DSI channel number given as the address is the data memory 280.
The DSI channel is connected to the PCM channel whose number is the output of
It is only necessary to check whether the MSB of the output (in which the output of the voice detection circuit 110 is stored) is 0 or not. If this is 0, an inactive DSI channel has been detected. This step ends when an unconnected DSI channel or an inactive DSI channel is detected, or when all DSI channels (46 channels) have been searched. In the worst case, this process is approximately
It can be executed in 600 steps (about 1 PCM frame), and the DSI channel selection routine can be completed during the 4th PCM frame. The DSI channel and PCM channel assignment function is performed as follows. DSI channel selected and new allocation request
If a PCM channel exists in the queue, the elected DSI channel and new allocation request
One combination of PCM channels can be determined. If a DSI channel is not selected or a new allocation request PCM channel does not exist, the transmitting DSI device transmits the contents of the assignment register 130 to the receiving side, and even if a malfunction occurs between transmission and reception, the malfunction will not continue. It is necessary to perform a refresh operation so that a set of PCM channels and DSI channels indicating the current allocation is selected from the contents of the data memory 280 and used as a new allocation. This routine can be completed within about 100 steps. The point at which these new allocations are determined varies depending on the flow of the program in managing the PCM channel requesting new allocation and selecting an unconnected or inactive DSI channel. Therefore, the determined new allocation data is transferred to terminal 4.
After waiting until the new assignment output timing signal inputted from 40 is sequentially inputted to the program reading circuit 200, it is transferred to the new connection register 300. The allocation information input to the new connection register 300 is transmitted to the receiving DSI device by the allocation information transmission circuit 310, and the PCM channel data part of the contents of the new connection register 300 matches the PCM channel number input from the terminal 400. When this happens, the DSI channel data of the contents of the new connection register 300 is transferred to the assignment register change circuit 3.
20 to the assignment register 130 (new assignment), and also write to the new connection register 30
When the DSI channel data containing 0 matches the output of the assignment register 130, the assignment register change circuit 320 is used to write 0 to the assignment register 130. (Old Allocation) The processing that the assignment processor must perform during the remaining time is to clear data memory 280 in preparation for the next assignment frame. This can be accomplished by simply accessing data memory 280 from address 1 to address 46 and writing 0, and the program can be implemented in 300 steps or less. The processing to be executed in the assignment frame can be summarized as follows.

[Table] A specific example of the assignment register changing circuit indicated by reference numeral 320 in FIG. 4 is shown in FIG. The assignment register change circuit shown in FIG.
4, 3205 and 3206, zero input terminal 32
07, a PCM channel number input terminal 400 and a timing signal input terminal 3210. Since the timing signal input from the terminal 3210 is off except during one PCM frame that permits rewriting of the assignment register 130, it is output to the write enable terminal W of the assignment register 130 for other PCM frames. Never. The PCM frame in which the timing signal is turned on is determined by the transmission method of allocation information, etc., and for convenience, it is assumed to be the fourth PCM frame here. Therefore, during the assignment frame, time assignment registers 130 other than the fourth PCM frame are accessed by the PCM channel number signal input from terminal 400. New assignment information is transferred to the new connection register 300 in the fifth PCM frame of the previous assignment frame. As mentioned above, the new allocation information includes a set of PCM channel numbers, DSI channel numbers, and these PCM channel numbers.
It consists of mode information indicating whether to connect (on) or disconnect (off) between the channel and the DSI channel. First, a case where the mode information is on in the fourth PCM frame will be described. The PCM channel number signal input from the terminal 400 and the PCM channel number part in the new connection register 300 are compared by the matching circuit 3203, and a new connection request is made.
When a PCM channel time slot arrives, a match signal is output. In the gate 3204, the mode information is on and the output of the matching circuit 3203 is on, so the selection signal input terminal of the selection circuit 3201 is turned on. The selection circuit 3201 selects the DSI channel section of the new connection register 300 when the selection signal is on, and selects the DSI channel section of the new connection register 300 when the selection signal is off.
In order to select the zero input from 207, the data input terminal DI of the assignment register 130
The newly connected DSI channel number is conveyed to .
Also, at this time, since the output of the matching circuit 3203 passes through gates 3205 and 3206, the newly connected DSI channel number is written in the address position of the new assignment request PCM channel number input from the terminal 400 in the assignment register 130. It turns out. Furthermore, the output of the assignment register 130, that is, the DSI channel number,
The matching circuit 3202 compares the DSI channel number section of the new connection register 300, and if a matching DSI channel is detected, the current
The PCM channel number and DSI channel number were connected until the previous assignment frame, and must be disconnected in order to make a new connection in the current assignment frame. At this time, since the output of the matching circuit 3203 is normally off, the gate 3204 is closed and the selection circuit 3201
The zero value input from the terminal 3207 is selected. On the other hand, the output of match circuit 3202 is on and provides a signal to write command terminal W of assignment register 130 through gates 3205 and 3206. Therefore, zero is written to the corresponding PCM channel number address in the assignment register 130, and the disconnection can be executed. Next, a case where the mode information is off will be explained. This situation is necessary when performing the refresh mentioned above, and although it is not directly related to the embodiment of the present invention, it is necessary to avoid overload in a DSI device using the above-described overload channel. Necessary for cutting channels, etc. In this case, the information stored in the new connection register 300
All you have to do is disconnect the PCM channel number and DSI channel number.The difference from when the mode information is on is that the matching circuit 3203 is on and the corresponding PCM
When notifying that the time slot of a channel has been reached, instead of writing the DSI channel number stored in the new connection register 300 to the assignment register 130, it is sufficient to write zero. This can be achieved because the selection circuit 3201 selects the zero value added from the terminal 3207 since the gate 3204 is always off based on the mode information. As described above, according to the present invention, a copy of the assignment register and its inverse correspondence table can be generated in the first PCM frame, thereby easily realizing the subsequent assignment determination. Furthermore, according to the present invention, various assignment processes including allocation decisions can be realized with a single piece of hardware, no special external circuit is required, and the scale of the assignment processor can be made smaller compared to conventional ones. . Furthermore, since the present invention is an assignment processor that is controlled by a program, failure diagnosis can be easily realized by preparing a failure diagnosis program. Self-diagnosis can also be performed in real time if there is enough time for the steps. In the present invention, the program execution speed of the assignment processor is set to 6 steps per PCM channel, but this is not essential. If a data processing circuit is used, the program execution speed will be further improved.
The device can be realized. Further, in the present invention, reference numeral 24 in FIG.
Memory address registers indicated by 0 are MSB
However, by reducing the capacity of the data memory 280 and masking the memory address.
The MSB of register 240 may not be connected to the address section of memory 280.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a general DSI transmitter/receiver, FIG. 2 is a diagram showing the contents of the assignment register 130 in FIG. 1, and FIGS. A diagram showing correspondence, FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is a diagram showing an embodiment of the present invention.
6 is an operation timing diagram of FIG. 4, FIG. 7 is a diagram showing the contents of the data memory 270 of FIG. 4, and FIG. FIG. 4 is a diagram showing the contents of data memory 280, and FIG. 9 is a diagram showing a specific example of the assignment register changing circuit of FIG. 4. In FIG. 4, 200...sequential program reading circuit, 210... program memory, 220
...Data processing circuits, 230 and 240...Memory address registers, 250 and 260...
...memory data registers, 270 and 280
...Data memory, 290...Data acquisition gate, 300...New connection register, 310...
Assignment information transmission circuit, 320... Assignment register change circuit, 130... Assignment register, 110... Voice detection circuit, 400...
PCM channel number input terminal, 410...PCM
Audio input terminal, 420...DSI channel number output terminal, 430...1st PCM frame synchronization signal input terminal, 440...new allocation output timing signal input terminal, 450...clock signal input terminal.

Claims (1)

[Scope of Claims] 1. A voice detector detects whether or not there is voice in each pulse code modulation channel from the multiplexed input pulse code modulation signal, and connects the input pulse code modulation channel and the output digital voice insertion channel. Determine a new assignment between the pulse code modulation channel and the digital audio insertion channel in the digital audio insertion device that connects the input pulse code modulation channel where audio exists to the output digital audio insertion channel using the allocation register indicating the correspondence with the input pulse code modulation channel. A digital audio insertion processor that includes a sequential program reading circuit, a program memory connected to the sequential program reading circuit, a data processing circuit connected to the program memory, and a data processing circuit connected to the data processing circuit and connected to the program memory. The outputs of the first and second data memories in which address setting and data setting are performed, the new connection register connected to the data processing circuit, and the outputs of the voice detector and the assignment register are connected to the data processing circuit. and means for changing the allocation register according to the contents of the new connection register, and the first data memory is configured to input a pulse code modulation channel to the first data memory via the data processing circuit for each assignment frame. Write the contents of the assignment register so that the channel number for digital audio insertion is output when the address is specified by a number, and write the contents of the second assignment register.
A DSI digital audio system characterized in that the contents of the allocation register are loaded into the data memory so that the pulse code modulation channel number is output when an address is specified using the digital audio insertion channel number, and these operations are performed simultaneously. Insertion processor.