JPS6148301B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is applicable to digital speech (Digital Speech).
Interpolation (DSI) device processor. In a typical telephone conversation, one person is only listening while the other person is speaking, and both parties are often silent. Therefore, on a time-average basis, the transmission path is only used for about 1/2 or less of the time. Taking advantage of this fact, DSI equipment increases the efficiency of transmission path usage by transmitting only the portion where voice is present, approximately doubling the capacity of existing POM lines. The theory of DSI equipment is explained in the publication “Digital Speech Interpolation” COMSAT
TECHNICAL REVIEW, Vol.6, No.1, Spring
1976”. The configuration of such a DSI device is shown in Figure 1. Reference number 1 is the transmitting side DSI device, reference number 2 is the receiving side DSI device.
Showing DSI equipment. The transmitting DSI device 1 includes a voice detector 110, a transmitting voice memory 120, a transmitting assignment register 130, and an assignment processor 140, and is configured to transmit a PCM channel 2.
Compress to DSI channel 3 and PCM channel 2
New connection information with the DSI channel 3 is transmitted to the receiving DSI device via the allocation information signal line 4.
The receiving DSI device 2 includes an assignment information receiver 150, a receiving assignment register 160, and a receiving audio memory 170, and transmits PCM data from the DSI channel 3 and the assignment information signal line 4 to the PCM channel 5.
Replay the state of channel 2. In transmitting side DSI device 1, input PCM channel 2
Of the signals, only the channel with audio is written to the transmitting side audio memory 120 under the control of the transmitting side assignment register 130 and read out as the signal of DSI channel 3. The transmission side assignment register 130 indicates the correspondence between PCM channel numbers and DSI channel numbers. For convenience of explanation, suppose that the transmission side assignment register 130 has a correspondence relationship as shown in FIG.
The relationship between is shown in FIG. In other words, PCM channel number 1 has DSI channel number 2, PCM channel 3 has DSI channel number 1,
Assume that DSI channel number 3 is assigned to PCM channel number 4. At this time, for example,
When PCM channel number 7 has audio (hereinafter referred to as active), the audio detector 110
detects that PCM channel number 7 is active. Assignment processor 140
searches for the DSI channel number that is not active (in the case of Figure 2, it is DSI channel number 4),
A new connection is determined, sent as assignment information, and the sending assignment register 130 is rewritten.
The allocation information consists of a part indicating connection or disconnection, a PCM channel number part, and a DSI channel number part. In the receiving DSI device 2, the contents of the receiving assignment register 160 are updated according to the assignment information received by the assignment information receiver 150 and track the contents of the transmitting assignment register 130. As a result, the received DSI signal obtains an output PCM signal by performing the reverse operation of the operation performed on the transmitting side. Even if the PCM channel number connected to a DSI channel is no longer active, the assignment processor 140 can connect the DSI channel to another channel.
It will remain connected unless you assign it to a PCM channel. Since the number of DSI channels is fixed, sometimes PCM channel numbers greater than the number of DSI channels become active, resulting in the inability to transmit the first part of audio. This situation temporarily degrades the precision of the PCM word (one sample value of the PCM) from 8 bits to 7 or 6 bits, and virtually
Significant improvement can be achieved by increasing the number of DSI channels. For example, if the number of PCM channels is 8 as shown in Figure 3a, and the number of DSI channels is 4 as shown in Figure 3b, then if all the PCM words transmitted on the DSI channels are 6 bits, the total Therefore, the number of DSI channels can be increased by one. DSI equipment is usually equipment that targets RCM60 channels or more. For example, in a system that compresses 96 channels consisting of 4 PCM24 lines into 48 DSI channels,
By making the PCM word a 7-bit transmission, six new channels can be generated, and by making the PCM word a 6-bit transmission, six new channels can be added. These newly added channels are respectively called overload 1 channel (hereinafter abbreviated as OL1CH) and overload 2 channel (hereinafter abbreviated as OL2CH). In contrast, the original DSI channel will be referred to as a normal channel (hereinafter abbreviated as NCH). If an overload channel is used, assignment processor 140 may
If there is a channel with no audio (hereinafter referred to as inactive) and there is no new connection request,
In order to improve the accuracy of the PCM word, it is necessary to reallocate the PCM channel connected to the overload channel to the inactive NCH. Even if these targets are taken, they cannot be assigned to a DSI channel even though they are active.
A PCM channel may also be present. The ratio of unallocated PCM channels to active PCM channels in a unit time is called the lockout rate, and if the DSI device shows an abnormally high lockout rate, the assignment processor can also inform the outside world of this. 140 additional functions. Allocation information only needs to be sent once every few frames.
One of the most important application fields of DSI equipment
One method is to use six frames as one assignment frame to suit TDMA satellite communications. Assignment processor 14 explained above
To summarize the functions of 0, (1) Acceptance of new allocation request PCM channel. (2) Detection of inactive DSI channels. (3) Overload channel management. (4) Decision on new allocation. (5) Organizing statistical data such as lockout rate. (6) The above functions must be performed within 6 frames in synchronization with peripheral circuits such as PCM. Conventional DSI devices are realized by combining dedicated hardware that performs the various functions described above, or by using a minicomputer. If it is implemented using dedicated hardware, the scale of the device will be large and complex due to the need to implement the many functions described above, and it will also have the disadvantage that the initial adjustment time required during production and the repair time in the event of a failure will be long. In addition, the configuration using a minicomputer is
Although it has the advantage of being able to alleviate the drawbacks of the configuration achieved with the above dedicated hardware, it is insufficient in terms of processing speed, and the above functions (1), (2) and (3) of the above assignment processor Many of the functions of are still realized by dedicated hardware, and only parts such as determining new allocations are realized by minicomputers, so the scale is not so small compared to dedicated hardware. Furthermore, whether the assignment processor is implemented using only dedicated hardware or a minicomputer, functions (1) and (2) of the assignment processor described above are performed by dedicated hardware, and the complexity of the dedicated hardware increases. As a compromise in terms of functionality, new allocation requests for PCM channels are accepted in descending order of PCM channel numbers, and available DSI channel numbers are also selected in descending order of the currently connected PCM channel numbers. It is being As a result, new allocation requests for PCM channels will not be accepted.
The one with the lower PCM channel number has higher priority, and even if the channel with the lower PCM channel number is connected to the DSI channel,
As soon as channels with higher PCM channel numbers become inactive, they are deallocated for other assignments, resulting in unfair service provided by PCM channel numbers. An object of the present invention is to provide a small-scale DSI processor that facilitates fault diagnosis by configuring a DSI assignment processor that performs the above functions (1) and (2) using a microprocessor or the like. . Another object of the present invention is to provide a DSI assignment processor that provides fair assignment services to all PCM channels without depending on the arrangement order of the PCM channels. The processor of the present invention includes a central processing circuit, a new connection request pulse code modulation channel register connected to the data bus of the central processing circuit, and an available digital audio insertion channel register connected to the data bus of the central processing circuit. a new connection register connected to a data bus of the central processing circuit; means for inputting the output of the voice detector and the output of the allocation register to the data bus of the central processing circuit; and information on the new connection register. means for updating the allocation register; and means for updating the new connection request pulse code modulation channel register and the available audio insertion channel register in each period for determining a combination of a set of pulse code modulation channels and audio insertion channels. Writing is permitted for one cycle of the pulse code modulation channel, and the time at which the write permission starts is set to 1 for each cycle in which a combination of a set of pulse code modulation channels and a channel for audio insertion is determined.
a time window generator that delays the permission start time by the number of multiplexed pulse code modulation channels and advances the permission start time by the number of multiplexed pulse code modulation channels when delayed by the number of multiplexed pulse code modulation channels; means for capturing a pulse code modulation channel number requesting new connection from the output of the audio detection circuit and the output of the time window generator into the new connection request pulse code modulation channel register; The apparatus further comprises means for loading an available audio insertion channel number into the available audio insertion channel register based on the output of the detection circuit and the output of the time window generator. An embodiment of the present invention will be described with reference to FIG. The DSI processor in FIG. 4 includes a central processing circuit 400, a new connection request PCM channel register 410, and an available DSI channel register 42.
0, new assignment register 430, voice detection circuit 11
0, assignment register 130, data write gate 440, assignment register change circuit 450,
Time window generator 460, register timing generation circuit 470, PCM audio input signal terminal 480, PCM
Channel number input signal terminal 490, DSI channel number output signal terminal 500, reset signal terminal 510, new connection timing signal input terminal 520
and an assignment message output terminal 530. In FIG. 4, the voice detection circuit 110 is described in detail in Patent Publication No. 120317 of 1972, and the central processing circuit 400 is also described in the publication ``Advanced''.
Micro Devices The Am2900Family Date Book
P.43, 1976”. As shown in FIG. 2, the assignment register 130 is a random access memory that outputs the DSI channel number to which the PCM channel is connected when a PCM channel number is input to the address. The fact that a channel is not connected to a DSI channel is distinguished from others by the fact that the address position of the corresponding assignment register 130 is set to 0. In addition, the new connection request PCM channel register is a memory (First In First Out memory) in which four or more pieces of data can be read out in the order in which they are written.
×4FIFO SERIAL MEMORY, Oct.1976”. Figure 4 shows an example of a DSI processor that compresses a PCM96 channel into a DSI48 channel.To make it easier to distinguish the overload DSI channel from the normal DSI channel, the channel number of OL1 (7-bit overload channel) is 65. to 70, OL2 (6-bit overload
Channel numbers shall be from 97 to 102. In this way, if bit 7 of the DSI channel number is 1 and bit 6 is 0, it belongs to OL1, and similarly, if bit 7 of the DSI channel number is 1 and bit 6 is 1, it easily belongs to OL2. Can be distinguished. The available DSI channel register 420 includes three registers described later, namely, a register for storing available normal DSI channels, and a register for storing available normal DSI channels.
It has a register for storing OL1DSI channels and a register for storing available OL2DSI channels. The computing power of the central processing circuit 400 is assumed to be capable of performing 6 steps of operation in 1 PCM channel time slot (4.5 MHz operation is possible). Details of the available DSI channel register 420, assignment register modification circuit 450, time window generator 460, and register timing generation circuit 470 are described below. Next, the present invention will be explained in detail with reference to FIG. First, a reset signal is input to the terminal 510 in synchronization with the start of each assignment frame, notifying the central processing circuit 400 of the start of the assignment frame, and starting the assignment program.
At the same time, an operation start permission command is given to the time window generation circuit 460, and the new connection request PCM channel register 410 and the available DSI channel register 420 are cleared. Since the central processing circuit 400 and the time window generation circuit 460 operate in parallel up to the second PCM frame, the operation of the central processing circuit 400 will be explained first. A reset signal input from terminal 510 causes central processing circuit 400 to open data capture gate 440 and capture the outputs of assignment register 130 and voice detection circuit 110 into internal memory. The audio detection circuit 110 outputs the presence or absence of audio on the corresponding PCM channel in synchronization with the PCM channel number signal inputted from the PCM audio input signal inputted from the terminal 480 and the PCM channel number signal inputted from the terminal 490. . Additionally, the assignment register change circuit 450
In the first and second PCM frames, the PCM channel number signal input from the terminal 490 is directly transmitted to the assignment register 130. Synchronize and output the DSI channel number to which the corresponding PCM channel is connected. Therefore, the central processing circuit 400 calculates the MSB (Most
The output of the voice detection circuit 110 is added to the Significant Bit (most significant bit) side, and it is made into one data.
Central processing circuit 40 via capture gate 440
Start writing from address 1 of internal memory 0. The central processing circuit 400 has 1 PCM channel.
Since six steps of operation are possible per time slot, the aforementioned data acquisition gate 440
By completing writing to the internal memory of the central processing circuit 400 via 6 steps and repeating the same process 96 times, addresses 1 to 96 of the internal memory of the central processing circuit 400 are written in correspondence with the PCM channel number. The output of assignment register 130 and the output of voice detection circuit 110 are written. This process ends in synchronization with the end of the first PCM frame in the assignment frame. In the second PCM frame, the central processing circuit 400 sequentially loads the data written in the previous PCM frame from address 1 to address 96 in the internal memory, masks the MSB that is the voice detector output, and masks the numeric value 1.
00 is added as a new address, and the address where the original data was stored is written as data at that address position. As a result, if you add 100 to the DSI channel number and access the internal memory, it will be connected to the DSI channel number.
The PCM channel number will be output.
As described below, the previous assignment frame
Internal memory address 1 in 5PCM frame
Since 0 is written from address 00 to address 202, if a certain DSI channel is not in use, accessing the internal memory using the DSI channel number plus 100 will result in 0 being output. Note that addresses 100 to 146 correspond to normal DSI channels, and addresses 165 to 146 correspond to normal DSI channels.
From address 170 corresponds to the OL1DSI channel, from address 197 to address 202
Compatible with OL2DSI channel. Since the above processing is approximately the same as the processing in the first PCM frame, it ends during the second PCM frame. As a result, the internal memory of the central processing circuit 400 stores data as shown in FIG. On the other hand, the time window generation circuit 460 outputs an ON signal for the length of one PCM frame over two frame intervals of the first PCM frame and the second PCM frame, and the time window generation circuit 460 outputs an ON signal for each assignment frame. The point in time is delayed by 1 PCM channel time slot. In other words, in a certain assignment frame, the time window generation circuit 4
60 outputs from the 60th PCM channel timeslot in the first PCM frame and up to the 59th PCM channel timeslot in the second PCM frame, then in the next assignment frame it outputs from the 61st PCM channel of the first PCM frame. - The time window generation circuit 460 operates and outputs from the time slot, and turns off at the 60th PCM channel time slot of the second PCM frame. However, if the time window generation circuit 460 starts outputting in a certain assignment frame at the 96th channel time slot of the first PCM frame, and outputs up to the 95th channel time slot of the second PCM frame, then
The output start point of the time window generation circuit 460 in the next assignment frame returns to the beginning, and
Starting from the first PCM channel time slot of one PCM frame. Register timing generation circuit 470 performs the following operation only when the output of time window generation circuit 460 is on. In addition to the output of the time window generation circuit 460, the register timing generation circuit 470 also includes the voice detection circuit 11.
0 and the output of the assignment register 130 are input, and as mentioned above, the output of the assignment register 130 is input to the terminal 4.
In synchronization with the PCM channel number signal input from 90, a signal indicating whether or not there is audio in the corresponding PCM channel and a connected DSI channel number are output. Therefore, the register
The timing generation circuit 470 is the time window generation circuit 46
0 starts outputting, and the output of the audio detector 110 indicates the presence of audio, and the output of the assignment register 130 is zero (that is, even though there is audio on the corresponding PCM channel). (indicating that it is not yet connected to a DSI channel), outputs a timing pulse to the new connection request PCM channel register 410. As a result, even though the new connection request PCM channel register 410 has the above voice,
A PCM channel number input from terminal 490 for a PCM channel not connected to a DSI channel is written. If multiple such PCM channels exist, multiple
The PCM channel is input to the new connection request PCM channel register 410, and as described above, the new connection request PCM channel register 4
Since 10 is a FIFO memory, the first input is stored with higher priority. Further, the register timing generation circuit 470 generates a signal from the corresponding PCM channel when the time window generation circuit 460 has an output, the output from the audio detector 110 indicates no audio, and the output from the assignment register 130 is not zero (i.e., when the corresponding PCM channel number indicates no audio but connected to DSI channel), available
DSI channel register 420 contains timing information.
Output pulse. As a result, the available DSI channel register 420 has no audio.
The DSI channel number connected to the PCM channel is input from the assignment register 130. At this time, in the available DSI channel register 420, the assignment register 130
From the output, is it a normal DSI channel?
After determining whether it is an OL1/DSI channel or an OL2/DSI channel, the three internal registers of the available DSI channel register 420, namely, the available normal DSI channel register, the available OL1/DSI channel register, and the available Give to either OL2 or DSI channel register. Once one piece of data is written to each of these three internal registers, no other data will be accepted. As a result of the above, new connection request PCM channel
Register 410 and available DSI channels
Regarding the PCM channel number and DSI channel number given to the register 420, those that match the conditions early within the time window of the time window generation circuit 470 are selected and determined by the register timing generation circuit 470, and the time window generation circuit 460 Since the working point moves by one PCM channel time slot every assignment frame, the priority of PCM channel numbers and DSI channel numbers that may be captured in the registers changes every assignment frame. Therefore, on average, there is no priority depending on the channel number. As described above, the central processing circuit 400 and the time window generation circuit 460 up to the second PCM frame, which are the core of the present invention.
Although the operation has been explained, the flow of the allocation process will be briefly explained below. An overview of the items to be executed by the DSI processor in one assignment frame, including those to be performed by the second PCM frame, is as follows.

[Table] The allocation processing from the third PCM frame will be described below. New connection request PCM channel can only be connected to one DSI channel in one assignment frame. For this reason, the assignment
If there are multiple new connection request PCM channels, the processor must wait. Newly connected PCM channel register 410
has a FIFO function and stores multiple new connection request PCM channel numbers in order of priority.
Since all data in the new connection request PCM channel register 410 is cleared by a reset signal input from the PCM channel register 410, the data in the new connection request PCM channel register 410 cannot be used in the next assignment frame, and it does not have the advanced queuing function described below. New connection request PCM required by DSI Assignment Processor
The function of the channel number queue is as follows. PCM channel numbers that become inactive during a queue are removed from the queue. In the waiting queue, the first to arrive is given a higher allocation priority, and the PCM channel number used in the previous assignment frame is excluded. Adds the newly generated new connection request PCM channel to the waiting queue. However, the length of the entire waiting queue may be up to 4. The queue can be implemented using the internal memory of central processing circuit 400 and is illustrated in FIG. First, in order to realize the first function above, PCMs in the new connection request PCM channel queue
When the internal memory of the central processing circuit 400 is accessed using the channel number and the MSB of the output data (in which the output of the audio detector 110 is stored) is 0, that is, when the PCM channel becomes inactive. , remove that PCM channel number from the queue, and move the queue forward. The operation of pushing the matrix forward can be processed in conjunction with the above function, and since the entire matrix only has a length of 4, it can be executed in about 100 program steps. The above function is for new connection request PCM channel.
New connection request stored in register 410
The PCM channel number is loaded into the central processing circuit 400, and the assignment is determined in the previous assignment frame, and the first , in the second PCM frame, it is checked that the contents of the assignment register 130 do not match the PCM channel for which the contents have not been changed, and the frames are added to the above-mentioned waiting queue. Whether the overall waiting queue length is 4 or new connection request PCM channel register 4
The queue continues to be updated until 10 is empty, which takes about 200 steps. That is,
Updating the queue requires a total of about 300 steps and ends in the middle of the third PCM frame. The selection of available DSI channels is done in three cases: (A) Detect and use unconnected normal DSI channels (B) Use from available DSI channel register 420 (C) Detect and use unconnected OL1 and OL2 DSI channels Normally, the DSI system is used when there is no audio on the PCM channel. Also connected to normal DSI channel and connected DSI channel to other PCM
It remains connected until it is used for a channel, and any normal DSI channel is always connected to some PCM channel. However, when the power is turned on or the power is momentarily interrupted, the connection is normal.
DSI channel occurs. For this reason, it is necessary to detect unconnected normal DSI channels, and this is done by inspecting the internal memory of the central processing circuit 400 shown in FIG. If any of them is 0, it can be seen that the DSI channel whose value is 100 subtracted from the value at that address is not connected. Normal available
It is only necessary to find one DSI channel, and it is not connected.
This process ends if even one DSI channel is found. If no unconnected DSI channels are found,
In the method (B) above, the data stored in the available DSI channel register 420 is used as the available DSI channel. Available
Also within the DSI channel register 420,
The priority is to use data from registers for available normal DSI channels, available OL1DSI
Data from the channel register is used, and data from the available OL2DSI channel register is used. If the available DSI channel register 420 is empty, method (C) above, i.e.
Detects and uses unconnected OL1 and OL2DSI channels. To detect an unconnected OL1DSI channel, check addresses 165 to 170 of the internal memory of the central processing circuit 400 (see Figure 6), and check if the contents are 0.
The unconnected OL1DSI channel is the address number minus 100. If no available DSI channels have been detected yet, check addresses 197 to 202 of the internal memory of the central processing circuit 400 (see FIG. 6) to detect unconnected OL2DSI channels;
It is determined by subtracting 100 from the address number whose content is 0. If an available DSI channel cannot be detected using the above three methods (A), (B), and (C), new connections cannot be made, but
Performs processing related to improving the performance of the DSI assignment system. The above processing requires approximately 500 steps and ends in the middle of the 4th PCM frame in the worst case. The new allocation decision is made as follows. New connection request PCM channel queue (see Figure 5)
If there is data and there is an available DSI channel, prepare this PCM channel and DSI channel as new allocations, turn on the mode bit that determines whether to connect or disconnect, and create a new one to indicate connection. Connection request PCM channel
If there is no data in the queue, the next decision is made. Disconnect inactive OL2, OL1, and DSI channels Execute reassignment ´ Change from OL2DSI channel to normal DSI channel ´ Change from OL1DSI channel to normal DSI channel ´ Change from OL2DSI channel to OL1DSI channel Execute refresh This is done because it is necessary to minimize the use of overload channels and return the data accuracy of the PCM channel to 8 bits. OL2DSI channel or OL1DSI with no audio
The channels are the same as those stored in the available DSI channel register 420 and are
If there is data in an available overload DSI channel register in the DSI channel register 420, the overload DSI channel is associated with PCM channel number 0 and the connection is disconnected. Also, as mentioned above, the mode at this time
The bit is set off to indicate a disconnect. Even if an inactive overload DSI channel cannot be obtained by using the available DSI channel register 420 and connection cannot be disconnected, if a usable DSI channel has been obtained in a previous process, the following is shown. Perform reallocation. Reassignment means that when a certain PCM channel is connected to an overload DSI channel, and there is no new connection or disconnection as shown above, and there is a normal DSI channel available, the PCM channel and overload DSI channel will be reassigned. The purpose of this invention is to improve the accuracy of data on a PCM channel by disconnecting a set of load DSI channels and simultaneously connecting an available normal DSI channel to the PCM channel. connected to an overload DSI channel, as described below.
The PCM channel number is a queue called an overload escape queue (hereinafter referred to as OL1 queue queue for overload 1 and OL2 queue queue for overload 2).
It is registered and managed in the internal memory of 0 (see Figure 5). First, there is a DSI channel available, and when it is a normal DSI channel, it is an OL2 matrix or
If there is data in the OL1 matrix, the OL2 matrix or the PCM channel number in the OL1 matrix and the available normal DSI channel are reallocated, and the mode bit is turned on to indicate the connection. At this time, the DSI channel assigned to the PCM channel is automatically disconnected by the assigned memory change circuit 450, which will be described later. At this time, it is assumed that selection from the OL2 matrix described above has a higher priority than selection from the OL1 matrix described above. Available DSI channels are overload 1
If so, reallocation is possible only from overload 2, the PCM channel number in the OL2 matrix mentioned above and the available OL1DSI channel are used as a new connection, and the mode bit is turned on to indicate the connection. When new assignment, overload channel disconnection, and reassignment cannot be performed, the DSI processor uses a refresh routine to select a set of DSI channels and PCM channels from the contents of the current assignment register and directly assigns them as a new assignment. use This operation can prevent mismatches in the contents of the assignment register between the transmitting DSI device and the receiving DSI device due to transmission errors, momentary power interruptions, and the like. The new allocation process described above is not a complicated process and can be completed in a few dozen steps. Once a new allocation is determined, it is necessary to continue updating the OL1 matrix or the OL2 matrix based on the result. The method for updating these matrices is as follows. If an overload DSI channel is used for new allocation, add the connected PCM channel number to the corresponding overload channel matrix (OL1 matrix or OL2 matrix). If the new assignment is a disconnection from an overload channel, the PCM channel number connected to the overload channel in the corresponding overload channel matrix (OL1 matrix or OL2 matrix) is deleted.
The same applies to reallocation. This process is performed from the OL2DSI channel to the OL1DSI
In the case of reallocation to a channel, it is necessary to update both the OL1 and OL2 matrices, which takes the longest time. However, since the length of each matrix is 6 or less, about 200 steps are sufficient. From the above explanation, the worst case is that the new allocation is determined and the overload matrix is updated at the beginning of the fifth frame. In the remainder of the fifth frame, the central processing circuit 400 starts from address 100 of the internal memory shown in FIG.
Clear address 206. As mentioned above, this is the processing in the 4th PCM frame of the next assignment frame, that is, the DSI channel number is set to the value 100.
If the internal memory is accessed by adding
This is to enable detection of the DSI channel as 0. This process requires about 300 steps and can be accomplished during the 5th PCM frame. When a new assignment timing signal inputted from the terminal 520 is inputted to the central processing circuit 400 in synchronization with the end of the fifth PCM frame, the central processing circuit performs one of the new assignment, disconnection, and reassignment in this assignment frame. The set of the determined PCM channel number and DSI channel number or the set of the PCM channel number and DSI channel number determined by the refresh routine is transferred to the new connection register 430, and then the next assignment. The central processing circuit does nothing until a frame appears. The new connection register 430, as described above,
The data consists of a PCM channel number, a DSI channel number, and a mode bit indicating either connection or disconnection. The assignment register 130 is updated according to the new connection in synchronization with the device. Assignment register change circuit 450 updates assignment register 130 according to new connection register 430. From the above description, the central processing circuit 400 of the present invention
It can be seen that new assignments can be made within the assignment frame. FIG. 6 is a diagram illustrating assignment register change circuit 450 of FIG. 4 in detail. The assignment register change circuit shown in FIG. 6 includes a new connection register 430, an assignment register 130, a selection circuit 4301, and a matching circuit 430.
2 and 4303, gate circuits 4304, 430
5 and 4306, zero input terminal 4307,
It consists of a POM channel number input terminal 490 and a timing signal input terminal 4310. Since the timing signal input from the terminal 4310 is off except during one PCM frame that permits rewriting of the assignment register 130, it is output to the write enable terminal W of the assignment register 130 for other PCM frames. Never. The PCM frame in which the timing signal is turned on is determined by the transmission method of allocation information, etc., and for convenience, it is assumed to be the fourth PCM frame here. Therefore, during the assignment frame, time assignment registers 130 other than the fourth PCM frame will be accessed by the PCM channel number signal input from terminal 490. New assignment information is transferred to the new connection register 430 in the fifth PCM frame of the previous assignment frame. As mentioned above, the new allocation information is a set of PCM channel numbers and
DSI channel number and whether to connect these PCM channels and DSI channels (on)
or mode information indicating whether to disconnect (off). First, a case where the mode information is on in the fourth PCM frame will be described. The PCM channel number signal input from the terminal 490 and the PCM channel number part in the new connection register 430 are compared by the matching circuit 4303, and a new connection request is made.
When a PCM channel time slot arrives, a match signal is output. In the gate 4304, the mode information is on and the output of the matching circuit 4303 is on, so the selection signal input terminal of the selection circuit 4301 is turned on. The selection circuit 4301 selects the DSI channel section of the new connection register 430 when the selection signal is on, and selects the DSI channel section of the new connection register 430 when the selection signal is off.
In order to select the zero input from 307, the data input terminal DI of the assignment register 130
The newly connected DSI channel number is conveyed to .
Also, at this time, since the output of the matching circuit 4303 passes through gates 4305 and 4306, the newly connected DSI channel number is written in the address position of the new assignment request PCM channel number input from the terminal 490 in the assignment register 130. It turns out. Furthermore, the output of the assignment register 130, that is, the DSI channel number, and the DSI channel number part of the new connection register 430 are compared by a matching circuit 4302, and if a matching DSI channel is detected, the current PCM channel number is and DSI channel number were connected until the previous assignment frame, and must be disconnected in order to establish a new connection in the current assignment frame. At this time, since the output of the matching circuit 4303 is normally off, the gate 4304 is closed and the zero value input to the selection circuit 4301 from the terminal 4307 is selected. On the other hand, matching circuit 430
The output of 2 is on, and the output of gate 4305 and 4
A signal is applied to the write command terminal W of the assignment register 130 through 306 . Therefore, zero is written to the corresponding PCM channel number address in the assignment register 130, and the connection can be disconnected. Next, a case where the mode information is off will be explained. This situation is necessary when performing the above-mentioned refresh, and the inactive overload
Necessary for disconnecting channels, etc. In this case, the information stored in the new connection register 430
All you have to do is disconnect the PCM channel number and DSI channel number.The difference from when the mode information is on is that the matching circuit 4303 is on and the corresponding
When notifying that the time slot of a PCM channel has arrived, instead of writing the DSI channel number stored in the new connection register 430 to the assignment register 130, it is sufficient to write zero. This is because the gate 4304 is always off due to the mode information, so the selection circuit 4301
This can be achieved because the value of zero added from 302 is selected. FIG. 7 is a diagram showing details of the time generator of FIG. 4. This generator includes stepper 4601, matching circuit 4
602, 4603, flip-flop 4604,
Gates 4605, 4606, first PCM frame signal terminal 4607, second PCM frame signal terminal 46
08, reset signal terminal 510, numerical value 1 input terminal 4611, numerical value 96 input terminal 4612, PCM channel number input terminal 490 and window output terminal 46
It consists of 13. At the beginning of the first PCM frame, a reset signal is input to the terminal 510, and the stepper 4601 is incremented by one. Also, the number input from terminal 4607 is
The 1PCM frame signal is on during the first PCM frame. Since the PCM channel number input from the terminal 490 is incremented every channel time slot, the matching circuit 4602 matches the PCM channel number signal input from the terminal 490 and the output of the stepper 4601. Then gate 46
05, the gate signal of gate 4605 is turned on, and an input is applied to the set terminal of flip-flop 4604. Therefore, the terminal 461
3 transmits the ON signal indicated by the flip-flop 4604 from the PCM channel number of the value indicated by the advancer 4601 of the first PCM frame. 2nd PCM
In the frame, the first input from terminal 4608
2PCM frame signal is on during 1PCM frame. At this time, the PCM channel number signal input from the terminal 490 again and the stepper 460
When a match with the value indicated by 1 is detected by match circuit 4602, a match signal passes through gate 4606 and is applied to the reset terminal of flip-flop 4604. Therefore, the terminal 4613
The value indicated by the stepper 4601 of the 2PCM frame
The off signal indicated by flip-flop 4604 is transmitted on the PCM channel number. That is, the signal from the terminal 4613 is transmitted to the stepper 4 of the first frame.
The output of the flip-flop 4604 that is turned on is transmitted from the PCM channel number indicated by 601 to the PCM channel number one value smaller than the value indicated by the stepper 4601 of the second frame. Furthermore, since the stepper 4601 increments by 1 by the reset signal from the terminal 510 at the beginning of each assignment frame, the assignment
The signal outputted from the terminal 4613 for each frame generates a signal that is delayed by one time slot and remains on for one PCM frame. Progressor 4601
advances to 96, the matching circuit 4603 outputs terminal 4.
It is detected that the numerical value 96 input from step 612 matches the value of step 4601, and a signal is applied to the load terminal of step 4601. In this state, when the next assignment frame starts and a reset signal is applied from terminal 510, stepper 4601 is loaded with the value 1 given from terminal 4611. Therefore, the flip-flop 4604 is set from PCM channel number 1 of the first PCM frame, and an on signal is transmitted to the terminal 4613, thereby functioning as a desired time window generator. FIG. 9 is a diagram showing the register timing generation circuit 470 of FIG. 4. This circuit includes a zero detection circuit 4701, gates 4702, 4703, assignment register output signal input terminal 4704, voice detection circuit output signal input terminal 4705, time window generation circuit output signal input terminal 4706, new connection
Timing signal output terminal 4707 for PCM channel register and available DSI channel register.
It has a register timing signal output terminal 4708. Gate 4702 turns on when the time window generator output signal from terminal 4706 is on, the audio detection circuit output signal from terminal 4705 is on, and the assignment register output signal input from terminal 4704 is zero. Detection circuit 4701
Only when it is determined to be zero, an on signal is transmitted to the terminal 4704. This is when the time window is on, indicating that the PCM channel has audio but is not connected to the DSI channel, and the desired new connection request PCM channel.
It serves as a timing signal for registers. Furthermore, the gate 4702 is turned on when the terminal 47
When the time window generator output signal from 06 is on, the audio detection circuit output signal from terminal 4705 is off, and the assignment signal input from terminal 4704 is
Only when the register output signal is determined to be non-zero by the zero detection circuit 4701, the terminal 470
Send the on signal to 8. This is when the time window is on, and there is no audio on the PCM channel and the DSI
The channel indicates that it is connected and is the timing signal for the desired available DSI channel register. FIG. 9 is a diagram illustrating the available DSI channel register 420 of FIG. This register 42
0 is available normal DSI channel register 4201, available OL1DSI channel register 4202, available OL2DSI channel register 4203, busy flip-flop 4
204-4206, gates 4207-4209,
Register timing circuit signal input terminal 421
0, assignment register signal input terminal 421
1, available DSI channel register output terminals 4212-4214, and reset signal input terminal 510. At the beginning of an assignment frame, a register 4201 for normal DSI channel, which can be used by a reset signal input from terminal 510,
Register 420 for available OL1DSI channels
2. Register 42 for available OL2DSI channels
03 and busy flip-flop 4204
-4206 are reset. By the way, as mentioned above, the seventh bit of the DSI channel number belonging to the OL1 channel is 1, and the sixth bit is 0. Furthermore, both the 7th bit and the 6th bit of the DSI channel number belonging to the OL2 channel are 1. Therefore, terminal 4
When the register timing circuit output signal indicating the arrival of an available DSI channel is applied to terminal 4210, the sixth and fifth assignment register outputs (indicating the DSI channel number) applied to terminal 4211 The combination of 7 bits determines whether the incoming DSI channel number belongs to the normal channel or the OL1 channel OL2
Each gate 42 corresponds to the channel it belongs to.
07,4208,4209 opens. Now terminal 4
Assuming that a normal DSI channel number is added to 211 and a register timing circuit signal is applied to terminal 4210, gate 42
07 opens, thereby writing the value of the DSI channel number applied to the terminal 4211 into the available normal DSI channel register 4201, and turning on the busy flip-flop 4204. As a result, the normal signal is returned to terminal 4211 again.
Even if a DSI channel number is added and a signal is applied to register timing circuit signal terminal 4210, busy flip-flop 4204 is turned on, gate 4207 is not opened, and the contents of register 4201 for available normal DSI channels are It does not change. More than that available OL1DSI
Channel register 4202 and available
The same applies to the OL2DSI channel register 4203, and the available DSI channel register 420 can be realized. Thus, according to the present invention, a simple circuit that only requires a time window generator, a new connection request PCM channel register, and an available DSI channel register is provided around the central processing circuit.
A DSI assignment processor can be configured, and by using a time window generator, a fair DSI assignment processor can be configured that does not request DSI assignment services for PCM channel numbers.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a basic DSI device, Figure 2 is a specific example of the assignment register 130 in Figure 1, Figures 3a and b are diagrams showing the connection relationship between the PCM channel and DSI channel, 4 is a diagram showing an embodiment of the present invention, FIG. 5 is a diagram showing the state of use of the internal memory in the central processing circuit 400 of FIG. 4, and FIG.
7 is a diagram illustrating an example of the assignment register changing circuit 450 shown in FIG.
Figure 8 shows an example of register 0 in Figure 4.
A diagram showing an example of a timing circuit 470 and a ninth
The figure is a diagram illustrating an example of the available DSI channel register 420 of FIG. In FIG. 4, 130...Assignment register, 110...Audio detector, 400...Central processing circuit, 410...New connection request PCM channel register, 420...Available DSI channel register, 430...New connection register, 440 ...Data acquisition gate, 450...Assignment register change circuit, 460...Time window generator, 470...
This is a register timing circuit.

Claims (1)

[Claims] 1. A voice detector detects whether or not there is voice in each pulse code modulation channel from the multiplexed input pulse code modulation signal, and connects the input pulse code modulation channel and the output digital voice insertion channel. Determine a new assignment between the pulse code modulation channel and the digital audio insertion channel in the digital audio insertion device that connects the input pulse code modulation channel where audio exists to the output digital audio insertion channel using the allocation register indicating the correspondence between the input pulse code modulation channel and the digital audio insertion channel. A digital audio insertion processor comprising: a central processing circuit; a new connection request pulse code modulation channel register connected to the data bus of the central processing circuit; and an available digital audio insertion processor connected to the data bus of the central processing circuit. a new connection register connected to a data bus of the central processing circuit; and means for capturing the output of the voice detector and the output of the allocation register into the data bus of the central processing circuit;
means for updating the allocation register with information in the new connection register; and means for updating the new connection request pulse code modulation channel register and the available audio in each period for determining a combination of a set of pulse code modulation channels and a channel for audio insertion. Permit writing to the insertion channel register for one period of the multiplexed pulse code modulation channel, and set the time at which the writing permission starts for each period in which a combination of a set of pulse code modulation channels and audio insertion channel is determined. a time window generator that delays the permission start time by one pulse code modulation channel and advances the permission start time by the number of multiplexed pulse code modulation channels when delayed by the number of multiplexed pulse code modulation channels; and an output of the assignment register; means for capturing a pulse code modulation channel number requesting new connection into the connection request pulse code modulation channel register from the output of the audio detection circuit and the output of the time window generator; A processor for digital audio insertion, comprising means for loading an available audio insertion channel number into the available audio insertion channel register based on the output of the detection circuit and the output of the time window generator.