JPS6153738B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is applicable to digital speech (Digital Speech).
Interpolation (DSI) device processor. In a typical telephone conversation, one person is only listening while the other person is speaking, and both parties are often silent. Therefore, on a time-average basis, the transmission path is only used for about 1/2 or less of the time. Taking advantage of this fact, DSI equipment increases the efficiency of transmission path usage by transmitting only the portion where voice is present, approximately doubling the capacity of existing PCM lines. The theory of DSI equipment is explained in the publication “Digital Speech Interpolation” COMSAT
TECHNICAL REVIEW, Vol.6, No.1, Spring
1976”. The configuration of such a DSI device is shown in Figure 1. Reference number 1 is the transmitting side DSI device, reference number 2 is the receiving side DSI device.
Showing DSI equipment. The transmitting side DSI device 1 consists of a voice detector 110, a transmitting voice memory 120, a transmitting assignment register 130, and an assignment processor 140.
Compress to DSI channel 3 and POM channel 2
New connection information with the DSI channel 3 is transmitted to the receiving DSI device via the allocation information signal line 4.
The receiving DSI device 2 includes an assignment information receiver 150, a receiving assignment register 160, and a receiving audio memory 170, and transmits PCM data from the DSI channel 3 and the assignment information signal line 4 to the PCM channel 5.
Replay the state of channel 2. In transmitting side DSI device 1, input PCM channel 2
Of the signals, only the channel with audio is written to the transmitting side audio memory 120 under the control of the transmitting side assignment register 130 and read out as the signal of DSI channel 3. The transmission side assignment register 130 indicates the correspondence between PCM channel numbers and DSI channel numbers. For convenience of explanation, suppose that the transmission side assignment register 130 has a correspondence relationship as shown in FIG.
The relationship between is shown in FIG. That is, assume that DSI channel number 2 is assigned to PCM channel number 1, DSI channel number 1 is assigned to PCM channel number 3, and DSI channel number 3 is assigned to PCM channel number 4. At this time, for example,
When PCM channel number 7 has audio (hereinafter referred to as active), the audio detector 110
detects that PCM channel number 7 is active. Assignment processor 140
searches for the DSI channel number that is not active (in the case of Figure 2, it is DSI channel number 4),
A new connection is determined, sent as assignment information, and the sending assignment register 130 is rewritten.
The allocation information is the part that indicates connection or disconnection, PCM
It consists of a channel number section and a DSI channel number section. In the receiving DSI device 2, the contents of the receiving assignment register 160 are updated according to the assignment information received by the assignment information receiver 150 and track the contents of the transmitting assignment register 130. As a result, the output PCM signal 5 is obtained from the received DSI signal 3 by performing the reverse operation of the operation performed on the transmitting side. A PCM channel connected to a DSI channel remains connected even if it is no longer active unless assignment processor 140 assigns the DSI channel to another PCM channel. Since the number of DSI channels is fixed, sometimes more PCM channels than the number of DSI channels become active, making it impossible to transmit the first part of the audio. This situation can be greatly improved by temporarily reducing the accuracy of the PCM word (one sample value of PCM) from 8 bits to 7 or 6 bits and virtually increasing the number of DSI channels. For example, if the number of PCM channels is 8 as shown in Figure 3a and the number of DSI channels is 4 as shown in Figure 3b, the PCM transmitted on the DSI channel
If all words are 6 bits, there will be a total of 8 bits left over, so one new DSI channel can be added. DSI equipment is usually equipment that targets PCM60 channels or more. for example,
96 channels consisting of 4 lines of PCM24 to DSI48
In a system that compresses data into channels, six new channels can be generated by transmitting a PCM word in 7 bits, and six new channels can be added by transmitting a PCM word in 6 bits. These newly added channels are respectively called overload 1 channel (hereinafter abbreviated as OL ₁ CH) and overload 2 channel (hereinafter abbreviated as OL ₂ CH). In contrast, the original DSI channel will be referred to as a normal channel (hereinafter abbreviated as NCH). If an overload channel is used, assignment processor 140 may
If there is a channel with no audio (hereinafter referred to as inactive) and there is no new connection request,
In order to improve the accuracy of PCM words, it is necessary to reallocate the PCM channel connected to the overload channel to the inactive NCH. Even after taking these measures, the channel cannot be assigned to a DSI channel even though it is active.
A PCM channel may also be present. The ratio of active PCM channels that cannot be allocated to active PCM channels in a unit time is called the lockout rate.
It is an additional function of the assignment processor 140 to communicate this externally if the DSI device is indicating. Allocation information only needs to be sent once every few frames.
One of the most important application fields of DSI equipment
One method is to use six frames as one assignment frame to suit TDMA satellite communications. Assignment processor 14 explained above
To summarize the functions of 0: 1 Acceptance of new allocation request PCM channel. 2 Detection of inactive DSI channels. 3. Management of overload channels. 4. Decision on new allocation. 5. Organizing statistical data such as lockout rate. 6 The above functions must be performed within 6 frames and in synchronization with peripheral circuits such as PCM. An assignment processor with the above functions can be implemented using a mini computer or microprocessor. However, with these conventional configurations, it takes time to collect data on the number of active PCM channels and the number of locked out PCM channels required to calculate the lockout rate, and the assignment processor is not used until the calculation of the lockout rate. It is difficult to perform, and even if it is possible to calculate the lockout rate, it has the disadvantage that less time is available for managing other DSI equipment and preparing for the next assignment frame. . The object of the present invention is to provide a digital audio insertion system that can significantly reduce the time required to calculate the lockout rate by connecting small-scale hardware to the data bus of a central processing circuit such as a mini-computer or microprocessor. The goal is to provide a processor. The processor of the present invention includes a central processing circuit, first and second counters connected to a data bus of the central processing circuit and capable of loading contents into the central processing circuit, When the signal is connected to the position of the data bus corresponding to the voice detection result when read out onto the bus and is commanded by the program, and there is a signal indicating the presence of voice at the position of the data bus corresponding to the voice detection result, the means for incrementing a counter of No. 1; a signal connected to a data bus of the central processing circuit, commanded by the program and indicating the presence of a voice at a position on the data bus corresponding to the voice detection result; means for incrementing the second counter when there is a signal indicating that there is no output digital audio insertion channel number (not connected) at a position on the data bus corresponding to the audio insertion channel number; and a data bus of the central processing circuit. and an abnormal exclusion register connected to the central processing circuit, and the two counters are externally provided with a function of collecting data necessary for calculating the exclusion rate from data stored in the internal memory of the central processing circuit. The present invention is characterized in that the arrangement of data for calculating the lockout rate and the calculation of the lockout rate are performed by a central processing circuit, thereby reducing the load on the central processing circuit. Next, the present invention will be explained in detail with reference to the drawings. FIG. 4 shows a conventional example of an assignment processor for digital audio insertion that compresses 96 PCM channels, that is, four 24-multiplexed PCM signals into 48 DSI channels. ment register 130, audio detector 110, assignment register update circuit 320, data input bus 210, data output bus 220, clock terminal 230, assignment frame signal terminal 240, input gate 2
50, control signal bus 260, PCM channel number signal input terminal 400, PCM data signal input terminal 410, assignment register output terminal 42
Starting from 0. Among the above, central processing circuit 2
00 is the publication “Am2900Bipolar Microprocessr” published by Advanced Micro Devices in 1976.
This circuit is as described in "Family", page 91, and a clock signal four times (6.176 MHz) as the clock (1.544 MHz) of the 24-channel multiplexed input PCM signal is input from the terminal 230.
The voice detection circuit 110 is also described in detail in, for example, US Pat. Assignment register 13 consisting of random access memory
0 is a memory that outputs the DSI channel number to which that PCM channel is connected when a PCM channel number is given to its address input, and if a certain PCM channel is not connected to a DSI channel, it outputs that PCM channel number. Even when applied to the address of assignment register 130, the output is zero. As will be described later, the assignment register change circuit 320 is a circuit that writes new connection information to the assignment register 130 according to the contents of the new connection register 300.
The new connection register 300 is a register that stores connection information of a newly determined set of PCM channels and DSI channels.
It stores data consisting of a channel number and M bits indicating whether to connect or disconnect. An outline of the operation of this sciment processor will be described below. When a signal indicating the start of an assignment frame is transmitted to the central processing circuit 200 from the terminal 240, the central processing circuit 200 transmits the signal to the control signal bus 26.
0, the output of the voice detection circuit 110 and the output of the assignment register 130 are loaded as one data word for each input PCM channel via the input gate 250 and stored in the internal register of the central processing circuit 200. PCM channel number signal input from terminal 400, input from terminal 410
The PCM data signal is synchronized with the clock input from the terminal 230, and the central processing circuit 200 can operate in 8 steps per PCM channel (125 μm per PCM channel).
The clock operates at 6.176 MHz for sec/96), and storing the output of the audio detection circuit 110 and the output of the assignment register 130 in internal memory is an 8-step program.
This is done in synchronization with the change in PCM channels, and by repeating this 96 times, the above information for all PCM channels can be stored in the internal memory of the central processing circuit 200. One PCM frame period is required for this processing. If the output of the audio detector 110 and the output of the assignment register 130 for all PCM channels are obtained in the internal memory of the central processing circuit 200,
The function of the assignment processor described above can be realized. First, a new assignment request channel is detected when the part of the data stored in the internal memory corresponding to the output of the audio detector 110 indicates that there is audio, and the part corresponding to the output of the assignment register 130 is not connected. This is done by detecting that The detected new allocation request PCM channel is registered in a new allocation request channel queue stored in a part of the internal memory of the central processing circuit 200. This new assignment request channel queue holds any new assignment request PCM channels that could not be connected up to the previous assignment frame, and stores new assignment request channels newly generated in the current assignment frame. Prioritizes connection requests and removes previous assignments.
Up until the frame, new allocation requests were being made.
If the output of the voice detector is no voice in the current assignment frame for a PCM channel, such PCM channel is removed from the new assignment request channel queue. Approximately 2 PCM frame periods are required to complete the above program. To detect available DSI channels, the
For data consisting of the output of the audio detection circuit 110 and the output of the assignment register 130 for PCM96 channels, the output of the audio detection circuit 110 indicates no audio, and the assignment register 13
It is only necessary to detect data indicating the DSI channel number to which the output of 0 is connected, and this DSI channel number can be used for new allocation by disconnecting the PCM channel that has been connected so far. . This processing also requires time equivalent to one PCM frame. If there is a new allocation request PCM channel in the new allocation request PCM channel queue and an available DSI channel is detected, the central processing circuit 200 sets the combination of this PCM channel and DSI channel as new allocation. Overload
When using a DSI channel, when the above new allocation cannot be performed, overload DSI channels with no audio can be used to reduce the use of overload DSI channels as much as possible and improve the accuracy of PCM data.
If there is a channel, the disconnection between this overload DSI channel and the connected PCM channel is set as a new assignment. Furthermore, if the above two new allocations cannot be made and the available DSI channel is a normal DSI channel, check the overload management matrix to see if the overload DSI channel is being used, so that the overload management matrix is checked. As you can see, this overload
A PCM channel connected to a DSI channel is reallocated to the available DSI channel. If none of the above new allocations can be made, a pair of connected DSI channels and PCM channels are newly allocated in order to notify the receiving side of the current allocation status. This is called a refresh, and occurs when the transmitting side assignment register 130 and the receiving side assignment register 160 are
(See Figure 1) If the new allocation involves an overload DSI channel, the central processing circuit 200
Add the overload DSI channel number to the overload management matrix formed in the internal memory of Use it to make decisions. The above new allocation process requires approximately 1 PCM frame time. After this, a set of new allocation PCM
The central processing circuit 200 sends this data to the new connection register 300 via the data output bus 220 via the control bus 260 with the addition of an M bit to the channels and DSI channels indicating whether these channels are to be connected or disconnected. transfer. As a result, the processing performed by the central processing circuit 200 in one assignment frame is as follows.

[Table] The data in the new connection register 300 is the sending side DSI
After the assignment information has been transmitted from the device to the receiving DSI device, for example, in the fourth PCM frame, the transmitting DSI device and the receiving DSI device change the assignment register via the assignment register change circuit in synchronization. 130 and is available at the end of the fifth PCM frame when central processing circuit 200 writes new data to new connection register 300. A specific example of the assignment register changing circuit indicated by reference numeral 320 in FIG. 4 is shown in FIG. The assignment register change circuit shown in FIG. 5 includes a new connection register 300, an assignment register 130, a selection circuit 3201, and a match circuit 3202 and
3. Gate circuits 3204, 3205 and 320
6, zero input terminal 3207, PCM channel number input terminal 400, and timing signal input terminal 3210. Since the timing signal input from terminal 3210 is off except for the 1 PCM frame period that allows rewriting of assignment register 130, assignment register 1
No other PCM frame is output to the write permission terminal W of No. 30. The PCM frame in which the timing signal is turned on is determined by the transmission method of allocation information, etc., and for convenience, it is assumed to be the fourth PCM frame here. Therefore, in the assignment frame,
Time assignment registers 130 other than 4 PCM frames will be accessed by the PCM channel number signal input from terminal 400.
New assignment information is transferred to the new connection register 300 in the fifth PCM frame of the previous assignment frame. As mentioned above, the new allocation information includes a set of PCM channel numbers and DSI channel numbers, and whether to connect (on) or disconnect (off) between these PCM channels and DSI channels. It consists of mode information indicating that. First, a case where the mode information is on in the fourth PCM frame will be described. The PCM channel number signal input from the terminal 400 and the PCM channel number part in the new connection register 300 are compared by the matching circuit 3203, and a new connection request is made.
When a PCM channel time slot arrives, a match signal is output. In the gate 3204, the mode information is on and the output of the matching circuit 3203 is on, so the selection signal input terminal of the selection circuit 3201 is turned on. The selection circuit 3201 selects the DSI channel section of the new connection register 300 when the selection signal is on, and selects the DSI channel section of the new connection register 300 when the selection signal is off.
In order to select the zero input from 207, the data input terminal DI of the assignment register 130
The newly connected DSI channel number is conveyed to .
Also, at this time, since the output of the matching circuit 3203 passes through gates 3205 and 3206, the newly connected DSI channel number is written in the address position of the new assignment request PCM channel number input from the terminal 400 in the assignment register 130. It turns out. Furthermore, the output of the assignment register 130, that is, the DSI channel number,
The matching circuit 3202 compares the DSI channel number section of the new connection register 300, and if a matching DSI channel is detected, the current
The PCM channel number and DSI channel number were connected until the previous assignment frame, and must be disconnected in order to make a new connection in the current assignment frame. At this time, since the output of the matching circuit 3203 is normally off, the gate 3204 is closed and the selection circuit 3201
The zero value input from the terminal 3207 is selected. On the other hand, the output of match circuit 3202 is on and provides a signal to write command terminal W of assignment register 130 through gates 3205 and 3206. Therefore, zero is written to the corresponding PCM channel number address in the assignment register 130, and the disconnection can be executed.
Next, a case where the mode information is off will be explained. Such a situation is necessary when performing the above-mentioned refresh, and is necessary when disconnecting the overload channel in a DSI device using the above-mentioned overload channel.
In this case, it is only necessary to disconnect the PCM channel number and DSI channel number stored in the new connection register 300.The difference from the case where the mode information is on is that the matching circuit 3203 is on and the corresponding
When notifying that the time slot of the PCM channel has arrived, instead of writing the DSI channel number stored in the new connection register 300 to the assignment register 130, it is sufficient to write zero. Since the gate 3204 is always off according to the mode information, the selection circuit 3201
can be realized because the value of zero added from the terminal 3207 is selected. As described above, the processor for digital audio insertion has been explained. All allocation processing is performed within one assignment frame (750 μsec) by the central processing circuit 200, but it is also necessary to calculate the abnormal exclusion rate and the next assignment. - Preparations for frames must be made within one PCM frame period. As mentioned above, calculation of the lockout rate is an important function of the DSI processor. The lockout rate is the number of active PCM channels per unit time,
It is defined by the ratio of the number of active PCM channels (locked-out channels) that are not connected to a DSI channel, and the number of these channels is defined by the ratio of the output of the audio detection circuit 110 to the number of active PCM channels (locked-out channels) for each assignment frame. Number of PCM channels that showed yes and also 1
The number of PCM channels for which the output of the assignment register 130 indicates not connected to a DSI channel even though the output of the audio detection circuit 110 indicates that there is audio for 96 PCM channels for each assignment frame. It can be calculated by counting. However, since the transmission audio memory 120 in FIG. 1 includes a delay function for a PCM channel that is in the process of new connection or for which a new connection has been newly determined, the data of the corresponding PCM channel is sent to the receiving end without being shut out. Therefore, these PCM channels are not included in the exclusion channels. That is, the count of shut-out channels cannot be determined simply by the output of the audio detector or the assignment register. Furthermore, when observing the lockout rate over a short period of time such as one assignment frame (750 μsec), the fluctuation is very large, and the DSI device exhibits an abnormally high lockout rate. Therefore, if it is desired to issue an alarm signal indicating abnormal lockout to the outside, it is necessary to average the lockout rate for about one minute. The counter length required for this purpose is such that even in a system that compresses PCM96 channels to DSI48 channels, it is necessary to use a counter that counts active channels.
Considering the possibility that it may be necessary to count up to 96 channels x 60 sec/750 μsec = 7.68 x 10 ⁶ , a length of 24 bits is required. Furthermore, the counter that counts blocked channels must be 23 bits because in the worst case, half of all active channels will be blocked. In conventional DSI devices, the calculation of the lockout rate is performed using dedicated hardware or using a central processing circuit. When dedicated hardware is used, it has the disadvantage of requiring a large-scale circuit configuration, as it requires correction of the above-mentioned cut-off channel, a counter that requires a long number of bits, a one-minute measuring device, a divider, and the like. Furthermore, even in a configuration that uses a central processing circuit, other processors that execute the TDMA communication protocol can be used for the DSI management function in a time-sharing manner, independent of the processor with the configuration shown in Figure 4. This often includes the calculation of the lockout rate, and in such cases, it is useful for applications other than TDMA communication for international satellite links (for example, communication to a specific area using domestic satellites or communication using terrestrial communication lines). is not available. Next, an embodiment of the present invention shown in FIG. 6 will be described. The processor in FIG. 6 is a central processing circuit 20.
0, active channel number counter 610, shut-out channel number counter 620, gate 63
0 and 640, a zero detection circuit 650, an input data bus 210, an output data bus 220, a control signal line 260, and an abnormality lockout register 680. As explained above, the central processing circuit 200 performs the following for each of the input 96 PCM channel numbers.
The output of the audio detector 110 and the output of the assignment register 130 corresponding to the PCM channel are stored as one word, and the composition of one word is MSB.
(most significant bit) corresponds to the voice detector output,
All bits other than MSB are output from the assignment register. It is also assumed that one input of gates 630 and 640 is connected to a line indicating the MSB of the data bus, and zero detection circuit 650 is connected to a portion of the bus indicating other than the MSB of the data bus. Furthermore, since the present invention assumes a case where PCM96 channels are compressed into DSI48 channels, the active channel number counter 610 and the shut-out channel number counter 620 are set to 8 bits. Furthermore, the internal memory of the central processing circuit 200 is provided with a 24-bit area for accumulating the number of active channels and a 23-bit area for accumulating the number of shut-out channels. New allocation results can be stored. The operation of the present invention will be explained in detail below. At the end of each assignment frame, active channels counter 610 and blocked channels counter 620 are reset via control signal bus 260. For this reason, the central processing circuit 200
Since counters 610 and 620 are not used for new allocation, both counters 61 and 620 are used when determining new allocation.
The contents of both 0 and 620 remain zero. When the central processing circuit 200 determines a new assignment, the central processing circuit 200 uses the input stored in the internal memory of the central processing circuit 200.
A new allocation process is in progress for the internal memory area consisting of the output of the audio detector 110 and the output of the assignment register 130 for the 96 PCM channel, which is also stored in the internal memory.
PCM channel and newly determined new allocation
Make changes according to the PCM channel information.
For example, even if there is audio in the PCM16 channel stored in the internal memory but it is not connected, if it is to be connected to the DSI5 channel by new allocation, then the internal memory
PCM16 channel section has audio and connects DSI
Channel number 5 is entered. After performing such changes, the central processing circuit 2
00 is the output of the audio detection circuit 110 for the input 96 PCM channels and the assignment register 1.
The data in the internal memory area consisting of 30 outputs is
Each PCM channel is placed on the output data bus 220 and sent to the gate 630 via the control signal bus 260.
open. Therefore, if the MSB of the value on the output data bus 220 is on, it outputs on, and if it is off, it outputs off. The state of this MSB indicates whether or not the PCM channel corresponding to the data carried on the output data bus 220 has audio.
30 is on, the active channel number counter 610 is incremented. At the same time, gate 640
is also opened via the control signal bus 260 so that the MSB of the value on the data bus is on (indicating audio) and the zero detector 650 is on the MSB of the value on the data bus.
When it is detected that the other than zero is zero (indicating that it is not connected to the DSI channel), a match signal is transmitted to the shut-out channel number counter 620 to increment it by one step. When the central processing circuit 200 reads out all areas corresponding to 96 PCM channels in the internal memory onto the output data bus 260, the contents of the active channel number counter 610 indicate the total number of active PCM channels in the current assignment frame. Further, the blocked channel number counter 620 indicates the total number of blocked PCM channels, including the correction of PCM channels that are about to be connected. The central processing circuit 200 loads the active channel number indicated in the active channel number counter 610 via the control signal bus 260, and loads the active channel number up to the previous assignment frame stored in the aforementioned internal memory. The contents of the channel number counter 610 are accumulated to the channel number cumulative value. Similarly, the central processing circuit 200 instructs the number of blocked channels counter 620 via the control signal bus 260 to load the number of blocked channels indicated in the number of blocked channels counter 620 before being stored in the aforementioned internal memory. Add to the cumulative number of shut-out channels up to the previous assignment frame. Separately, the central processing circuit has a memory area in its internal memory that adds 1 for each assignment frame, and the contents of this area are 8×10 ⁴ (=60sec/
750 μsec), that is, when one minute has passed, the ratio of the accumulated value of the number of active channels and the accumulated value of the number of shut-out channels is calculated to calculate the lock-out rate, and at the same time the internal Give 0 to the memory area for the next lockout rate calculation. If the lockout rate is abnormally high (for example,
0.5% or more), data indicating an abnormality is transferred to the abnormality exclusion register 680 under the control of the central processing circuit 200, and data indicating normality is transferred to the abnormality exclusion register 680 via the data bus. As described above, in the DSI assignment processor of the present invention, calculation of the lockout rate required for each assignment frame can be performed by simply providing a simple external counter, reading data from the internal memory, and accumulating the number of active channels. 1 addition for and 1 addition for accumulating the number of shut-out channels.
Since this can be done with one addition for the minute counter, the load on the central processing circuit can be reduced. In addition, since data collection for the exclusion rate uses only the internal memory of the central processing circuit, there is no need to consider synchronization with the audio detector or assignment register external to the DSI assignment processor, and the calculation of the exclusion rate begins. Since there are no restrictions on time points, there is also the advantage that calculations can be made at appropriate times within one assignment frame depending on the processing status of the central processing circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the DSI device, FIG. 2 is a diagram specifically showing the assignment register 130 of FIG. 1, FIG. 3 is a diagram showing the connection relationship between the PCM channel and the DSI channel, and FIG. 4 shows a conventional assignment processor 140, FIG. 5 shows an assignment register changing circuit 450 of FIG. 4, and FIG. 6 shows an embodiment of the present invention. In FIG. 6, 200...central processing circuit, 61
0...Active channel number counter, 620...
Lockout channel number counter, 630 and 6
40...gate, 650...zero detection circuit, 680...
Abnormal lockout register.

Claims (1)

[Claims] 1. New combination of input pulse code modulation channel and digital audio insertion channel in a digital audio insertion device that connects only the input pulse code modulation channel with audio out of the multiplexed input pulse code modulation signal to the output digital audio insertion channel. When determining assignment, a data word summarizing the result of detecting whether or not there is audio in an input pulse code modulation channel and the channel number for output digital audio insertion to which the input pulse code modulation channel is connected is assigned to each input pulse code. In a digital audio insertion processor consisting of a central processing circuit that captures data into an internal memory in correspondence with a modulation channel and determines allocation based on the data in the internal memory, a first a second counter connected to a position on the data bus that corresponds to the voice detection result when the data word stored in the internal memory is read onto the data bus; means for incrementing the first counter when there is a signal indicating the presence of voice at a position on the data bus; There is a signal indicating the presence of audio at a position on the data bus corresponding to the output digital audio insertion channel number, and there is a signal indicating that there is no output digital audio insertion channel number (not connected) at the data bus position corresponding to the output digital audio insertion channel number. Sometimes the second
and means for incrementing a counter of an input pulse modulated channel which cannot be connected to an output digital audio insertion channel despite the presence of audio from data stored in an internal memory of the central processing circuit. The center is used to generate the data necessary to calculate the lockout rate, which indicates the percentage of the total number of input pulse modulation channels in which audio is present, and the data arrangement for the lockout rate calculation and the calculation of the lockout rate are carried out by the central 1. A digital audio insertion processor, characterized in that the processing is carried out by a processing circuit, thereby reducing the load on the central processing circuit.