JPS6147430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device that outputs a synchronization signal suitable for an externally synchronized display device even when the number of XY lines or frame frequency of the display device is different.

For example, the EL display device has 320 x 240 lines or
Some models have a number of XY lines such as 521 x 128, and others have different frame frequencies. For this reason, when inputting a synchronization signal, a data signal, etc. to a display device, since the cycles of the synchronization signals and the like differ, image processing circuits suitable for each are required.

The present invention provides an X-
Initial setting memory (P-ROM) is available even when the number of Y lines or frame frequency is different.
By changing the data of It can be shortened and is very useful in terms of cost.

An embodiment of the present invention will be described below with reference to the drawings. The drawing is a system block diagram of one embodiment.

1 is an EL display device, 2 is an oscillator and frequency dividing circuit,
3 is a synchronization signal generation circuit and a display read address generation circuit, 4 is a synchronization signal initialization circuit consisting of a P-ROM, 5 is an input/output control circuit, 6 is an address multiplexer, 7 is a data multiplexer, 8 is a display memory circuit, 9 is a parallel-serial conversion circuit, 10 is a pattern character generator, and 11 is an input/output buffer circuit.
2 to 11 constitute an image processing circuit 12, and here the image processing circuit 12 is further connected to a central processing circuit 13.
It is connected to a microcomputer 15 including a decoder 14 and other external devices 16.

The EL display device 1 is of an external synchronization type and requires four types of external inputs: serial data D _IN , transfer clock CK _D , horizontal synchronization signal, and vertical synchronization signal. The synchronization signal generation circuit section of circuit 3 can freely set the synchronization signal synchronization etc. by a program, and is equivalent to the synchronization signal generation circuit which can freely set the synchronization signal synchronization etc. by a program such as a CRT controller or CTC. things are used. The display read address of the display read address output circuit section of the circuit 3 is of a linear address type. In the case of the XY address method, if the number of XY lines differs depending on the display device, it is necessary to redesign the circuit that outputs the XY address to match the number of XY lines.

It is preferable that the display readout address output circuit unit be able to initialize the readout address of the display memory circuit 8 or set it by a program from the microcomputer 15. This is some kind of X-
When designing an image processing circuit that can be used for display devices with different numbers of Y lines, in order to match the memory capacity of the memory circuit 8 to the device with the largest number of X-Y lines, Only part of it will be used. Therefore, if the circuit is designed as described above, scrolling, page changes, etc. can be performed by changing the reading start address of the display memory circuit 8 using program data etc. from the microcomputer 15, and the memory can be used without wasting memory. I can do it.

The synchronization signal initialization circuit 4 is a circuit that initializes the synchronization signal generation circuit portion of the circuit 3 via the data multiplexer 7 after power is turned on or upon reset from the microcomputer 15. The contents of the initialization include setting of horizontal and vertical synchronizing signals suitable for the display device and setting of a start address at which the display read address circuit starts reading the display memory circuit 8.

As a procedure for initialization settings, program data for initialization settings is written in advance into a memory such as P-ROM. Then, using the frequency divided output from the oscillation frequency dividing circuit 2 as the address input of the P-ROM, program data is read out and sequentially programmed into the synchronizing signal generating circuit section of the circuit 3. In other words, with this device, by simply changing the program data of the P-ROM (preparing some types of synchronization initialization circuits 4), a synchronization signal suitable for a display device with a different XY line or a display device with a different frame frequency can be generated. can be easily obtained. Also, P for this blog program
- If you increase the memory capacity of the ROM and write initialization settings programs for several display devices for the corresponding number of pages, the display can be performed simply by switching pages using the switch, terminal, or plug-in control of the initialization circuit 4. Since an image processing device suitable for the device can be obtained, versatility is further increased and convenience is achieved.

As described above, the image processing device of the present invention can be used with various externally synchronized EL display devices (X-
It is designed for models with different numbers of Y lines, models with different frame frequencies, etc.), and when using any display device, there is no need to change the hardware, just a change in the software. A feature is that an output signal suitable for a display device can be obtained. Further, when designing a product, it is possible to check only the image processing circuit, and the development efficiency can be improved.

In this case, the above-mentioned software refers not to a microcomputer program but to program data of a P-ROM for initializing settings in the image processing circuit. Therefore, another feature of this processing device is that
Although a program is required, the initialization settings are programmed inside the image processing circuit, so even if the microcontroller is not connected, the correct synchronization signal and clock will be output to the display device, making it easy to interface. has advantages. Further, in the present invention, the program data of the synchronization signal initialization circuit made of ROM in the image processing circuit is read out using the frequency division output of the oscillation frequency division circuit provided in the image processing circuit as an address input, The circuit configuration is also very simple and can be provided at low cost.

Although the present invention has been described using an externally synchronized EL display device as an example, the gist of the present invention will not be impaired even when used in other externally synchronized display devices (CRT, plasma display, etc.). .

[Brief explanation of the drawing]

The drawing is a system block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... EL display device, 2... Oscillation frequency divider circuit, 3... Synchronization signal generation circuit and display read address generation circuit, 4... Synchronization signal initialization circuit, 7... Data multiplexer, 8... Memory circuit for display, 12... Image Processing circuit, 15...microcomputer.

Claims (1)

[Claims] 1. A synchronization signal generation circuit for an externally synchronized display device is a circuit that can be initialized, and a synchronization signal initialization circuit consisting of a ROM in which the initialization program data is written in advance is provided in the image processing circuit,
The program data is read from the synchronization signal initialization circuit using a frequency division output from an oscillation frequency division circuit provided in the image processing circuit as an address input, and the synchronization signal generation circuit is initialized and set using the read data. An image processing device characterized by: