JPS6152585B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an improvement in the pattern of a buried gate portion of a semiconductor control element having a buried gate structure.

Regarding the conventional structure of a gate turn-off thyristor (GTO) having a buried gate P ⁺⁺ layer, its cross-sectional shape is similar to the first structure according to the present invention except that the pattern shape of the low resistance buried P ⁺⁺ layer is different. Since it is the same as the figure, the _P2 base layer is made up of three layers: the _P'2 layer, the P ⁺⁺ layer, and the _P''2 layer, and the P ⁺⁺ layer is shown in Figure 2. As shown in the figure, it is a comb-shaped pattern (shaded area), and the P ⁺⁺ layer 14 of this comb-shaped pattern is embedded in the _P'2 layer, and the surface thereof is covered with the _P''2 layer. P″ ₂ layer surface has _N2
A layer is formed. In order to take out the electrode from part 2 of the P ⁺⁺ layer, dig part 1 of the P″ ₂ layer to reach the P ⁺⁺ layer.
3, and an auxiliary gate electrode G is provided on the surface of this portion 2.
Glue _R. Also, the gate electrode for ignition (on) G _O
A recessed portion 12 for accelerating the ignition state is provided in a part of the N ₂ layer close to the ignition state, and a cathode electrode K is bonded to the surface of the other N ₂ layer. An anode electrode A is provided on the surface of one _P1 layer.

In Fig. 1 of the conventional structure constructed in this way, a GTO with a structure in which the pattern shape of the P ⁺⁺ layer is as shown in Fig. 2 is used.
Regarding the operation of GTO, when a voltage is applied between the anode electrode A and the cathode electrode K with the anode electrode A side being positive, a voltage is applied between the cathode electrode K and the gate electrode _G0 by the power supply 3, resistor 4, and switch 5.
By passing current in a direction that forward biases the P ₂ N ₂ junction, the GTO transitions from a blocking state to a conducting state and allows current to flow. In order to shift from this state to the blocking state, the cathode electrode K is connected to the power supply 6 and switch 7.
A voltage is applied between the _P2N2 junction and the auxiliary gate electrode _GR in a direction that reverse biases the _P2N2 junction, and a current of 20 to 50% of the current (forward current) flowing until then is applied to the low-resistance embedded P ⁺⁺ layer. When the current is swept from the current to the auxiliary gate electrode G _R side, the current flowing between the anode electrode A and the cathode electrode K shifts to O in a short time, and becomes a blocked state.

In order to facilitate the transition to the off-state, the low-resistance buried P ⁺⁺ layer is connected to the cathode as shown in FIG.
Although a comb-like shape with a uniform arrangement is adopted for the _N2 layer, the low-resistance buried P ⁺⁺ layer essentially inhibits the conduction of current between the anode electrode A and the cathode electrode K. This causes problems especially in the conduction region at the initial stage of gate ignition.

To explain this in detail in Figure 2, the gate electrode G ₀
There is no problem if the entire length of one side of the cathode N ₂ layer near the gate electrode G ₀ is ignited at the initial stage of ignition, and the conduction region spreads over the entire area from there. Due to the non-uniformity of _{the 2N2} junction, etc., it is difficult to fire the entire area at the same time. In GTO, the on-sensitivity is poor because the off-function is particularly important, and the above-mentioned problem becomes important. In Fig. 2, if we consider the case where only point B ignites, if there is no low-resistance buried P ⁺⁺ layer, the conduction region will spread from point B to the entire cathode, but
Because of the P ⁺⁺ layer, the spread is limited to the C direction, and the spread is worse in the lateral directions D and E, and in the worst case, the current flows only in a small area surrounded by the P ⁺⁺ layer in the C direction. This will cause an overcurrent condition and result in thermal breakdown. Expansion in the lateral directions D and E can be achieved by narrowing the width of the low-resistance buried P ⁺⁺ layer, but this increases the resistance of the buried P ⁺⁺ layer, causing a problem in the off function.

In order to solve these conventional problems, the present invention improves the pattern shape of the low-resistance buried P ⁺⁺ layer and provides a semiconductor device that effectively spreads the conduction region during gate ignition. This will be explained below using examples.

1 is a longitudinal sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 3a is a longitudinal sectional view of a main part of FIG. 1, and FIG. FIG. 3 is a plan view showing the pattern shape and arrangement of a low-resistance buried P ⁺⁺ layer.

To explain the configuration shown in Figure 1, one side of an N-type silicon (Si) wafer with a specific resistance of 50 Ω-cm and a thickness of 350 μm is mirror-polished, and potassium is applied to the surface concentration of 5 × 10 from both sides by the usual thermal diffusion method. ¹⁷
(atom/cm ³ ) to a depth of 40 μm to form a P ₁ N ₁ P′ ₂ layer. Here, a _P'2 layer is formed on the mirror-polished side, and a _P1 layer is formed on the non-mirror-polished side. Next, boron was diffused to a surface concentration of 1×10 ²⁰ (atom/cm ³ ) to a depth of 10 μm on the mirror-polished surface of the P′ ₂ layer using a selective diffusion method using an oxide film, as shown in Figure 3b. Create a low-resistance embedded P ⁺⁺ layer with a comb-shaped pattern. The embedded P ⁺⁺ layer of this comb-shaped pattern is divided into a plurality of parts on the side to which the firing command is applied, and here it is divided into two parts to make the width narrower. Furthermore, on the surface of this buried P ⁺⁺ layer, _two P″ layers with a resistivity of 15Ω-cm were grown to a thickness of 25 μm using an epitaxial method to form a P ⁺⁺ layer.
P″ is buried under _two layers.Furthermore, using conventional selective diffusion technology, phosphorus is added at a surface concentration of 1×10 ²⁰ (atom/cm ³ ) and at a depth of
Diffuse for 15μm and pass through the _N2 layer. Low resistance embedded P ⁺⁺ layer 14
As shown in Fig. 3b, the width of the wide part 15 is _t1.
250 μm, the width t ₂ of the narrow parts 10 and 11 is 50 μm,
The width _t3 of the wide part 16 of the conductive area without embedded parts is 250μ
m, and the width t ₄ of the narrow portion 9 was 150 μm. The length of the divided portion 8 of this embedded pattern is 2.0 mm, and the divided portion 8 is arranged so that a portion 81 of this portion overlaps the opposing cathode electrode K. Further, a trench portion 12 for accelerating the ignition state is provided in the _N2 layer facing the region 82. Further, as described above, a trenched portion 13 reaching the P ⁺⁺ layer is provided in a part of the P″ ₂ layer, and the auxiliary gate electrode G _R is bonded to the surface of this portion 2. A cathode electrode K is bonded to the surface _{of the second} layer.An anode electrode A is provided to the surface of the _P1 layer.A gate electrode G _O for ON is bonded to _{the second} surface of P″. A power source 3, a resistor 4, and a switch 5 are connected in series between the cathode electrodes K in a direction that forward biases the P ₂ N ₂ junction. Further, a power source 6 and a switch 7 are connected in series between the auxiliary gate electrode G _R and the cathode electrode K. Note that 17 is a cathode electrode extraction terminal, and 18 is an anode electrode extraction terminal.

To explain the operation of the semiconductor device configured in this way, when an ON command pulse is applied to the ON gate electrode G ₀ in the same manner as described above, first the portion 19 close to the gate electrode G ₀ is transferred from the P ₂ layer to the N ₂ layer. (3rd
Current flows from figure a), but in the lateral direction
There is no problem if the current flows all around the cathode _N2 layer facing G ₀ , but in the worst case, only point B is ignited, and the current in the portion 19 near the gate electrode G ₀ begins to flow only in this portion. The spread from point B to direction C is the fastest, but because the narrow parts 10 and 11 of the P ⁺⁺ layer are narrow, C
It was found that the current started to flow in the D direction and the E direction a little later than the current direction, and the conduction area expanded, and the conduction surface spread over the entire area from point B. In this case, as a result of experiments regarding the allowable dimension _t2 of the narrow width portions 10 and 11 of the embedded P ⁺⁺ layer, it was found that there is no problem in practical use if the allowable dimension t2 is set to 50 to 100 μm.

In this example, the low resistance buried P ⁺⁺ layer 1
The narrow part 1 is divided into two parts on the side where the ignition command of 4 is applied.
0 and 11, but the present invention is not limited to this, and instead of dividing into two, a firing command is added to each tooth of the comb-shaped pattern of the low-resistance embedded P ⁺⁺ layer 14. The sides may be arranged as shown in FIGS. 5 and 6. In addition, in FIGS. 5 and 6, it has been found from experiments that the widths t ₆ and t ₇ of the narrow portions of the comb-shaped pattern are preferably 50 to 100 μm.

In addition, in Fig. 1 of this embodiment, a low-resistance embedded
The pattern shape of the P ⁺⁺ layer is a comb pattern shape,
Although the side to which the firing command is applied is divided into a plurality of parts and divided into two here, the present invention is not limited to this, and for example, as shown in FIG. A narrow connecting portion 20 that connects each tooth portion to each other may be provided in a portion close to the dividing portion 8 on the applying side, thereby suppressing the current spreading direction C shown in FIG. The spread of current in the direction may be promoted.
In addition, in FIG. 4, the width _t5 of the connecting portion 20 is 50~
It was experimentally determined that 100 μm is suitable.

Furthermore, although the present embodiment has been described using a GTO as an example, the present invention is not limited thereto, and can be applied to, for example, a normal thyristor, or a structure that applies a reverse bias to the gate to help shorten the turn-off time. It can also be applied to thyristors (gate-assisted off thyristors), etc.

Furthermore, the pattern shape of the embedded layer according to the present invention is
In the explanation, the so-called comb-shaped shape, which is linear and intricate, was explained, but it is not limited to this.
It goes without saying that the shape of the low-resistance embedded layer (tooth shape) may be curved, and various modifications are possible.

As described above, if the semiconductor device according to the present invention is used, the width of the low-resistance buried P ⁺⁺ layer in the region initially fired by the gate is narrowed with respect to the main conduction region, so that the width is reduced in the lateral directions D and E. This makes it easier to widen the ignition range of the cathode, making it possible to bring the entire cathode into a conductive state in a short period of time.This increases the di/dt withstand capability and increases the current capacity.Especially when the gate current is small, the ignition range can be easily expanded. Even if the gate is turned on, the conduction region can be expanded to the same extent as when the gate is turned on with a large gate current.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG ^.
A plan view showing the pattern shape and arrangement of a conventional embedded P ⁺⁺ layer corresponding to the layer, FIG. 3a is a vertical cross-sectional view of the main part of FIG. 1, and FIG. A plan view showing the pattern shape of the low resistance embedded P ⁺⁺ layer, and FIGS. 4, 5, and 6 respectively show other examples of the pattern shape of the low resistance embedded P ⁺⁺ layer of FIG. 1. It is a plan view, and in the figure, A is an anode electrode, K is a cathode electrode,
G ₀ is the on gate electrode, G _R is the auxiliary gate electrode,
3 and 6 are power supplies, 4 are resistors, 5 and 7 are switches, 8
is the divided part, 9, 10, 11 is the narrow part, 12, 13
is the digging part, 14 is the low resistance buried P ⁺⁺ layer, 15, 16
19 is the wide part, 19 is the part close to the gate electrode G ₀ , 2
0 indicates a connecting part.

Claims (1)

[Scope of Claims] 1. A semiconductor control element which is made conductive or conductive or non-conductive using a low-resistance buried layer having a comb-shaped pattern buried in at least a base region, A semiconductor device characterized in that the width of the comb-shaped pattern of the low-resistance buried layer is made narrower on the side to which an ignition command is applied. 2. The width of the narrowed part of the comb-shaped pattern of the low-resistance embedded layer on the side where the firing command is applied is 50 to 100 μm.
A semiconductor device according to claim 1, characterized in that: 3. The semiconductor device according to claim 1, wherein the side of the comb-shaped pattern of the low-resistance buried layer on which a firing command is applied is divided into a plurality of parts to make the width narrower. 4. Claim 3, characterized in that the side on which the ignition command is applied of the comb-shaped pattern of the low-resistance logic layer is divided into a plurality of narrow parts, each of which has a width of 50 to 100 μm. The semiconductor device described. 5. In a semiconductor control element in which a low-resistance buried layer having a comb-shaped pattern embedded in at least a base region is used to make it conductive or to make it conductive or non-conductive, the low-resistance buried layer is The comb-shaped tooth-like pattern has a narrower width on the side to which the firing command is applied, and the parts of the respective parts corresponding to the teeth of the comb-shaped tooth-like pattern that are closer to the side to which the firing command is applied are connected to each other. semiconductor device. 6. The semiconductor device according to claim 5, wherein the comb-shaped pattern of the low-resistance buried layer is divided into a plurality of narrow widths on the side to which a firing command is applied. 7 The side of the comb-shaped tooth-shaped pattern of the low-resistance embedded layer on which the firing command is applied is divided into a plurality of narrow parts, each of which has a width of 50 to 100 μm, and each tooth part of the comb-shaped tooth-shaped pattern is connected. The width of the connecting part is 50~
The semiconductor device according to claim 6, characterized in that the thickness is 100 μm.