JPS6156810B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an analog output circuit that samples and holds a plurality of time-series data signals and outputs the sample-and-hold data signals.

(2) Prior art When switching, sample-holding, and outputting multiple time-series data signals from a central processing unit, if the central processing unit malfunctions due to a failure, etc.
There is an inconvenience that a correct sample and hold signal cannot be obtained.

(3) Purpose of the Invention In view of the above points, the purpose of the present invention is to provide an analog output circuit that detects malfunctions of a central processing unit.

(4) Embodiment of the Invention FIG. 1 is a configuration explanatory diagram showing an embodiment of the invention.

In the figure, reference numeral 1 denotes a central processing unit such as a microprocessor that generates a plurality of time-series data signals, a location (channel) selection signal, and a clock signal for transmitting these signals;
1 is a first register that temporarily holds the data signal of the central processing unit 1 and outputs it in response to a clock signal; 3 is a DA converter that converts the output of the first register 21 into an analog signal; 4 is a DA converter For example, semiconductor analog switches 41, 42, such as FETs, sequentially select and take out the analog outputs of 3.
The switching circuit 51, 52, . . . consists of resistors r ₁ , r _{2 ,} . . . which sample and hold the outputs taken out by the switches 41, 42 .
..., a time constant circuit consisting of capacitors C ₁ , C ₂ , ... and a sample-and-hold circuit including amplifiers A ₁ , A ₂ ..., 61, 62, ... output from the sample-and-hold circuits 51, 52, ... This is the output terminal to take out.

Further, 22 is a second register that temporarily holds the location selection signal of the central processing unit 1 and outputs it in response to a clock signal. A driving gate circuit 8 detects the presence or absence of a clock signal from the central processing unit 1, and when the clock signal no longer comes, it resets the contents of the first register 21 and sets all parts of the gate circuit 7 to a high level. This is a detection circuit. Note that the detection circuit 8 is, for example,
An inverter I inverts the clock signal, a switching means such as a transistor Tr whose output is supplied to the base B via a resistor _R3 , and a resistor between the collector C of the transistor Tr and the power supply Vcc.
A resistor R ₂ and a capacitor C' are connected in series between R ₁ , the collector C, and the emitter E, and the output of the capacitor C' is supplied to the first register 21 and the gate circuit 7. It is assumed that R ₁ ≫ R ₂ and that the charging of the capacitor C′ is slow and the discharging is fast.

Next, the operation will be explained.

The central processing unit 1 generates a data signal and a location selection signal corresponding to each channel at a predetermined period, and the data signal is sent to the switching circuit 4 via the first register 21 and the DA converter 3 according to the clock signal. Supplied. The location selection signal that determines from which location this data signal is output is also stored in the second register 2.
2. Through the gate circuit 7, each switch 41, 42, .
The output signal of the DA converter 3 is taken in by the terminals 2, . . . and outputted from the output terminals 61, 62, .
These operations are then repeated in sequence to obtain continuous analog output for each channel.

On the other hand, the detection circuit 8 switches the transistor every time the clock signal in the first half of FIG. 2a comes from the central processing unit 1.
The Tr turns on, discharges the charge stored in the capacitor C', and continues charging until the next clock signal arrives. The capacitor is turned on again by the next clock signal.
The charge on C' is discharged (see Figure 2b). As described above, when the central processing unit 1 is operating normally and the clock signal arrives at a predetermined period, the charge on the capacitor C' is always at a low level.

By the way, if the central processing unit 1 is in an abnormal state due to a failure or the like, the clock signal does not come to the detection circuit 8 as shown in the latter half of FIG. 2a. Then the capacitor
The charge charged to C′ is never discharged,
As shown in the second half of Figure 2b, the level finally reaches a predetermined level.
It exceeds Ec. Therefore, the first register 21 is reset and supplies zero output to the D-A converter 3 for the first time by an output higher than this level Ec, and an output higher than this level Ec causes all the gate circuits 7 to It is supplied to the circuit and all gates are set to high level. Therefore, zero output is supplied to all the switches 41, 42, . . . of the switching circuit 4, all the switches 41, 42, .
The content of becomes 0, and zero output is output terminal 61, 6.
2. It will be taken out from...

Note that FIG. 2b is an enlarged view of FIG. 2a.

(5) Summary of the Invention As described above, the present invention detects the presence or absence of a clock signal using a detection circuit, resets a register for a data signal, and sets all parts of a gate circuit for a part selection signal to a high level. , an analog output circuit that responds to abnormalities in the central processing unit.

(6) Effects of the invention Therefore, an abnormality in the central processing unit can be detected with an extremely simple configuration, and all analog outputs can be set to zero. Also transistor,
Since a detection circuit consisting of a capacitor and a resistor is used, the circuit is inexpensive and has practical effects such as being able to easily set the delay time for generating an output when a pulse does not arrive.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining operation. 1...Central processing unit, 21, 22...Register, 3...D-A converter, 4...Switching circuit, 4
1, 42...Switch, 51, 52...Sample hold circuit, 7...Gate circuit, 8...Detection circuit.

Claims (1)

[Claims] 1 A central processing unit that generates a plurality of data signals, a location selection signal, and a clock signal for sending these signals, a register that temporarily holds the data signals of this central processing unit, and an analog signal for the output of this register. a D-A converter for converting into
A switching circuit consisting of a plurality of switches that switches the output of this D-A converter, a plurality of sample and hold circuits that sample and hold the output of this switching circuit, and a point selection signal of the central processing unit is supplied to the switching circuit. A gate circuit drives one of the switches, and when the central processing unit's clock signal stops coming, it generates an output signal to reset the register and sets all parts of the gate circuit to high level. A detection circuit operates to turn on a switch and extract zero output from all output terminals, and the detection circuit is connected between a transistor whose base is supplied with a clock from a central processing unit, and the collector of this transistor and a power supply. It consists of a first resistor connected to the transistor, a second resistor and a capacitor connected in series between the emitter and collector of the transistor, and the output is taken out from this capacitor, and the resistance value of the second resistor is set to the first resistor. An analog output circuit characterized by using a circuit whose resistance value is smaller than that of a resistor.