JPS6158966B2 - - Google Patents
Info
- Publication number
- JPS6158966B2 JPS6158966B2 JP55110599A JP11059980A JPS6158966B2 JP S6158966 B2 JPS6158966 B2 JP S6158966B2 JP 55110599 A JP55110599 A JP 55110599A JP 11059980 A JP11059980 A JP 11059980A JP S6158966 B2 JPS6158966 B2 JP S6158966B2
- Authority
- JP
- Japan
- Prior art keywords
- management information
- circuit
- product management
- control
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は、半導体装置に係り、特に製造工程
試験工程の自動化に適し、アセンブルするときの
自動化に役立たせることのできる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device that is suitable for automating manufacturing test steps and that can be useful for automating assembly.
最近、カスタムLSIの需要がますます増えてお
り、数百個、数十個あるいは数個だけ必要である
というような少量多品種時代に突入しつつある。
このような状勢になると製品管理を現状のような
汎用の大量生産と同じ管理方式をとり続ければ相
当な工数と人手と場所を必要とすることになる。
例えば、現在少量多品種の生産工程では、マスタ
ー・スライス法やPLA（programmable logic
array）法などによつて、一つの下地から配線な
どを変更するだけで少量多品種に答えようとして
いるが、この下地を作る工程までは大量生産方式
をとれるが、その後の配線工程以後はそのように
はいかず、１つの下地から何千品種と出て来るこ
とが予想される。この場合、一品種が数個のもの
から数百個のものまで同一の製造ラインで管理し
なければならない。配線後のウエーハ・テストか
らはじまりパツケージング工程、捺印工程、信頼
性テスト等で品種が多くなれば、人手の介在も多
くなり、伝票処理も増え、工数が急激に増加する
ことが予想される。また、人手によつて数個単位
で物が製造ラインを流れたら品種の読み違いによ
る誤りも多くなることが考えられる。これではカ
スタムLSIに要求されるターン・アラウンド・タ
イムの短かさとコストの安さは逆に、長く、高く
なり、円滑な少量多品種生産ができなくなる。 Recently, the demand for custom LSIs has been increasing more and more, and we are entering an era of high-mix, low-volume LSIs where hundreds, tens, or even just a few pieces are required.
In such a situation, if we continue to manage products in the same manner as the current general-purpose mass production, it will require a considerable amount of man-hours, manpower, and space.
For example, in the current low-volume, high-mix production process, the master slicing method and PLA (programmable logic
We are attempting to produce a wide variety of products in small quantities by simply changing the wiring etc. from a single base using the array method.However, mass production is possible up to the process of making this base, but after the wiring process. It is expected that thousands of varieties will emerge from a single base. In this case, it is necessary to manage everything from a few items to several hundred items of one type on the same production line. As the number of product types increases, starting from wafer testing after wiring, packaging process, stamping process, reliability testing, etc., it is expected that human intervention will increase, the number of slips will increase, and the number of man-hours will increase rapidly. Furthermore, if products are passed down the production line in units of several by hand, there will be many errors due to misreading of product types. In this case, the short turnaround time and low cost required for custom LSIs become longer and more expensive, making smooth low-volume, high-mix production impossible.
本発明は上に述べたような不便さを解消した半
導体装置である。 The present invention is a semiconductor device that eliminates the above-mentioned inconveniences.
以下に、本発明の実施例により図面を参照して
説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の実施例であるICのペレツト
の一部を示している。このペレツトではボンデイ
ング・パツト１，２，３，４，５と内部回路１
１，１２，１３，１４，１５との間にスイツチ回
路と製品管理情報を内蔵した回路６，７，８，
９，１０をもうける。この回路６，７，８，９，
１０には製品管理情報として１か０の論理信号ま
たはある電圧レベルを有した回路と、さらに内部
回路１１，１２，１３，１４，１５とこの製品管
理情報回路とを切り換えるスイツチ回路を有して
いる。６，７，８，９，１０の回路はスイツチ制
御線１６に接続されており、この制御線に信号を
加えることによりボンデイング・パツトが（また
はパツケージのピン）製品管理情報信号モードに
なつたり、内部回路信号モードになつたりする。 FIG. 1 shows a portion of an IC pellet that is an embodiment of the present invention. In this pellet, bonding parts 1, 2, 3, 4, 5 and internal circuit 1
1, 12, 13, 14, 15, circuits 6, 7, 8, with built-in switch circuits and product management information.
Make 9, 10. This circuit 6, 7, 8, 9,
10 has a circuit having a logic signal of 1 or 0 or a certain voltage level as product management information, and a switch circuit for switching between internal circuits 11, 12, 13, 14, and 15 and this product management information circuit. There is. The circuits 6, 7, 8, 9, and 10 are connected to a switch control line 16, and by applying a signal to this control line, the bonding pad (or package pin) is placed in the product management information signal mode. It becomes internal circuit signal mode.
第２図は第１図の回路を用いて製品番号を表示
している例である。各ボンデイング・パツト２１
〜４０はスイツチ回路により製品管理情報信号モ
ードになつて、“１”または“０”の論理信号が
出ている状態を示す。２１ピンは“１”、２２ピ
ンは“１”、２３ピンは“０”、２４ピンは“１”
でこれらより16進表示に変換すると“Ｄ”となり
以下同じように２５から４０ピンまで次々に読み
取ると“D7891”という製品名を読み取ることが
できる。ボンデイング・パツトの数が多ければ製
品名の他に製造番号、テスト・プログラム名、製
造装置番号等の製品管理情報を入れることができ
る。 FIG. 2 is an example of displaying a product number using the circuit shown in FIG. 1. Each bonding part 21
40 indicates a state in which the switch circuit enters the product management information signal mode and a logic signal of "1" or "0" is output. Pin 21 is “1”, pin 22 is “1”, pin 23 is “0”, pin 24 is “1”
If you convert these to hexadecimal notation, it becomes "D", and if you read pins 25 to 40 one after another in the same way, you can read the product name "D7891". If there are a large number of bonding pads, it is possible to include product management information such as a serial number, test program name, manufacturing equipment number, etc. in addition to the product name.
この発明による効果には次の様なものがある。 The effects of this invention include the following.
(1) 同一製造ラインに少量で多品種を流しても管
理情報を使つた自動化ラインを組みやすくな
る。(1) Even if a wide variety of products are run in small quantities on the same production line, it will be easier to set up an automated line using management information.
(2) ペレツト単位に管理情報があるため、一つの
ウエーハに多品種作つても、ウエーハ・プロー
バを特別変更せずプログラムの追加だけでウエ
ーハの管理が行える。(2) Since management information is provided for each pellet, even if a variety of products are produced on a single wafer, the wafer can be managed simply by adding a program without making any special changes to the wafer prober.
(3) パツケージ単位に電気的管理情報を持つてい
るため一品種ごとに特別な出庫場所（または入
庫場所）を用意しなくてもグループ単位でまと
めて保管しておき、出庫（または入庫）のとき
はグループ単位でまとめて選別機にかけて必要
なものを選び出せるようになる。(3) Since each package cage has electrical management information, it is not necessary to prepare a special warehouse location (or warehouse location) for each product, and it is possible to store them together in groups, and At some point, you can put them in groups and put them through a sorting machine to pick out the items you need.
(4) ボンデイング・パツト上に管理情報が出るよ
うになつているため、テスターなどは従来機の
プログラムを変更する程度（テスト・プログラ
ム自動選択ルーチン）で少量多品種型テスタに
改造できる。(4) Since management information is now displayed on the bonding pad, testers can be converted into low-volume, high-mix testers by simply changing the program of the conventional machine (automatic test program selection routine).
(5) 電子ビーム描画装置の直接描画はスルー・プ
ツトが悪いが、一つのウエーハに多数品種を描
画してもペツト単位の管理システムを用いるこ
とにより、それをカバーできるようになる。(5) Direct lithography using an electron beam lithography system has a poor throughput, but by using a pet-by-pet management system, even if multiple types of wafers are to be scribed on a single wafer, this can be compensated for.
(6) ペレツト単位（またはパツケージ単位）に電
気的管理情報を持つているためテスターの検出
機能とテスト・プログラム自動選択ルーチンを
ユニツト化して少量多品種の搬送ライン自動化
も同一ユニツトを使うことにより安くできる。(6) Since each pellet (or package) has electrical management information, the tester's detection function and test program automatic selection routine can be integrated into a single unit, making it possible to automate a conveyance line for small quantities and a wide variety of products using the same unit. can.
(7) (6)のユニツトをアセンブル・ユーザが使用す
ることにより実装工数を大巾に少なくすること
ができる。(7) By using the unit in (6) by an assembler user, the number of mounting steps can be greatly reduced.
第１図は本発明の実施例であるICのペレツト
の一部を示す平面図である。第２図はボンデイン
グ・パツトに“１”，“０”の論理で製品管理情報
が出力されていることを示す説明図である。
図中、１乃至５……ボンデイング・パツト、６
乃至１０……スイツチ回路と製品管理情報回路、
１１乃至１５……内部回路、１６……スイツチ制
御線、１７……ペレツト、２１乃至４０……ボン
デイング・パツト、４１……ペレツト。
FIG. 1 is a plan view showing a part of an IC pellet according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing that product management information is outputted to the bonding pad with logics of "1" and "0". In the figure, 1 to 5... bonding parts, 6
to 10... switch circuit and product management information circuit,
11 to 15...internal circuit, 16...switch control line, 17...pellet, 21 to 40...bonding pad, 41...pellet.
Claims (1)
イツチ回路と製品管理情報を“１”か“０”かの
論理信号として内蔵した制御回路をそれぞれ設
け、これらそれぞれの制御回路に共通に制御線を
接続し、この制御線のレベルに応答して各制御回
路は外部端子と内部回路とを接続する第１のモー
ドと、該外部端子を内部回路から分離して内蔵さ
れた製品管理情報を該外部端子に出力する第２の
モードとを有するICチツプを有することを特徴
とする半導体装置。1 A control circuit containing a switch circuit and product management information as a logic signal of "1" or "0" is provided between the plurality of external terminals and the plurality of internal circuits, and a common control is provided to each of these control circuits. In response to the level of this control line, each control circuit has two modes: a first mode in which the external terminal is connected to the internal circuit, and a first mode in which the external terminal is separated from the internal circuit to display built-in product management information. A semiconductor device comprising an IC chip having a second mode for outputting to the external terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059980A JPS5735332A (en) | 1980-08-12 | 1980-08-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11059980A JPS5735332A (en) | 1980-08-12 | 1980-08-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5735332A JPS5735332A (en) | 1982-02-25 |
| JPS6158966B2 true JPS6158966B2 (en) | 1986-12-13 |
Family
ID=14539928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11059980A Granted JPS5735332A (en) | 1980-08-12 | 1980-08-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5735332A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961056A (en) * | 1982-09-30 | 1984-04-07 | Fujitsu Ltd | Semiconductor chip |
| JPS59115637U (en) * | 1983-01-26 | 1984-08-04 | 日本電気アイシ−マイコンシステム株式会社 | semiconductor wafer |
| JPS6092606A (en) * | 1983-10-26 | 1985-05-24 | Nec Corp | Manufacture of semiconductor device |
| JPS61156839A (en) * | 1984-12-28 | 1986-07-16 | Mitsubishi Electric Corp | Semiconductor device |
-
1980
- 1980-08-12 JP JP11059980A patent/JPS5735332A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5735332A (en) | 1982-02-25 |
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