JPS6214109B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing a shotgun barrier gate field effect transistor.

Conventionally, as shown in FIG. 1, a semi-insulating substrate 1 made of, for example, GaAs is prepared in advance (FIG. 1A) as a manufacturing method for a shotgun barrier gate field effect transistor (hereinafter simply referred to as a transistor for simplicity). For example, an N-type semiconductor layer 2 made of GaAs, for example, is formed on the substrate 1 by a process using a crystal growth method (FIG. 1B), and then extended over the semiconductor layer 2 and connected with an ohm. Contacting metal layers 3 and 4 made of, for example, an Au-Ge alloy are simultaneously formed by a process including a process using photolithography (FIG. 1C), and then the metal layers 3 and 4 are formed on the semiconductor layer 2. 3
A metal layer 6 made of a metal such as Al or Au is formed by a process including a process using a photolithography method, extending in the area 5 between the areas 5 and 4 and making spot contact with the area 5. Figure D), thus metal layer 3
A method has been proposed in which a transistor is obtained in which the metal layer 6 and the metal layer 6 are used as a source electrode and a drain electrode, respectively, and the metal layer 6 is used as a gate electrode.

By the way, the transistor shown in FIG. 1D obtained by the above-mentioned manufacturing method has a gate with a load connected between the metal layer 3 as a source electrode and the metal layer 4 as a drain electrode via a power source. When a control voltage is applied between the metal layer 6 as an electrode and the metal layer 3 as a source electrode, it has the function of controlling the current flowing to the load in the region 5 of the semiconductor layer 2. In the case of the conventional manufacturing method described above in FIG. For this reason, it was not possible to easily manufacture the desired transistor.

Further, in the case of the transistor shown in FIG. 1D obtained by the manufacturing method described above in FIG.
The shorter the length L _g of the gate electrode, the higher the performance and the function described above. However, in the case of the conventional manufacturing method shown in FIG.
The metal layer 6 as a gate electrode is formed by a process including a process using a photolithography method, while generally corresponding to the metal layer 6 is formed by a process including a process using a photolithography method. When forming a layer, there is a certain limit to the resolution of the process, so there is a certain limit to the miniaturization of the layer, so the metal layer 6 and therefore the gate electrode are formed as short ones with a length L _g . However, there are certain limits to the ability to obtain a desired transistor with higher performance.

Further, in the case of a transistor obtained by the conventional manufacturing method described above, the metal layers 3 and 4 of the semiconductor layer 2
The smaller the series resistance between each of the metal layers 3 and 6 as the source electrode and the metal layer 6 as the gate electrode, the smaller the series resistance between the metal layer 3 as the source electrode and the metal layer 6 as the gate electrode. and the metal layer 6
In particular, the _smaller the distance L _{S is} , the higher the performance is and the function described above is exhibited. However, in the case of the conventional manufacturing method described above in FIG. After that, the metal layer 6 is formed, and the metal layer 6 is formed by a process including a process using a photolithography method. Since the metal layer 6 is not formed to be connected to the metal layer 3 or 4, it requires mask alignment, and there is a certain limit to the precision of the mask alignment, so the distance between the metal layer 6 and each of the metal layers 3 and 4 is L _S
And L _D has certain limitations, especially when the distance L _S is small, and thus there are certain limitations in obtaining a target transistor with higher performance. had.

SUMMARY OF THE INVENTION Accordingly, the present invention proposes a novel method for manufacturing a short barrier gate type field effect transistor free from the above-mentioned drawbacks, which will become clear from the detailed description below.

FIG. 2 shows an example of a method for manufacturing a transistor according to the present invention. As shown in FIG. 2A, a semi-insulating substrate 10 made of GaAs, for example, is prepared in advance, and For example, as shown in B
For example, an N-type semiconductor layer 11 made of GaAs is grown to a certain thickness by processing using a known crystal growth method.
It is formed to have a thickness of 0.1 to 0.5 μm and an impurity concentration of, for example, 5 to 50×10 ¹⁶ cm ⁻³ . Next, as shown in FIG. 2C, SiO ₂ ,
In order to form the semiconductor regions 14 and 15 of the semiconductor layer 11 sandwiching the insulating layer 13 made of Si ₃ N ₄ , Al ₂ O ₃ or the like when viewed from above, a well-known photolithography method is used. For example, a thickness of 1 to 2 μm, 2 to 3
It is formed to have a length in the direction connecting the semiconductor regions 14 and 15 of μm or more and a rectangular parallelepiped cross section.

Next, the angle between the semiconductor layer 11 and the semiconductor layer 11 is less than 90 degrees when viewed in a plane perpendicular to the upper surface of the semiconductor layer 11 (generally referred to as M) including a line in the direction connecting the semiconductor regions 14 and 15. _Straight deposition of a metal such as an Au-Ge alloy in ohmic contact with the semiconductor layer 11 using a vacuum evaporation method or the like from an obliquely upward direction as indicated by an arrow A in FIG. As shown in FIG. 2D, as shown in _FIG . A metal layer 16 extends from the position P1, which is a distance D ₁ , to the side opposite to the insulating layer 13 side and makes ohmic contact with the semiconductor region 14; A metal layer 17 for ohmic contact is formed at the same time.

Next, an angle θ ₂ larger than the above-mentioned angle θ 1 is taken between the semiconductor layer 11 and the semiconductor layer ₁₁ when viewed within the above-mentioned plane M in the diagonally upward direction shown by the arrow B in FIG. 2E. 2E, the semiconductor region 14 between the insulation layer 13 and the metal layer 16 is formed as shown in FIG. 2E. The insulating layer 1 is placed on the insulating layer 18 from the position P2 at a distance _D2 which is smaller than the above-mentioned distance _D1 determined by the value of the angle _θ2 mentioned above and the thickness of the insulating layer 13.
An insulating layer 19 is formed on the opposite side of the insulating layer 19 so as to extend continuously up to the top of the metal layer 16.

In this case, at the same time as the insulating layer 19, an insulating layer 20 extending over the metal layer 17 is also formed.

Next, from the diagonal upward direction shown by _{arrow C} in FIG. As shown in FIG. 2F, as shown in FIG. A distance D 3 from the insulating layer 13 on the semiconductor region 21 between the insulating layers 13 and 19 is set from the insulating layer ₁₃ with a value smaller than the above-mentioned distance D ₂ determined by the value of the angle θ 3 mentioned above and the thickness of the insulating layer ₁₃ . Insulating layer 13 from the taken position P3
A semiconductor region 21 is continuously extended to the top of the insulating layer 19 on the side.
A metal layer 22 is formed in direct contact with the metal layer 22 . In this case, a metal layer 23 extending over the insulating layer 20 is also formed simultaneously with the metal layer 22 .

In this way, the desired transistor is obtained.

The above is an example of the method for manufacturing a transistor according to the present invention. The transistor shown in FIG.
1, and metal layers 16, 17, and 22, the substrate 1, the semiconductor layer 2, and the metal layers 3, 4 of the transistor shown in FIG.
and 6, respectively. Therefore, it is possible to perform the same function as the transistor described above in FIG. However, in the case of the manufacturing method of the present invention described above in FIG. Although three deposition processes are required: a process including a process for forming the metal layer 22 and a process including a process for forming the metal layer 22, the process including the process for forming the metal layer 22 is a process that includes a process using a photolithography method. On the other hand, the process including the process using the photolithography method is only one time when forming the insulating layer 13, and therefore the target transistor can be formed more easily than in the case of FIG. It can be manufactured.

Further, the transistor shown in FIG. 2F obtained by the manufacturing method of the present invention described above in FIG.
As in the case of the transistor described above, the shorter the length of the metal layer 22 in contact with the semiconductor layer 11, that is, the length of the gate electrode L _g , the higher the performance and the function described above is exhibited. Yes, but the second
In the case of the manufacturing method of the present invention described above with reference to the drawings, the metal layer 22 as the gate electrode is made of a metal that is in ohmic contact with the semiconductor layer 11 from diagonally above, taking the above-mentioned angle θ ₃ with respect to the semiconductor layer 11 using the insulating layer 13. In this case, by appropriately selecting the angle θ ₃ mentioned above, the length L _g of the metal layer 22 can be made sufficiently small.
The metal layer 22 and therefore the gate electrode can be formed to have a sufficiently short length L _g , thereby making it possible to obtain the desired transistor with higher performance than in the case of FIG. 1. It is.

Furthermore, the transistor shown in FIG. 2F obtained by the manufacturing method of the present invention described above in FIG. The smaller the series resistance between the metal layer 16 as the source electrode and the metal layer 22 as the gate electrode, the smaller the series resistance between the metal layers 16 and 17 and the metal layer 22. The distance between L _S and L _D especially the distance L
The smaller _S is, the higher the performance is and the function described above is exhibited. However, in the case of the manufacturing method of the present invention described above in FIG. In this case, the length of the insulating layer 13 is made small and the angle θ _{1 is}
By appropriately selecting metal layers 16 and 17
In addition, the insulating layer 19 is formed by applying the insulating material to the semiconductor layer 11 using the insulating layer 13 by a process including applying the insulating material from diagonally above at an angle θ ₂ as described above. In this case, by appropriately selecting the angle θ ₂ mentioned above, the length of the insulating layer 19 connected to the semiconductor layer 11 can be made sufficiently small. Semiconductor layer 1 that similarly utilizes insulating layer 13
The metal layers 16, 17 and 22 are formed so as to be connected to the insulating layer 19 by applying metal from diagonally above the metal layer 1.
The distance L _S between each of 6 and 17 and the metal layer 22
and L _D , especially the distance L _{S ,} can be made sufficiently small, and the desired transistor can be obtained with higher performance than in the case of Fig. 1. It has the following characteristics.

Next, referring to FIG. 3, another example of the method for manufacturing a transistor according to the present invention will be described.
As shown in FIGS. A to F, the detailed explanation will be omitted, but a semiconductor layer 11 is formed as shown in FIG.
A metal layer 1 is provided on the semiconductor region 14 side of the semiconductor region 14 to be connected thereto.
6. Obtaining a structure in which an insulating layer 19 and a metal layer 22 are formed, and a metal layer 17 in contact with the semiconductor region 15 side and an insulating layer 20 and a metal layer 23 formed on the metal layer 17 are formed. .

Next, from the diagonally _upward direction shown by arrow _D in FIG. As shown in FIG. 24 from the insulating layer 13 to the value of the angle θ ₄ mentioned above and the insulating layer 1
Insulating layer 1 from position P4, which is a distance _D4 smaller than the above-mentioned distance _D3 determined by the thickness of
An insulating layer 25 is formed on the side opposite to the third side so as to extend continuously up to the top of the metal layer 22.

In this case, at the same time as the insulating layer 25, an insulating layer 26 extending over the metal layer 23 is also formed.

Next, the semiconductor layer 11 is subjected to a process including a process of depositing a metal in ohmic contact with the semiconductor layer 11 from directly above as shown by the arrow E in FIG. As shown in FIG. 3H, the insulating layers 13 and 2 formed by the semiconductor region 24 are
A metal layer 28 is formed on the semiconductor region 27 between the holes 5 and 5 in ohmic contact with the semiconductor region 27. In this case, like the metal layer 28, metal layers 29 and 30 are also formed which extend over the insulating layers 25 and 26, respectively.

In this way, the desired transistor is obtained.

The above is another example of the method for manufacturing a transistor according to the present invention.
In the transistor shown in FIG. 2F obtained by the manufacturing method of the present invention described above in FIG. It has a structure in which an insulating layer 25 and a metal layer 28 are formed in contact with the semiconductor layer 11 between the metal layer 2 and the metal layer 28.
It is clear that 8 can be used as a drain electrode instead of the metal layer 17, so the function is similar to that of the transistor described above in FIG. However, in the case of the manufacturing method of the present invention described above in FIG. 3, in addition to the sequential steps in the manufacturing method of the present invention described above in FIG.
Since the process includes a process including an adhesion process when forming the metal layer 28, the desired transistor can be easily manufactured in the same manner as in the manufacturing method of the present invention described above in FIG. It's something you get.

In addition, in the case of the manufacturing method of the present invention described above in FIG. 3, the metal layer 16 serving as the source electrode, the insulating layer 19, and the metal layer 22 serving as the gate electrode are the same as in the case of the manufacturing method of the present invention described above in FIG. , and the insulating layer 2
5, and a metal layer 28 serving as a drain electrode are formed in the same manner as the insulating layer 25 and metal layers 16 and 22 are formed, and in this case, the distance between the alloy metal layers 22 and 28, and therefore the gate electrode and the drain electrode. Since the distance L _D between the electrodes can be made much smaller than in the case of FIG. 2, the target transistor can have even higher performance than in the case of FIG. 2, etc. It has the following great characteristics.

In the above description, the metal layer 16 is formed as a source electrode, and the metal layers 17 and 28 are formed as drain electrodes. However, conversely, the metal layer 16 is formed as a drain electrode, and the metal layers 17 and 28 are formed as source electrodes. Alternatively, the substrate 10 may be a P-type semiconductor substrate, the substrate 10 may be an insulating substrate,
The substrate 10 and the semiconductor layer 11 can be respectively made of a semi-insulating substrate or an insulating substrate and an N-type or P-type semiconductor layer, and furthermore, in the manufacturing method described above in FIG. Instead of forming the insulating layer 2 from above, it is also possible to form the insulating layer 2 from above obliquely, and furthermore, in the manufacturing method described above in FIG.
In the manufacturing method described above in FIG. 3, the insulating layers 13, 20 and 26 and the metal layers 17, 23 and 30 are removed after the step in FIG. , and various other modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

1A to 1D are schematic cross-sectional views in sequential steps showing a conventional method for manufacturing a transistor, and FIG. 2 is a schematic cross-sectional view in sequential steps showing an example of a method for manufacturing a transistor according to the present invention. 3A and 3B are schematic cross-sectional views in sequential steps showing another example of the method for manufacturing a transistor according to the present invention. In the figure, 10 is a phase plate, 11 is a semiconductor layer, 13, 1
9 and 25 are insulating layers, 14, 15, 18, 21,
24 and 27 are semiconductor regions, and 16, 17, 22 and 28 are metal layers, respectively.

Claims (1)

[Claims] 1. A first insulating layer on a semiconductor layer, and a first insulating layer formed by the semiconductor layer sandwiching the first insulating layer when viewed from above.
and a step of forming a second semiconductor region, and a process of depositing a first metal in ohmic contact with the semiconductor layer from an obliquely upward direction with respect to the semiconductor layer, thereby forming a first semiconductor region. above first
a first metal layer that extends from a position a predetermined distance from the insulating layer to the side opposite to the first insulating layer and makes ohmic contact with the first semiconductor region; and the second semiconductor region. and a second metal layer that extends continuously over the first insulating layer and is in ohmic contact with the second semiconductor region, and applying an insulating material to the semiconductor layer from an obliquely upward direction. The process including the process causes the first semiconductor region to form a third semiconductor region between the first insulating layer and the first metal layer from a position at a predetermined distance from the first insulating layer. forming a second insulating layer that extends continuously up to the first metal layer on the side opposite to the first insulating layer; and making spot contact with the semiconductor layer from an obliquely upward direction with respect to the semiconductor layer; A process including a second metal deposition process causes the third semiconductor region to form a predetermined distance from the first insulating layer onto the fourth semiconductor region between the first and second insulating layers. forming a third metal layer that continuously extends from the position opposite to the first insulating layer to above the second insulating layer and makes occasional contact with the fourth semiconductor region. A method for manufacturing a shotgun barrier gate field effect transistor characterized by the following. 2. A first insulating layer on the semiconductor layer, and a first insulating layer formed by the semiconductor layer sandwiching the first insulating layer when viewed from above.
and a step of forming a second semiconductor region, and a process of depositing a first metal in ohmic contact with the semiconductor layer from an obliquely upward direction to the semiconductor layer. The first insulating layer extends from a position on the region at a predetermined distance from the first insulating layer to the side opposite to the first insulating layer.
forming a first metal layer in ohmic contact with the semiconductor region; and depositing a first insulating material on the semiconductor layer from an obliquely upward direction. the first insulating layer and the third semiconductor region between the first insulating layer and the first metal layer;
forming a second insulating layer that extends continuously from a position at a predetermined distance from the insulating layer to above the first metal layer on the side opposite to the first insulating layer; By a process including a process of depositing a second metal that is in spot contact with the semiconductor layer from an obliquely upward direction, the third semiconductor region is applied onto the fourth semiconductor region between the first and second insulating layers. A first insulating layer that continuously extends from a position a predetermined distance from the first insulating layer to the second insulating layer on the side opposite to the first insulating layer side and makes occasional contact with the fourth semiconductor region. 3 and a process of depositing a second insulating material on the semiconductor layer from an obliquely upward direction, the first insulating layer and the third metal are formed in the fourth semiconductor region A third layer continuously extending from a position at a predetermined distance from the first insulating layer to the third metal layer on the side opposite to the first insulating layer on the fifth semiconductor region between the layers. A process including forming an insulating layer and depositing a third metal in ohmic contact with the semiconductor layer from above on the semiconductor layer allows the first and third semiconductor regions to be in contact with each other by the fifth semiconductor region. forming a fourth metal layer in ohmic contact on the sixth semiconductor region between the insulating layers.