JPS6218066B2 - - Google Patents

Description

Claim 1: Selectively addressable storage means comprising a plurality of memories; and addressing means for addressing said memory to read selected memory data therefrom; said selected memory data; includes a plurality of check bits selected to be able to determine whether at least one bit error exists in the selected memory data, one for each memory and included therein; for detecting and correcting one-bit memory read errors in selected memory data read from each memory in response to said check bit, and for detecting and correcting one-bit memory read errors in selected memory data read from each of said memory data whenever a one-bit memory read error is detected; local error detection and correction means for automatically restoring within each memory address; and common error detection and correction in which data read from each memory is provided without correction by the respective local error detection and correction means. the common error detection and correction means is operative to detect and correct single bit errors in response to check bits contained in each selected memory data provided therein; operative to provide a one-bit error signal with a corresponding error signal pattern indicating an incorrect bit each time a one-bit error is detected in the data, said one-bit error signal, said addressing means;
and configured and arranged to operate in response to said error signal pattern such that one bit memory read errors in different memory regions of each memory are detected in the same memory region without a one bit memory read error being detected in between. selective error determination means for indicating that a detected one-bit memory read error in data read from memory is hardware related by determining whether a detected one-bit memory read error in data read from memory is detected twice in succession; and the selective error determining means is configured to, in response to a one-bit error signal, store therein an error signal pattern and a memory address corresponding to the selected memory data that produced the one-bit error signal. an operable error register; and control means for preventing any changes in said error register whenever the same one-bit error is detected twice in succession for selected memory data corresponding to the same memory address. , the control means comprising: a comparator for comparing the currently produced error signal pattern and the corresponding memory address with what is currently stored in the error register; connected to said comparator, responsive to said comparator determining that an address is the same as one currently stored in said error register, thereby preventing any changes in said error register; A data processing device further comprising locking means for locking the data.

2. The check bits are selected to be capable of detecting multiple bit errors in selected memory data, and the common error detection and correction means detect multiple bit errors indicative of detection of multiple bit memory read errors in the provided memory data. 2. A data processing device as claimed in claim 1, wherein the signal is provided with a corresponding error signal pattern.

3. A data processing apparatus according to claim 1, further comprising means for transmitting said error signal pattern and corresponding memory address locked in said error register by said locking means to a utilization device.

4. A data processing apparatus as claimed in claim 3, further comprising means for clearing and unlocking said error register after transmission of said error signal pattern and corresponding memory address locked therein.

Introduction This invention relates to improved means and methods for use in detecting, correcting and recording errors occurring in digital data processing systems. More specifically, this invention:
An improved means and method for detecting, correcting and selectively recording data errors that occur during memory access operations.

BACKGROUND OF THE INVENTION In recent years, increased attention has been paid to means and methods for detecting, correcting, and recording errors that occur during digital data processing operations. In providing such capabilities, an appropriate balance must be struck between the benefits derived from them and the resulting cost, complexity and performance of the additional hardware, firmware and/or software required. It is important to take It therefore becomes important to select equipment for detecting, correcting and recording errors from which appropriate effects can be derived without unduly adding cost, complexity or work to the system.

SUMMARY OF THE INVENTION Therefore, the basic object of the invention is to detect and detect errors in data processing systems.
It is an object of the present invention to provide improved means and methods for use in correcting and/or recording.

A particular object of the invention is to provide improved means and apparatus for use in detecting, correcting and selectively recording certain types of errors that occur during memory access operations.

Another object of the present invention is to provide a simplified method for use with a memory that provides effective error detection and recording capabilities for use in rapidly manipulating single-bit errors that occur during memory read operations. The purpose is to provide equipment.

In certain embodiments of the invention, a relatively simple error detection, correction and recording apparatus is provided for use in conjunction with one or more integrated circuit data processor memories. In order to use this simple device effectively, it should be constructed and arranged in accordance with the present invention to ensure that the error patterns that experience and theoretical considerations indicate are most to be expected from the memory and the resulting Take advantage of operational effects. Therefore, for reasons explained below, this preferred arrangement essentially cannot be corrected by re-execution or by restoring the correct word in memory and then re-executing. It is directed to detecting and correcting 1-bit memory read errors while recording the address and error occurrence pattern of only fixed 1-bit memory read errors, defined as 1-bit errors. Other types of single-bit errors, such as temporary errors, are corrected, but not recorded. This preferred device may therefore be significantly simpler than would otherwise be possible.

Other advantages result from this preferred embodiment by providing correction for one-bit memory read errors in each memory module as well as in the data processor's memory control. One effect of such a configuration is that each memory module restores the corrected value for every one-bit error into its memory without relying on and burdening the processor memory controls. This means that it is possible to do so. Another advantage is that the processor memory control can directly receive uncorrected memory data and can independently detect and correct all single-bit errors, as well as record other types of errors. This means that fixed 1-bit memory read errors can be detected and recorded regardless of the Further, the processor memory control does not need to have a memory module that provides error detection and correction data, nor does it need to restore corrected words in the memory module that provided the data. The processor memory control can therefore be disconnected from the memory module as soon as it receives uncorrected data therefrom, as if those performance-related errors had never occurred.

Particular features of the invention, as well as other objects, features, advantages, uses and possible modifications thereof, will become apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings.

[Brief explanation of the drawing]

FIG. 1 is a block diagram generally illustrating a processor memory control system incorporating the present invention. FIG. 2 is a block diagram showing how the preferred apparatus is provided for each memory module in FIG. FIG. 3 is a block diagram illustrating how the preferred device is implemented within the processor memory control of FIG.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Like numbers and letters represent like elements throughout the drawings.

For the preferred embodiment where integrated circuit memory is used, the most common type of error that can be expected to occur is a one-bit memory read error.
Therefore, to maintain simplicity, the preferred embodiment of the present invention is primarily concerned with handling one-bit memory read errors.

A one-bit memory read error is characterized as permanent or temporary. As previously pointed out, a fixed 1-bit error is characterized by the fact that the error is not corrected even after re-running the read operation after restoring the corrected word back into memory. A one-bit error in a word read from memory.

A temporary one-bit memory read error is an error that can be corrected by re-executing (one or more times) or by restoring and then re-executing. Temporary 1-bit memory read errors that can be corrected by restoring and then rerunning are commonly referred to as output errors, and temporary 1-bit memory read errors that require restoring to obtain correction are commonly referred to as output errors. are usually referred to as soft errors.

Transient errors are considered not to be easily diagnosed because they do not occur during diagnostic operations. Also, unlike fixed errors, temporary errors do not necessarily occur as a result of defective hardware, but can be generated, for example, by noise or by alpha particle radiation. Furthermore, since temporary 1-bit errors are considered to occur more frequently than fixed 1-bit errors, these temporary errors place a large burden on the error recorder. Additionally, attempts to record these temporary errors hide more important fixed 1-bit errors.

The preferred apparatus of this invention incorporates the above elements and features into a device that is very simple to record fixed 1-bit errors, which is important for detecting and correcting 1-bit memory read errors and for hardware diagnostic purposes. and provide effective equipment.

Referring now to FIG. 1, a plurality of memory modules M ₁ - of one or more processors.
Performs communication between M _o and other processor parts,
A conventional arrangement of processor memory control PMC is shown. Typically, a processor memory control PMC receives read data accessed from memory modules M ₁ -M _o and directs memory modules M ₁ -M _o according to read and write memory addresses and write data. A read and write control signal is selectively applied to the memory.

Referring now to FIG. 2, it is shown how the memory portion of the preferred device is partially provided for use in conjunction with memory 10 of the exemplary memory module of FIG. It will be appreciated that data is read from memory 10 at an address selected in response to read signal R and a memory address provided by processor memory control PMC (FIG. 1). memory 1
This data read from 0 is read in the usual way.
PMC and is also partially applied to a 1-bit error detection and correction unit 12 (of conventional type). As is well known, data read from memory typically includes check bits that are used to detect and correct single bit errors that occur in reading data from a storage device or memory. Further information on error detection and correction devices can be found, for example, in R.
“Error Detecting and
Error Correcting Codes”, Bell Systems
Technical Journal, 29, 1950, PP, 147-160,
JELegory Invention U.S. Patent No. 4168486, HU
U.S. Patent No. 4,052,698 for Ragle invention and Ke-
No. 4,174,537 to Chiang et al.

The 1-bit error detection and correction unit 12 in FIG. 2 detects the occurrence of a 1-bit memory read error, and
automatically restores the corrected data provided by through multiplexer 15 into the same memory address. This multiplexer 15
moves this corrected data to the write input of the memory 10, preferably in response to the current read signal R, thereby causing the restoring of the corrected data whenever a one-bit error is detected. Make it happen automatically. Multiplexer 15 is also responsive to a write signal W provided by PMC (FIG. 1) to write data provided by PMC into the selected memory address in the conventional manner.

Referring now to FIG. 3, there is shown a portion of the processor memory control PMC of FIG. 1 included in the preferred apparatus of the present invention.

It will be appreciated from FIG. 3 that the illustrated portion of the PMC includes its own error detection and correction device 20. Memory read data from the memory module of FIG. 2 is provided to an error detection and corrector 20 which provides four outputs in a conventional manner in response to the data.

(1) A 1-bit error signal indicating the presence of a 1-bit error in the added memory data. (2) A multiple-bit error signal indicating the presence of multiple errors in the added memory data. (3) The type of error that occurred and the error if it is a 1-bit error. Error signal pattern (4) indicating a particular bit of applied memory data (typically referred to in this field as a syndrome bit) Output memory read data that is one of the following: a) Added memory read data if no errors are detected (b) Corrected memory read data if a single bit error is detected (c) Uncorrected memory read data if multiple errors are detected Third Before continuing with the description of the figures, it should be noted that since the preferred apparatus is essentially concerned with single-bit memory read errors, multiple read memory errors will be explained by the corresponding error signal pattern provided by error detection and corrector 20 in FIG. According to the corresponding memory address contained in the address register 23 of FIG. 3, appropriate actions such as aborting a processor operation or resuming an interrupted operation to handle multiple errors are performed. It should be noted that this is preferably handled by simply supplying multiple error signals to the main control part of the processor (not shown) for processing.

In the case of a 1-bit memory read error, the preferred apparatus is capable of operating in the normal manner without the processor interrupting or aborting its operation, as will become apparent from the further discussion of FIG. to be able to continue.

As shown in FIG.
), an AND for controlling the loading of the error register 25 with the error signal pattern (from the error detection and corrector 20) and the corresponding memory address (from the address register 23) each time a one-bit error is detected. gate 2
8. a comparator 30 for comparing the new signal error pattern and the corresponding memory address with what is currently stored in the error register 25;
and a lock that provides a lock signal to disable AND gate 28 in response to comparator 30 finding that the new error pattern and corresponding memory address are the same as those currently stored in error register 25. It includes a flip-flop 32.

Having described the basic construction and arrangement of the memory module and PMC portions of the preferred apparatus shown in FIGS. 2 and 3, respectively, their operation will now be considered. For preferred apparatus in this regard, the addressable word stored in the memory module includes sufficient check bits to detect at least single and multiple bit errors and to correct at least one bit error. shall be present.

Considering first the operations performed due to multiple bit errors, it should now be understood that they are easily manipulated by both the memory and PMC portions of this preferred device. This means that since the 1-bit error detection and corrector 12 is provided to correct and restore only 1-bit memory read errors, the memory portion of the preferred device shown in FIG. It will be obvious if you notice that it is ignored. In any case, uncorrected data read from the memory module is processed by the processor memory control as if the correction and restoring had never occurred in the memory module.
This does not create any problems or burdens on the processor since it is sent directly to the PMC (Figure 2).

As previously noted, the error detection and corrector 20 does not operate to correct or record multi-bit memory read errors, but rather does not operate to correct or record multi-bit memory read errors, but to alert the processor master to appropriate action, such as interrupting or aborting processor operations. Multi-bit memory read errors are detected as 3rd party error signals by providing multiple bit error signals with uncorrected memory data and corresponding memory addresses and error signal pattern addresses for transmission to the control.
It is also easily operated by the PMC part of the preferred device shown in the figure.

Having explained how easily multi-bit memory read errors can be manipulated, we will now explain how single-bit memory read errors can be effectively manipulated by this preferred device without burdening normal processor operations. Explain. From the foregoing discussion, it will be seen that the memory module portion of the preferred apparatus shown in FIG. Processor memory control PMC also processes uncorrected memory data without relying on it.
It is clear that handling one-bit memory read errors without relying on partial correction and restore operations to transmit (FIG. 1). As shown in the preferred apparatus portion illustrated in FIG. 3, uncorrected memory data is provided to an error detection and correction unit 20. If no errors exist, error detection and corrector 20 simply outputs the input memory data without altering the transmission to the processor portion requesting the memory data. On the other hand, if a 1-bit memory read error is detected, the error detection and correction unit 20 outputs the corrected memory data for transmission to the requesting processor section, and the 1-bit error detection and correction unit 20 outputs the corrected memory data for transmission to the requesting processor section. The only delay is the requirement for detection and correction operations, which can be economically designed to occur at high speed.

The remainder of this preferred apparatus, shown in FIG. It is directed towards selectively logging errors. The operations involved in this selective recording of fixed 1-bit memory read errors are independent of and associated with other processor operations, as will become apparent from further discussion of FIG. It should be appreciated that they can be executed concurrently and thus do not burden normal processor operations.

As shown in FIG. 3, when a 1-bit memory read error is detected by error detection and corrector 20 during a clock period, a 1-bit error signal is provided to one input of AND gate 28. The other input of AND gate 28 receives the lock signal provided by lock flip-flop 32 which is initially true as a result of the clear signal provided to lock flip-flop 32 first.

Therefore, when a 1-bit error signal is generated by error detection and corrector 20 during a clock period (as a result of the detection of a 1-bit memory read error), the load signal is generated during the same clock period (as a result of the detection of a 1-bit memory read error). (in register 23)
It is applied to the error register 25 according to the corresponding memory address and the error signal pattern provided by the error detection and correction unit 20. Also during the same clock period, the error signal pattern changes to error register 2 (which is initially set to all zeros by the clear signal).
5 is provided to a comparator 30 for comparison with data currently stored in 5. Therefore, in response to the next occurring clock signal, the error signal pattern generated within the previous clock period is stored in the error register 25 along with the corresponding memory address, and this generated error pattern is stored in the error register 25. 25, comparator 30 does not change the initial setting of lock flip-flop 32.
AND gate 28 thereby remains activated.

The next time a 1-bit error signal is generated by error detection and corrector 20 during a clock period, a new error signal pattern and memory address are stored in error register 25 in response to the previously detected 1-bit error. The same operation as described above is performed again, except that the AND gate 28 remains enabled.

Here, such that the error signal pattern generated by the error detection and corrector 20 and the corresponding memory address provided by the memory address register 23 are the same as that currently stored in the error register 25. to 1
Suppose a bit memory read error is detected, which occurs when two consecutive 1-bit errors are obtained at the same memory address. In such a case, the comparator provides an output to lock flip-flop 32 to change the lock signal from true to false, thereby disabling AND gate 28 and leaving error register 25 unchanged. Become. The processor then responds to this false lock signal by providing a transmission signal to the error register 25 so that the error signal pattern and memory address stored therein are recorded in a suitable recording device 40, such as a memory or display. to be transmitted for. A clear signal is then provided to allow the recording operation to be started again.

It will be appreciated from the above description of the recording operation in FIG. 3 that the particular one-bit memory error recorded is a one-bit memory read error consecutively detected at the same memory address. In other words, the comparator 30 compares the signal pattern and corresponding memory address of the currently detected 1-bit memory read error with the signal pattern and corresponding memory address obtained for the most recently generated 1-bit memory error signal. That is, it is compared with what is currently stored in the error register 25, so that if there are one or more 1-bit memory read errors to different memory addresses between the two detected 1-bit memory read errors corresponding to the same memory address. In that case, no recording is made at all. The use of such successively occurring single-bit errors for recording purposes provides an effective and easy way to detect and record fixed single-bit errors, which, as pointed out earlier, are most important from the standpoint of hardware defects. It was discovered that there is a method. Therefore, unimportant transient errors are conveniently ignored, and since it is highly unlikely that two transient memory read errors for the same memory address occur in succession, each Partially auto-corrected in memory module.

It will be appreciated that many modifications and changes may be made to this invention in construction, arrangement and use without departing from the true scope of the invention. The invention is therefore to be regarded as including all possible modifications and changes as defined by the appended claims.