JPS6218991B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using an insulated gate field effect transistor.

There is a conventional memory circuit as shown in FIG. Here, Clm(l=1~l, m=1~
m) is a memory cell, Xl (l = 1 to l) is the output of the row (ROW) side selection decoder, and Ym (m = 1 to
m) is the output of the column (COLUMN) side selection decoder,
Dm, (m=1~m) is a digit line, RB,
is a data bus, A is an amplification circuit, and φ _B is an internal signal generated from a memory external drive signal (here, chip select signal CS).

FIG. 2 shows the operation timing of this memory circuit.

In FIG. 2, CS is a signal that is activated at a low (LOW) level and inactivated at a high (HIGH) level, indicating the operation timing at the time of reading. The example circuit shown in FIG. 1 has the following drawbacks. When the data bus RB is inactive, the potential of the data bus RB is at a level one step below the threshold voltage of the transistors Q ₁₀ and Q ₁₁ than the power supply.
Q ₁₀ and Q ₁₁ are almost in the cut-off state. In this state, if noise opposite to the information that should originally be transmitted occurs on the data bus RB before period _T1 ,
Due to the noise, the output D _OUT of the amplifier A is significantly tilted to a potential opposite to that of the original information. Even if the original information is transmitted to the data bus RB during period _T1 in this state, the output of the amplifier A is the opposite information, so it is necessary to move from that potential to the potential of the original information. It takes more time than if there was no noise, and the speed is delayed. This situation is shown in FIG. Here, ΔT is the speed delay. In Figure 1, when noise occurs on data bus RB, transistors Q ₁₀ and Q ₁₁ are almost in a cut-off state, so the time constant for bringing both nodes of data bus RB toward the same potential is extremely large. .
Furthermore, there is no suppressing effect on noise that would further raise the potential of the data bus RB when it is inactive. An object of the present invention is to provide a memory circuit that does not malfunction due to noise.

A memory circuit according to the present invention includes a data bus line pair, first and second voltage sources, a pair of load transistors connected between the first voltage source and each younger line of the data bus line pair, and the second voltage source. a pair of control transistors connected between the voltage source and each line of the pair of data bus lines, the control transistors being turned on at least during a period before read data is applied to the data bus line; The present invention is characterized in that the load transistor is operated in a non-saturation region. Furthermore, in the present invention, an equalizer transistor may be provided between each line of the data bus line pair, and this may be driven by a delayed signal of an external signal.

According to one aspect of the present invention, in a data bus of a memory circuit using MOSFETs, the output of the first inverter is connected to the data bus on the in-phase side N, and the output of the second inverter is connected to the data bus on the anti-phase side. The load transistor and drive transistor of each inverter are made conductive, and the gate electrode of the MOSFET that equalizes the in-phase and anti-phase data buses is equipped with a memory circuit that inputs an equalization signal from an external drive signal via a delay circuit. can get. Further, in such a configuration, a memory is configured to input a control signal to the gate electrode of one or both of the load transistor and drive transistor of the first and second inverters to make the load and drive transistor of the inverter conductive only during a required period. You can also get a circuit.

Next, FIGS. 4 and 5 show reference examples of the present invention.

As shown in FIG. 4, there is a transistor _Q13 whose drain and gate are connected to the data bus line RB and whose source is grounded, and a transistor _Q14 whose drain and gate are connected to the data bus line and whose source is grounded. is provided. transistor
Q ₁₃ constitutes a ratio circuit with a load transistor Q ₁₀ and an inverter circuit configuration. transistor
_Q14 also constitutes a ratio circuit like the load transistor _Q11 . In addition, a transistor is inserted between the bus lines.
Q ₁₂ is provided, and a signal φ _B obtained from an external drive signal via a buffer 10 and a delay circuit 11 is applied to its gate. With this configuration, the potential of RB becomes lower than the potential of one threshold voltage step below the power supply, and Q ₁₀ ,
The transistors Q ₁₁ , Q ₁₃ and Q ₁₄ are not in the cut-off state, and even if noise occurs on the data bus line, the transistors are conductive, so when the voltage reaches the potential determined by the inverter ratio. The constant is small and has a large effect in directing both nodes of the bus line RB to the same potential. Furthermore, since the potential of the bus line RB is lower than that of the conventional circuit example, the effect of equalizing the potential of the transistor _Q12 by _φB is large, and a sufficient effect can be achieved without making the threshold voltage of the transistor _Q12 negative. can get.
As described above, in the present invention, even if noise occurs on the bus line RB, the effect of equalizing and removing the noise is large, and the output of the amplifier A is not directed to a potential opposite to the original information, but the time When the original information is transmitted to RB at _T1 , the information is transmitted to the output of amplifier A without delay.

FIG. 6 shows an embodiment of the present invention.

In this example, the basic operation is the same as that in FIG. 4, but a control signal is input to the gate terminals of transistors Q ₁₃ and Q ₁₄ to reduce power consumption. The operation is as follows. bus line
During the period of noise generation to RB, the clock φ _B ,
By keeping φ _p at a high level and making transistors Q ₁₃ and Q ₁₄ conductive, the same effect as in the reference example of FIG. 4 is obtained.
When the noise generation ends, φ _B and φ _p are set to a low potential (this time is adjusted by the delay circuits 11 and 11 in Figure 6).
Do it at 12. ) Transistors Q ₁₃ and Q ₁₄ are made non-conductive to reduce power consumption.

Thus, the present invention provides a memory circuit that eliminates noise generated on the data bus and does not slow down the speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional memory circuit, FIG. 2 is an operation timing diagram for explaining the circuit of FIG. 1, and FIG. 3 is an operation timing diagram when noise occurs in the conventional circuit example. FIG. 4 is a diagram showing a reference example of the present invention, FIG. 5 is an operation timing diagram for explaining the circuit of FIG. 4, and FIG. 6 is a diagram showing an embodiment of the present invention. C11~Clm...Memory cell, D1, D1~
Dm~...digit line, RB,...data bus line.

Claims (1)

[Claims] 1. A data bus line pair connected to a plurality of digit line pairs via gate means, a first and a second voltage source, and a pair each connected between the first voltage source and the data bus line pair. a load transistor, and a pair of control transistors respectively connected between the second voltage source and the pair of bus lines; A memory circuit characterized in that the control transistor is generated and a control signal is supplied to the gate of the control transistor to make it conductive.