JPS6221283B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an FM detection circuit, and particularly to a quadrature detection circuit.
Regarding FM detection circuit.

There are various types of FM detectors, but quadrature detectors are widely used because they are suitable for IC implementation and have good cost performance. Such a quadrature detector is a product detection method consisting of a so-called double-balanced differential amplifier circuit, and the product (multiplication) output of the double-balanced differential amplifier is amplified by a predetermined so-called post-amplifier, and then sent to a low-pass filter. Guided and configured.

Since it is this product detection stage and the post-amplifier stage that amplifies its output that determine most of the S/N and distortion rate, which are the basic performance of an FM tuner as an audio device, the S/N ratio in these circuits is Improvements in /N and distortion are desired.

On the other hand, the output of the post amplifier becomes a predetermined reference voltage when it is optimally tuned, and when it is detuned, a voltage that deviates from the reference voltage in proportion to the deviation is generated, and this output is used to drive the tuning meter. The configuration is as follows. In this case, the reference voltage is applied to the other end of the tuning meter, and the pointer of the tuning meter swings left and right in proportion to the potential difference between this reference voltage and the output voltage of the post amplifier, and when the tuning meter is optimally tuned, the meter pointer swings left and right. Both terminal voltages serve as a reference voltage, and the pointer points to the center, indicating the optimum tuning state.

Therefore, the DC voltage at the output point of the post amplifier is
It must be chosen equal to the reference voltage applied to the other end of the tuning meter.

The present invention has been made in view of the above-mentioned points, and is a circuit suitable for driving a tuning meter by improving the S/N and distortion ratio and selecting a desired DC voltage at the output point of a post amplifier. has a configuration
The purpose of the present invention is to provide an FM detection circuit.

Hereinafter, the present invention will be explained using the drawings.

The figure shows an FM detection circuit showing an embodiment of the present invention. Reference numeral 1 indicates a double-balanced differential amplifier circuit section, and a product (multiplying) detection section is shown. A first differential circuit having first and second transistors Q ₁ and Q ₂ to which an amplitude-limited intermediate frequency FM modulation signal (IF), that is, a test wave signal is applied between the bases, is provided. , the emitters of both transistors are commonly connected to a constant current source _I0 .

The collector of the first transistor Q ₁ is connected to the emitters of the third transistor Q ₃ and the fourth transistor Q ₄ via emitter resistors R ₁ and R ₂ , respectively, and the collector of the second transistor Q ₂ is connected to the emitters of the third transistor Q 3 and the fourth transistor Q 4, respectively. The fifth transistor _Q5 and the sixth transistor _Q6 are connected via emitter resistors _R3 and _R4 , respectively. Fourth and sixth transistors Q ₄ , Q ₆
Both bases of transistor _Q8 are connected in common
A predetermined reference base bias is applied by the emitter. Therefore, the emitter of the transistor is grounded via the resistor _R8 , its collector is connected to the power supply Vcc, and the reference voltage Vγ is applied to its base.

On the other hand, the bases of the third and fifth transistors Q ₃ and Q ₅ are commonly connected, and the output signal of the phase shifter 2 is applied via the emitter follower transistor Q ₇ . The resistor _R7 becomes the emitter load resistance of the emitter follower transistor _Q7 . The positive phase output of the differential amplifier 3 that amplifies the IF signal is applied to the input of the phase shifter 2, and the output is a signal delayed by 90 degrees with respect to the center frequency of the IF signal, ₀ = 10.7MHz. , and the phase is linearly changed in proportion to the change with respect to the center frequency ₀ and is output.

Then, the third and sixth transistors Q ₃ and Q ₆
The collectors of the transistors Q 4 and Q ₅ are connected to the power source through a load resistor R 5 , and the collectors of the fourth and fifth transistors Q ₄ and Q ₅ are connected to the power source through a load resistor R ₆ . A product signal output of the IF signal and the output signal of the phase shifter 2 is derived between the common collector connection point of the transistors Q ₃ and _{Q 6} and the common collector connection point of the transistors Q 4 and Q ₅ .

The product signal output is input to the post-amplifier section 4 at the next stage. This post amplifier 4 has a configuration as shown in the figure. That is, it has a differential amplifier configuration in which PNP transistors Q ₉ and Q ₁₀ are differential transistors, and the above product output is applied between the bases of both transistors. The emitters of both transistors are commonly connected to a current source consisting of PNP transistors Q ₁₁ to Q ₁₃ and resistors R ₉ , R ₁₀ and R ₁₄ . Also, the collector
It is connected to an active load of a current mirror circuit configuration consisting of NPN transistors Q ₁₄ and Q ₁₅ , and the collector output of transistor Q ₉ is applied to the base of output transistor Q ₁₆ . Output transistor Q ₁₆
The emitter of is grounded and the amplified output is taken out from the collector. In addition, resistor R ₁₁ and PNP transistor
_Q17 constitutes a current source together with the aforementioned PNP transistors _Q11 , _Q12, etc., and serves as an active load for the output transistor _Q16 . The output terminal OUT and the base (negative phase input) of the differential transistor _Q10 are connected to the feedback resistor _R13.
is connected and negative feedback is applied to reduce the distortion rate and S/N.
Improvements are being made. Further, the base (positive phase input) of the transistor _Q9 is connected to the reference voltage _Vγ via a resistor R12. In addition, the output transistor
The collector-base capacitance C ₁ of Q ₁₆ is a capacitance for phase compensation.

In order to better understand the characteristics of the circuit shown in FIG. 1, a block diagram is shown in FIG. 2, and equivalent parts are designated by the same reference numerals in both figures. As shown,
A pair of positive and negative phase signals, which are product outputs, are outputted via load resistors R ₅ and R ₆ and applied to the non-inverting and inverting inputs of the operational amplifier 4, respectively. A resistor _R13 is connected between the output of this amplifier 4 and the inverting input.
is provided to apply negative voltage feedback. Further, a resistor R ₁₂ is connected between the non-inverting input and the reference voltage Vγ, and this reference voltage Vγ is also used as the operating voltage of the product circuit 1. Furthermore, the reference voltage Vγ is applied to the other end of a tuning meter (not shown), and the output of the operational amplifier 4 is
OUT becomes an FM detection signal and is input to an MPX demodulation circuit (not shown) and is also applied to one input terminal of a tuning meter.

In this configuration, since the detection operation of the product circuit 1 is well known, a description of its operating principle will be omitted.

In the present invention, since an operational amplifier is used as a post-amplifier and negative voltage feedback is applied to the amplifier, the S/N and distortion ratio are improved, and the load resistance _R5 and the voltage application resistor _R12 are The ratio (R ₅ /R ₁₂ ) is selected to be equal to the ratio (R ₆ /R ₁₃ ) of the load resistance R ₆ and the negative feedback resistance R ₁₃ , e.g.
R ₅ = R ₆ = 3KΩ, R ₁₂ = R ₁₃ = 5.6KΩ. As a result, at optimal tuning, the product detection section 1
Since the magnitudes of the positive and negative phase outputs are equal to each other, the DC voltage of the output OUT of the operational amplifier 4 is the reference voltage V
is equal to γ. Therefore, at the time of detuning, the output voltage of the operational amplifier 4 changes around the reference voltage, so the circuit configuration is suitable for driving a tuning meter.

Furthermore, in the post amplifier, by using a PNP configuration for the differential transistors as shown in Figure 1, it is possible to suppress leakage of the IF carrier signal caused by the switching operation of the differential transistors in the product detection section 1. . This is because the IF carrier is 10.7MHz, and the PNP transistor is at its _T (cutoff frequency) in the IC configuration.
Since it is approximately 10MHz, it is clear that a carrier suppression effect can be expected.

Note that resistors R ₁ to R ₄ are inserted into the emitters of the differential transistors Q ₃ to _{Q 6} constituting the second and third differential circuits of the product detection stage 1, respectively. It has been found that by inserting these emitter resistors, the S/N can be improved by approximately 3 _dB compared to a conventional circuit without such emitter resistors. For example, if the emitter resistances _R1 to _R4 are selected to be 100Ω, the S/N of _88dB in the conventional circuit _{is 91dB.}
It has been confirmed through experiments that this can be improved.

These emitter resistance values are approximately 50Ω to 200Ω.
Values in the range of Ω are effective; values smaller than 50Ω are equivalent to conventional circuit configurations and no improvement in S/N can be seen, and values larger than 200Ω prevent the differential transistor from performing switching operation and the product detection function is disabled. This is not appropriate as this will result in the loss of the actual item. Of course, the product detection circuit 1 is not limited to the circuit configuration shown in the figure and can have various configurations, but if a circuit with an emitter resistor inserted as in this example is used, it is possible to improve the S/N, so the subsequent stage By using it together with a feedback type operational amplifier, the improvement in the characteristics of the FM detection circuit becomes more noticeable.

As described above, the present invention has the advantage that it is possible to improve the S/N ratio and the distortion rate, and the structure is suitable for driving a tuning meter.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit block diagram of FIG. 1. Explanation of symbols of main parts, 1...Product detector, 4...Post amplifier, Vγ...Reference voltage,
R ₅ , R ₆ ...Load resistance, R ₁₃ ...Feedback resistance, R ₁₂ ...
...Resistance for voltage application.

Claims (1)

[Claims] 1. A device having a positive phase output terminal and a negative phase output terminal, the positive phase output terminal being connected to the power supply via a first load resistor, and the negative phase output terminal being connected to the power supply via a second load resistor. a double-balanced differential amplification amplifier connected to the FM modulation signal and a phase difference signal having a phase difference of approximately 90° with respect to the FM modulation signal to obtain a positive and negative phase output of the multiplied signal; an operational amplifier in which a positive-phase output of a double-balanced differential amplifier is applied to a non-inverting input and a negative-phase output is applied to an inverting input; and a feedback resistor provided between the output and the inverting input of the operational amplifier. , a voltage applying resistor provided between the non-inverting input of the operational amplifier and the generation output of a predetermined reference voltage, the ratio of the first load resistor to the voltage applying resistor being equal to the second load resistor. and the feedback resistor.
FM detection circuit. 2. The circuit according to claim 1, wherein the operational amplifier is an integrated circuit, and the active element for amplification is a PNP transistor. 3. The double-balanced differential amplifier includes a first differential circuit having first and second transistors whose emitters are commonly connected, and a first differential circuit to which the FM modulation signal is applied between the bases of both transistors; a second differential circuit including third and fourth transistors connected to the collector of the first transistor through a resistor, and the phase difference signal is applied between the bases of both transistors; and the emitter thereof each has a resistor. a third differential circuit including fifth and sixth transistors connected to the collector of the second transistor through the third differential circuit, and the phase difference signal is applied between the bases of the transistors;
2. The circuit according to claim 1, wherein the collector of the sixth transistor constitutes the positive phase output terminal, and the collectors of the fourth and fifth transistors constitute the negative phase output terminal.