JPS6225274B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a memory cell of a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32K bits and 64K bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
(referred to as ROM), one memory cell consists of at least two transistors, so the degree of integration cannot be increased very high, and so far only 16K bits of integration have been announced.
However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure, 1 is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point is a MOS transistor 4 for bit selection.
and a double gate type MOS transistor 5 having a control gate and a floating gate for data storage are connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2, and the control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

An object of the present invention is to provide a semiconductor memory device that can eliminate the above-mentioned drawbacks.

An embodiment of the present invention will be described below with reference to the drawings. 2a to 2b show the configuration of 4 bits of memory cells of a semiconductor memory device according to the present invention, FIG. 2a is a pattern plan view, and FIG. 2b is a pattern plan view.
is a structural cross-sectional view taken along line -' in figure a, Figure 2 c is a structural cross-sectional view taken along line -' in figure a, and
Figure d is a structural sectional view taken along the line -' in figure a.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon. On the surface of this substrate 11, gate insulating films 12a, 12b, 12c, and 12d are arranged at regular intervals in an XY matrix.
Further, on the surface of the substrate 11, there are, for example, gate insulating films 12a at two locations adjacent to each other in the vertical direction in the figure.
and 12c, 12b and 12d as a pair, and field insulating films 13, 13' are formed between each pair of gate insulating films.
are formed separately. Moreover, on the plurality of field insulating films 13 adjacent to each other in the vertical direction in the figure,
The first layer is made of polysilicon containing P or _As .
The conductor layers 14 are formed continuously.
Furthermore, each of the gate insulating films 12a, 12b, 12
Second conductive layers 15a, 15b, 15c, and 15d made of polysilicon are formed on the conductor layers 15a, 15b, 15c, and 15d separately from each other. Two second conductor layers 15a and 15 are located on the left side of the first conductor layer 14 in the figure.
Each right end portion of c is connected to the first
It overlaps with the left end of the conductor layer 14 of the second layer. Further, the left end portions of the two second conductive layers 15b and 15d located on the right side with respect to the conductive layer 14 are connected to the right end portions of the conductive layer 14 via the insulating film 16. It overlaps with Furthermore, the second conductor layer 1 adjacent to each other in the left and right direction in the figure
5a and 15b, an insulating film 1 is formed to cover them.
7, a third layer made of polysilicon is set to have approximately the same width as both conductor layers 15a and 15b.
The second conductive layer 18A is formed, and similarly, on the second conductive layer 15c and 15d adjacent in the left and right direction in the figure, so as to cover this,
Through the insulating film 17, both conductor layers 15
Another third conductive layer 18B made of polysilicon and set to approximately the same width as c and 15d.
is formed. Furthermore, an N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between two gate insulating films 12a and 12c that are vertically adjacent in the figure, and similarly, two gate insulating films 12a and 12c are formed on the surface of the substrate 11. An N ⁺ type semiconductor layer 19B is formed in the surface region of the substrate 11 between the films 12b and 12d. Furthermore, each gate insulating film 12a, 12b, 12
c, 12d, the above N ⁺ type semiconductor layer 19A
Alternatively, a continuous N ⁺ type semiconductor layer 19C is formed in the surface region of the substrate 11 on the opposite side from the side where 19B is formed. Further, the third conductive layer 18
On A and 18B, fourth conductor layers 21A and 21B made of Al are formed with an insulating film 20 interposed between them, and one conductor layer 21A and the
The contact portion 22A is connected to the N ⁺ type semiconductor layer 19A.
The other conductor layer 21B and the
It is connected to the N ⁺ type semiconductor layer 19B by another contact portion 22B. and said
The N ⁺ type semiconductor layer 19C is connected to a reference potential point, for example, a ground potential point. Further, the thickness of the insulating film existing between the first conductor layer 14 and the N ⁺ type semiconductor layer 19C, which is formed in a region other than on the field insulating film 13, is at least as thick as that of the gate insulating film 12. It is also set thick.

In addition, in FIG. 2a, the area surrounded by broken lines with the symbol ABCD is 1 of this semiconductor memory device.
As is clear from FIG. 2b, this memory cell has a second conductive layer 15 with a floating gate.
It is composed of a MOS transistor in which the third conductor layer 18 is a control gate and the first conductor layer 14 is an erase gate, and further includes a 2-bit transistor as shown in FIG. 2b. In terms of details, the control gate and the erase gate are common, and are composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductor layers 21A and 21B, and 33 and 34 are the first conductor layers 1.
4 is an erase line formed by being extended, and 35 and 36 are selection lines formed by extending the third conductor layers 18A and 18B. Further, M1 to M4 are memory cells, and each memory cell is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S, and the drain D of the memory cells M1 and M2 is connected to one of the digit lines. 31, memory cells M3, M
The drain D of memory cell 4 is connected to the other digit line 32, and the sources S of all memory cells are connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now paying attention to memory cell M1 in FIG. 3, in the initial state the floating gate of this memory cell M1 is
No electrons are injected into FG, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and these hot electrons are injected into the floating gate FG from between the source and the drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. When writing data, the erase line 33 may be applied with a pulse of a high voltage, for example, +20 volts, or may be applied with a DC voltage of +5 volts or 0 volts, or may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
A high level signal (+
5 volts) is applied. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on and one digit line 3 is turned on.
A current flows from memory cell M1 toward the ground potential point. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time,
A state in which current flows through memory cell M1 is a logic "1" level, and a state in which no current flows is a logic "0" level.
level, this device can be used as a storage device. Also floating gate
As mentioned above, the FG is surrounded by an insulating film and is isolated from others, so
Once the electrons are injected here, they cannot escape under normal usage conditions, so it can be used as a non-volatile data storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is leaked to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to a low state similar to the cut-off state.

Note that when data is erased, since a high voltage is applied to the erase line 33, the portion of the first conductive layer 1 formed in the area other than on the field insulating film 13 is
4 and the N ⁺ type semiconductor layer 1 formed below it.
9C, but as mentioned above, the thickness of the insulating film between them is set to be at least thicker than the gate insulating film 12, so this leakage is definitely prevented. It can be prevented.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP--
It is possible to realize a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. That is, +20 volts when writing and +20 volts when erasing.
When reading 40 volts, you only need a +5 volt positive power supply, and if you use a booster circuit to obtain +20 volts and +40 volts from the +5 volt voltage, you can use only one +5 volt power supply. can. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 is shown in FIG.
This will be explained using the pattern plan views shown in FIGS. First, Figure 4a and Figure 5a
As shown in FIG. 2, field insulating films 13 and 13' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography.
Furthermore, P or _As is diffused into the shaded area in FIG. 4a by implantation or diffusion to form an N-type semiconductor layer 19C'. After the completion of the above diffusion, the above field insulating film 1
After exposing the surface of the substrate 11 in areas other than the forming areas 3 and 13', a thermal oxidation film having a relatively thin film thickness of 1000 to 2000 Å for forming the gate insulating film 12 is formed here using a thermal oxidation method. form 23. Next, polysilicon with a thickness of 6000 Å is grown on the entire substrate 11, and after doping it with P or _As , a first layer is formed in the solid line area in FIG. 4b by photolithography.
A second conductor layer 14 is formed. Here, an example is shown in which the first conductive layer 14 is not formed on the adjacent field insulating films 13'.
This may be formed as required. Next, after forming the first conductor layer, as shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500 Å is grown by thermal oxidation, and then hand
A polysilicon film with a thickness of 5000 Å was grown by the CVD method, and a second conductor layer 15a as a floating gate was grown by photolithography.
15b, 15c, and 15d are formed. Here the fifth
As is clear from the figure, in FIG. An example is shown in which at least a portion thereof overlaps with the conductor layer 14. Regarding the other ends of the conductor layers 15a and 15b, the conductor layer 1
It does not overlap with 4. After forming the floating gate, as shown in FIGS. 4d and 5d,
Insulating film 1 with a thickness of 1000 to 2000 Å by thermal oxidation method
7 is formed, polysilicon is deposited thereon, and a photolithography method is applied thereto to form third conductor layers 18A and 18B which will serve as control gates, and at the same time, a second conductor layer is formed. layers 15a, 15b,
15c and 15d are formed by self-alignment. Next, P or _As is diffused into the shaded area in ^FIG .
B, 19C is formed. Further, as shown in FIGS. 4e and 5e, an insulating film 20 is formed over the entire substrate 11.
and an Al film are successively deposited, and a photolithography method is applied to this Al film to form a fourth conductor layer 21A,
21B and the contact portion 21
A and 22B form the N ⁺ type semiconductor layer 19A,
This semiconductor memory device is completed by connecting each of 19B.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, only each right end portion or each left end portion of the second conductive layer 15 is at least a portion of the first conductive layer 14. Although a case has been described in which the conductor layer 15 overlaps with the conductor layer 15, it may be configured such that the conductor layer 15 overlaps at both ends thereof. Further, although the first conductive layer 14 and the second conductive layer 15 are both made of polysilicon, molybdenum may be used instead.

As explained above, the semiconductor memory device of the present invention can consist of one memory cell with one transistor, and data can be electrically erased, so it is extremely useful when adopted for E ² P-ROM. You can get many effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, and FIGS. 2 a to 2 d show a semiconductor memory device according to the present invention.
is a pattern plan view, and Fig. 2 b is a -' of the same Fig. 2 a.
A cross-sectional view of the structure along the line, Figure 2c is the same as that shown in Figure 2a.
2d is a structural sectional view taken along the line -' in Figure 2a, Figure 3 is an equivalent circuit diagram of the device shown in Figure 2, Figures 4a to 5e and 5 Figures a to e are for explaining an example of a manufacturing method for manufacturing the device shown in Figure 2 above, and Figures a to e are pattern plan views,
Figure 5 a to e are each of Figure 4 a to e.
FIG. 11... Semiconductor substrate, 12... Gate insulating film,
13...Field insulating film, 14...First conductor layer (erase gate), 15...Second conductor layer (floating gate), 16,1
7, 20... Insulating film, 18... Third conductor layer (control gate), 19... N ⁺ type semiconductor layer, 21... Fourth conductor layer, 22... Contact portion , 23... thermal oxide film, 31, 32...
Digit line, 33, 34... Erasing line, 35, 3
6... Selection line, M1, M2, M3, M4... Memory cell, CG... Control gate, FG... Floating gate, EG... Erase gate, D
...Drain, S...Source.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a pair of gate insulating films formed on the substrate at regular intervals, a field insulating film formed between the pair of gate insulating films, and a field insulating film formed between the gate insulating films. a first conductive layer extending in a direction crossing the arrangement direction and formed on the field insulating film; a second conductor layer overlapping at least a portion of the body layer; and a third conductor layer formed to cover the second conductor layer and insulated from the first conductor layer and the second conductor layer. a conductive layer; an insulating film formed between the first conductive layer and the base body located in a region other than on the field insulating film, the film thickness of which is set to be at least thicker than the gate insulating film; A semiconductor memory device characterized by comprising: