JPS6226595B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a memory cell of a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32K bits and 64K bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
(referred to as ROM), one memory cell consists of at least two transistors, so the degree of integration cannot be increased very high, and so far only 16K bits of integration have been announced.
However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure, 1 is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point is a MOS transistor 4 for bit selection.
and a double gate type MOS transistor 5 having a control gate and a floating gate for data storage are connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2, and the control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

An object of the present invention is to provide a semiconductor memory device that can eliminate the above-mentioned drawbacks.

An embodiment of the present invention will be described below with reference to the drawings. 2a to 2c show the structure of a semiconductor memory device according to the present invention, in which FIG. 2a is a pattern plan view, FIG. 2b is a structural sectional view taken along the line -' of FIG. FIG. 2c is a structural sectional view taken along the line -' in FIG. 2a.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon, and on the surface of this substrate 11, gate insulating films 12a to 12f are arranged at regular intervals in an XY matrix. Furthermore, the substrate 1
1, there are gate insulating films 12a and 12d, 12b and 12e, which are adjacent to each other in the vertical direction in the figure.
12c and 12f form a pair, and field insulating films 13 and 13' are formed between the pair of gate insulating films. In addition, the field insulating film 1 at the one location above
A first conductor layer 14 made of polysilicon containing P or As is formed on the conductor layer 3 . Furthermore, second conductor layers 15a to 15f made of polysilicon are formed separately from each other on each of the gate insulating films 12a to 12f. The right end portions of the two second conductive layers 15b and 15e located on the left side with respect to the first conductive layer 14 in the figure are connected to the insulating film 1.
It overlaps with the left end portion of the first conductive layer 14 via the conductor layer 6 . Further, the left end portions of the two second conductive layers 15c and 15f located on the right side with respect to the conductive layer 14 are connected to the insulating film 1.
The right end portion of the conductor layer 14 is overlapped with the conductor layer 14 via the conductor layer 6 . Furthermore, on the second conductor layers 15a, 15b, 15c adjacent to each other in the left and right direction in the figure, each of these conductor layers 15a, 15b, 15c is placed through an insulating film 17 so as to cover the second conductor layers 15a, 15b, 15c. A third conductive layer 18A made of polysilicon having approximately the same width is formed, and a second conductive layer 1 adjacent to the third conductive layer 18A in the horizontal direction in the figure is formed.
5d, 15e, and 15f, each of these conductor layers 15 is placed through the insulating film 17 so as to cover them.
Another third conductor layer 18B made of polysilicon is formed and has approximately the same width as d, 15e, and 15f. Furthermore, an N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between two gate insulating films 12a and 12d that are vertically adjacent to each other in the figure, and two gate insulating films 12b and 12e are formed on the surface of the substrate 11. An N ⁺ type semiconductor layer 19B is formed in the surface area of the substrate 11 between the two gate insulating films 12c and 12e, and an N ⁺ type semiconductor layer 19C is formed in the surface area of the substrate 11 between the two gate insulating films 12c and 12e. ing. Further, for each gate insulating film 12a to 12e, the N ⁺ type semiconductor layers 19A, 19B, 19C
A continuous N ⁺ type semiconductor layer 19D is formed in the surface region of the substrate 11 on the side opposite to the formation side.
Further, on the third conductor layers 18A and 18B, a wiring layer 21 made of Al is provided with an insulating film 20 interposed therebetween.
A, 21B, 21C, 21D are formed,
One of the wiring layers 21A and the N ⁺ type semiconductor layer 19A are connected through a contact hole 22A, the wiring layer 21B and the N ⁺ type semiconductor layer 19B are connected through a contact hole 22B, and the wiring layer 21C and the first conductor layer 14 are connected through a contact hole 22C, and the wiring layer 21D and the N ⁺ type semiconductor layer 19C are connected through a contact hole 22D. The N ⁺ type semiconductor layer 19D is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 2a, the area surrounded by broken lines with the symbol ABCD is 1 of this semiconductor memory device.
This memory cell has a second conductor layer 15 as a floating gate, a third conductor layer 18 as a control gate, and a first layer as a control gate. The eye conductor layer 14 is used as an erase gate, the N ⁺ type semiconductor layer 19B is used as a drain, and the N ⁺ type semiconductor layer 19D is used as an erase gate.
Furthermore, when looking at the two bits shown in Figure 2b, the control gate and erase gate are each common, and the control gate and erase gate are composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. It is configured. The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is.
Furthermore, since the erase gate is formed on the field insulating film 13, the overlapping portion of each floating gate and erase gate exists within the field region. Furthermore, the second
As shown in FIG. b, in the overlapping portion, the second conductive layer 15, that is, the floating gate is located above the first conductive layer 14, that is, the erase gate, and the substrate 11 is located above the first conductive layer 14, that is, the erase gate. The distance between the substrate 11 and the conductive layer 14 is shorter than the distance between the substrate 11 and the conductive layer 15. Further, as is clear from FIG. 2a, the first conductor layer 14 is provided at only one location for a 4-bit memory cell, and each conductor layer 14 at each location is provided at one contact point. The wiring layer 2 is connected to the hole 22C.
Connected to 1C.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, digit lines 31 and 32 are composed of the wiring layers 21B and 21D;
3 and 34 are erase lines formed by the wiring layer 21C connected to the first conductor layer 14;
5 and 36 are the third conductor layers 18A and 18
B is a selection line formed by being extended. Also M
1 to M4 are memory cells, and each memory cell has a control gate CG and a floating gate.
It is composed of an FG, an erase gate EG, a drain D, and a source S. The drains D of the memory cells M1 and M2 are connected to one of the digit lines 31, the drains D of the memory cells M3 and M4 are connected to the other digit line 32, and all Source S of the memory cell of
are respectively connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now paying attention to memory cell M1 in FIG. 3, in the initial state the floating gate of this memory cell M1 is
No electrons are injected into FG, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and the hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. When writing data, the erase line 33 may be applied with a pulse of a high voltage, for example, +20 volts, or may be applied with a DC voltage of +5 volts or 0 volts, or may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
A high level signal (+
5 volts) is applied. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on and one digit line 3 is turned on.
A current flows from M1 to the ground potential point through memory cell M1. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time,
A state in which current flows through memory cell M1 is a logic "1" level, and a state in which no current flows is a logic "0" level.
level, this device can be used as a storage device. Also floating gate
As mentioned above, the FG is surrounded by an insulating film and is isolated from others, so
Once the electrons are injected here, they cannot escape under normal usage conditions, so it can be used as a non-volatile data storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is leaked to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to a low state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP--
It is possible to realize a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. That is, +20 volts when writing and +20 volts when erasing.
When reading 40 volts, you only need a +5 volt positive power supply, and if you obtain +20 volts and +40 volts from the +5 volt voltage via a booster circuit, you can use only one +5 volt power supply. You can also do it. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Erase gate (first conductor layer 14)
Since the wiring is formed using the wiring layer 21C made of Al instead of wiring using polysilicon that constitutes the substrate, the thickness of the insulating film between the erasing line and the substrate can be reduced. It can be made relatively thick, so even if a high voltage is applied to the erase line, leakage will not occur.

One contact hole connects the erase gate and the wiring layer 21C for every four bits of the memory cell.
Since the number of contacts per bit is 1/4, it is possible to provide a high degree of integration.

Since hot electron injection is used when writing data and field emission is used when erasing data, a relatively thick insulating film can be used around the floating gate, resulting in good non-volatile characteristics, that is, data retention characteristics.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 is shown in FIG.
This will be explained using the pattern plan views shown in FIGS. First, Figure 4a and Figure 5a
As shown in FIG. 1, field insulating films 13 and 13' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 11 made of P-type silicon by photolithography. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 11, and after doping it with P or As, the above-mentioned one field is formed by photolithography as shown by the solid line in Figure 4b. Insulating film 1
3, a first conductor layer 14 is formed. Here, an example is shown in which the conductor layer 14 is not formed on the adjacent field insulating films 13'.
This may be formed as required. Next, after forming the first conductive layer 14, as shown in FIG. 4c and FIG. ~
12f and an insulating film 16 are formed, and then polysilicon is grown to a thickness of 5000 Å using the CVD method, and then a second layer conductor as a floating gate is formed using a photolithography method. layer 15a
Forms ~15f. As is clear from the figure, in FIG. An example is shown in which the first conductive layer 14 at least partially overlaps. And conductor layers 15b, 15
The other end of c does not overlap with the conductor layer 14. After forming the floating gate, as shown in FIGS. 4d and 5d, an insulating film 17 with a thickness of 1000 Å to 2000 Å is formed by thermal oxidation.
Polysilicon is deposited thereon, and a photolithographic method is applied thereto to form third conductor layers 18A and 18B which will become control gates, and at the same time, second conductor layers 15a to 15f are formed. is formed by self-alignment. Next, P or As is diffused into the shaded region in FIG. 4e to form N ⁺ -type semiconductor layers 19A, 19B, and 19C, which will become drains, and N ⁺ -type semiconductor layer 19D, which will serve as sources, respectively. Furthermore, as shown in FIG. 4e and FIG. 5e, an insulating film 20 and an Al film are successively deposited over the entire substrate 11, and a photolithography method is applied to this Al film to form wiring layers 21A, 21B. , 21C, 21D
form. At this time, contact holes 22A, 22B, 22C, and 22D are opened in advance, and N ⁺ type semiconductor layers 19A, 19B,
This semiconductor memory device is completed by connecting the first conductor layer 14 and the wiring layer 21C through the contact holes 22C and the wiring layers 21A, 21B, and 21D.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, only each right end portion or each left end portion of the second conductive layer 15 is at least a portion of the first conductive layer 14. Although the case where the conductor layer 15 overlaps with the conductor layer 14 has been described, the structure may be such that both ends of the conductor layer 15 overlap the conductor layer 14.

As explained above, the semiconductor memory device of the present invention can consist of one memory cell with one transistor, and data can be electrically erased, so it is extremely useful when adopted for E ² P-ROM. You can get many effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, and FIGS. 2a to 2c show a semiconductor memory device according to the present invention.
is a pattern plan view, and Fig. 2 b is a -' of the same Fig. 2 a.
A cross-sectional view of the structure along the line, Figure 2c is the same as that shown in Figure 2a.
Fig. 3 is an equivalent circuit diagram of the device shown in Fig. 2, Fig. 4 a to e, and Fig. 5
Figures a to e are for explaining an example of the manufacturing method for manufacturing the device shown in Figure 2, respectively; Figures 4 a to e are pattern plan views, and Figures 5 a to e are pattern plan views. Each of figures a to e -'
It is a sectional view along a line. 11... Semiconductor substrate, 12... Gate insulating film, 13
...Field insulating film, 14...First conductor layer (erase gate), 15...Second conductor layer (floating gate), 16, 17, 20...Insulating film, 18...Third layer Eye conductor layer (control gate), 19...N ⁺ type semiconductor layer, 21... wiring layer,
22... Contact hole, 31, 32... Digit line, 33, 34... Erase line, 35, 36... Selection line, M1, M2, M3, M4... Memory cell, CG
...control gate, FG...floating gate, EG...erase gate, D...drain, S...source.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate, a control gate provided on the substrate via an insulating film, and an erase gate provided in the insulating film sandwiched between the control gate and the substrate; A floating gate is provided in the insulating film in parallel with the erase gate, and an end portion of the floating gate overlaps at least a portion of the erase gate via the insulating film in the field region, and a source and a drain. When writing, a predetermined voltage is applied between the source and drain, and a voltage of the same polarity is applied to the control gate and erase gate. When erasing data, the source, drain, and control gate are set to approximately the same potential, and data is written to the erase gate. 1. A semiconductor device characterized in that a voltage of the same polarity as time is applied. 2 When erasing the data, the source, the drain, and the control gate are set to approximately the same potential, and a voltage is applied to the erase gate with the same polarity as when writing data and higher than the voltage applied when writing data. A semiconductor memory device according to claim 1.