JPS6230695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a test device for semiconductor devices for continuously testing the electrical characteristics of semiconductor devices. [Technical Background of the Invention] In semiconductor devices, such as ICs (semiconductor integrated circuit devices), it is necessary to test the electrical characteristics of each manufactured product to distinguish between good and defective products. In order to continuously and automatically perform the above-described testing and sorting on a large number of IC products, test equipment equipped with a so-called high-speed handler has been used. This conventional test apparatus for semiconductor devices will be described below with reference to FIGS. 1 a to 2 e and 2 a to e. First, the configuration will be explained with reference to FIG. 1a. In the figure, reference numeral 1 denotes a pre-test chute section for arranging continuously supplied semiconductor devices, for example, ICs, in a single row. ICx ₁ , x ₂ . . . arranged in a single row in the pre-test chute section 1 are
The test heads are shot one by one to the test head section 2 installed on the downstream side of the test head. The test head section 2 tests the electrical characteristics of each IC one by one to determine whether it is a good product or a defective product, and then shoots it to the sorting chute section 3.
If the IC being thrown out is a good product, the sorting chute section 3 will shunt it to a good product chute section 4, and if it is a defective product, it will be sent to a defective product chute section 5 disposed in the orthogonal direction. By shooting, good products and defective products are sorted out. Next, to explain the process by which good ICs x ₁ are selected according to Fig. 1 a to e, Fig. 1 a shows the process of selecting non-defective ICs x ₁ set in the test head section 2 after the test has been completed. It shows the condition. The ICx ₁ determined to be good in this way is further shunted from the sorting chute 3 to the good chute 4, and at the same time is sent to the next
ICx ₂ is thrown onto the test head 2 and set (as shown in FIG. 1b). Next, the test start of ICx ₂ newly set in the test head section 2 is turned on (as shown in Fig. 1c), and after the test is conducted (as shown in Fig. 1d), the test of ICx ₂ is turned off. (Illustrated in Figure 1e). On the other hand, assuming that this ICx ₂ is a defective product, the selection process will be explained below with reference to FIGS. 2a to 2e. FIG. 2a shows the state of FIG. 1e, ie, the test of the defective product ICx ₂ has been completed. When ICx ₂ is thus determined to be a defective product, this ICx ₂ is shunted to the sorting sheet section 3, and at the same time, the next ICx ₃ is shunted to the test head section 2 and set (as shown in FIG. 2b). Next, the sorting chute section 3 is rotated 90 degrees to remove defective products.
ICx ₂ is shunted to the defective product shunt section 5, and during this time the next ICx ₃ set in the test head section 2 is
The test start is turned on (as shown in FIG. 2c). Thereafter, a test of ICx ₃ is performed (as shown in FIG. 2d), and the test is further turned off (as shown in FIG. 2e). This ICx ₃ that has completed the test will be sorted by a process similar to that described with respect to FIG. 1 or FIG. 2, depending on whether it is a good product or a defective product. [Problems in the Background Art] As mentioned above, the conventional test equipment for semiconductor devices is equipped with only one test head section 2, and is configured as a single-row chute circuit system as a whole. Since the test head section 2 was constructed so that it was not possible to test a plurality of specimens at the same time, it was necessary to supply the test specimens to the test head section 2 one by one. Furthermore, when sorting out defective products, it is necessary to rotate the sorting chute section 3 to change the direction. Due to these factors, in conventional test equipment, it is difficult to conduct an electrical property test on a single test object. The machine index had to be quite large, approximately 1.0 to 1.5 seconds. For this reason, in order to improve work efficiency in the testing and sorting process of semiconductor devices, and ultimately to improve overall productivity, there has been a desire for a faster and more efficient testing apparatus for semiconductor devices. [Object of the Invention] A first object of the present invention is to provide a test apparatus for semiconductor devices having a plurality of columns of shoot circuit systems by providing a plurality of test heads in parallel. A second object of the present invention is to provide a semiconductor device testing apparatus that can simultaneously test a plurality of semiconductor devices using one test head. A third object of the present invention is to provide a test device for semiconductor devices that can efficiently sort semiconductor devices thrown from a plurality of test heads arranged in parallel into non-defective products and defective products. be. A more general object of the present invention is to provide a rapid and efficient test apparatus for semiconductor devices by achieving the above objects. [Summary of the Invention] The first feature of the semiconductor testing apparatus of the present invention is that a single fixed pre-test chute section for arranging the semiconductor devices supplied from the supply section in a single row, A plurality of fixed test heads for testing the electrical characteristics of the device are arranged in parallel, and a laterally movable distribution chute is provided between the test head and the pre-test chute. The semiconductor devices supplied in a single row from the chute section are distributed and shunted to a plurality of individual test head sections arranged in parallel. As a result, a plurality of parallel shute circuit systems including the test head section can be constructed, and a test apparatus that is more efficient than a conventional single-row shute circuit system can be obtained. Moreover, by providing a plurality of chute rows in parallel in this distribution chute section, it is possible to perform the operation of shunting semiconductor devices from the pre-test chute section to one of the chute rows, and the operation of shunting semiconductor devices from the pre-test chute section to another chute row where semiconductor devices have already been shunted. The operation of shunting the semiconductor device from the test head to one of the test heads can be performed at the same time. Therefore, in this case, the machine index for distributing and shunting semiconductor devices to each test head can be reduced to almost zero. A second feature of the semiconductor device testing apparatus of the present invention is that the individual test heads are capable of simultaneously testing the electrical characteristics of a plurality of semiconductor devices. Naturally, therefore, each chute row of the distribution chute is capable of accommodating the same number of semiconductor devices to be simultaneously tested in the test head. It is obvious without further explanation that this feature allows testing to be carried out more efficiently than in the past. A third feature of the present invention is that a single row of non-defective shoot parts is provided for the plurality of test heads provided in parallel, and a transversely movable part is provided between the non-defective shoot parts and the test head part. A sorting chute section is provided, and the sorting chute section selects and shoots only non-defective semiconductor devices that have been tested in the test head section to the non-defective chute section. The sorting chute section can be configured to include a plurality of chute rows, and may also include a bypass chute row specifically for sorting out defective products. Further, a defective product chute portion may be provided in parallel with the non-defective product chute portion,
A plurality of defective product chute sections can be provided in parallel. According to such a sorting mechanism, it is possible to sort out good products and defective products more quickly and efficiently than before. The semiconductor device testing apparatus of the present invention also makes it possible to reduce the machine index to substantially zero due to the above three features. [Embodiment of the Invention] FIG. 3 is an explanatory diagram showing a schematic configuration of a semiconductor device testing apparatus according to an embodiment of the present invention. In the figure, 11 is a pre-test chute section. The pre-test chute section 11 is connected to a semiconductor device supply section, and the semiconductor devices to be supplied are supplied in a single row in the direction of the arrow in the pre-test chute section 11. A distribution chute section 12 is disposed immediately downstream of the pre-test chute section 11. The distribution chute section 12 includes two chute rows 12 ₁ and 12 ₂ in parallel, each of which can accommodate two semiconductor devices, and the entire structure is arranged in the horizontal direction, that is, the flow of semiconductor devices, as shown by the arrows in the figure. It is now possible to move in a direction perpendicular to the direction. Immediately downstream of this distribution chute 12 are two test heads 13 ₁ , 13 _{2 .}
are installed in parallel. Individual test head 1
Test contacts 3 ₁ and 13 ₂ are provided with test contacts connected to one tester (not shown), and these test contacts are brought into contact with the leads of semiconductor devices set in the test heads 13 ₁ and 13 ₂ . Tests are now being held. Further, each of the test head sections 13 ₁ and 13 ₂ is configured to simultaneously set and test two semiconductor devices, and this test is all performed by the single tester (not shown). The distribution chute section 12 is arranged so that when one chute row ₁₂₁ is located directly below the pre-test chute section 11, the other chute row ₁₂₂ is located directly above the test head section ₁₃₂ ; When the chute row ₁₂₂ of the test head section 12 is located directly below the pre-test chute section 11, the other chute row ₁₂₁ is located directly above the test head section ₁₃₁ . And the distribution chute
12 moves in the direction of the arrow, two semiconductor devices are alternately thrown into the two chute rows 12 ₁ and 12 ₂ from the pre-test chute section 11, and at the same time, two semiconductor devices are thrown from the other chute row directly below them. Two semiconductor devices are thrown to the test head section ₁₃₁ or 132 located at the test head section 131 or ₁₃₂ . Immediately downstream of the test heads 13 ₁ and 13 ₂ , a sorting chute 14 that is movable in the lateral direction is disposed as indicated by the arrow in the figure. The sorting chute section 14 includes two chute rows 14 ₁ and 14 ₂ in parallel, each of which can accommodate two semiconductor devices. Immediately downstream of the sorting chute 14 , a single row of non-defective chute 15 is provided.
The non-defective product chute section 15 is connected to a non-defective product storage section (not shown) for storing semiconductor devices selected as non-defective products. In the sorting chute section 14 , when one chute row ₁₄₁ is located directly below the test head section ₁₃₁ , the other chute row ₁₄₂ is located directly above the non-defective chute section 15;
₂ is located directly below the test head portion ₁₃₂ , the chute row ₁₄₁ is located directly above the non-defective chute portion 15. The sorting chute section 14 operates in response to instructions from the tester (not shown), and the test head sections 13 ₁ , 13 ₂
Shoot rows 14 ₁ or 14 correspond to only good semiconductor devices that are alternately shot from
After receiving the semiconductor device into _the non-defective product chute section 15, the non-defective semiconductor device is moved laterally to be shunted into the non-defective product chute section 15. In addition, the pre-test chute section 11 and the distribution chute section
12 , test head sections 13 ₁ , 13 ₂ , and sorting chute section 14 are designed to be able to shoot out semiconductor devices one by one to the next stage section. As this shoot mechanism, a blow nozzle-based shoot mechanism can be used. On the other hand, as a mechanism for stopping the shunted semiconductor device at the next stage, a detection device for detecting the shunt of the semiconductor device and a stopper pen air cylinder operated by a detection signal from the detection device can be used. Further, as a mechanism for moving the distribution chute section 12 and the sorting chute section 14 in the lateral direction, a drive mechanism using a drive air cylinder can be used. As a matter of course, the operations of each of the above-mentioned parts, including the test equipment (not shown), are controlled as a whole so that they operate in a series of related manners as explained in the operation examples below. Hereinafter, with reference to FIGS. 4 to 6, the electrical characteristics test of semiconductor devices (ICs) to which the semiconductor device test apparatus according to the above embodiment is continuously supplied will be conducted, and based on the tests, these tests will be conducted. A specific example of the operation for sorting into good products and defective products will be explained. Operation example 1 (i) Figure 4a shows the state of the two ICx ₁ and 〓〓 set in the test head ₁₃₁ when the test is completed. As a result of this test, IC〓
It is assumed that 〓 is a defective product (hereinafter, an IC marked with a circle indicates that it is a defective product). At this time, the distribution chute section 12 is in the position shown, and ICy ₁ and y ₂ are shunted from one chute row ₁₂₂ to the test head section ₁₃₂ , and the other chute row ₁₂₁ has a pre-test chute. Part 1
The next shoot from ICx ₃ and x ₄ is about to take place. Further, the sorting chute section 14 is located at the position shown in the figure and is ready to sort the ICx ₁ and 〓〓 which have completed the test. (ii) Next, according to a command from a tester (not shown) that determines whether ICx ₁ and 〓〓 are good or defective, only the good ICx ₁ is sent to the sorting chute.
14 and housed in the chute row ₁₄₁ (as shown in FIG. 4b). At this time, in the distribution chute section 12 , from the pre-test chute section 11 to the chute row ₁₂₁ .
Shoots of ICx ₃ and x ₄ are being carried out, and
In the test head section ₁₃₂ , ICy ₁ and y ₂ are shunted from the distribution chute array ₁₂₂ and set for an electrical characteristic test. (iii) Next, the sorting chute section 14
In order to shoot out the ICx ₁ housed in the ICx ₁ to the non-defective product shoot section 15, the ICx 1 is moved in the direction of the arrow in the figure (as shown in FIG. 4c). At this time, the defective IC remains in the test head section ₁₃₁ as shown in the figure.
Also, in this state, the other test head
Testing of ICy ₁ and y ₂ has started, and distribution chute section 1
2, the shoots of ICx ₃ and x ₄ have been completed in the shoot column ₁₂₁ . (iv) Next, the sorting chute section 14
When _{ICx 1} comes directly above the non-defective product shoot section 15, it stops, and in this state, the non-defective product ICx ₁ is thrown to the non-defective product shoot section 15. At the same time, the defective IC left in the test head ₁₃₁
〓 is shunted to the defective product storage section as shown by the arrow in the figure (as shown in Fig. 4d). Note that normally, a defective product chute section is provided side by side with the non-defective product chute section 15. Further, in this state, a bypass chute row for defective products is provided on the left side of the chute row ₁₄₁ in the sorting chute section 14 so that the defective product chute section and the test head section ₁₃₁ are communicated with each other. is sent to the defective product storage section through this bypass chute row and the defective product chute section. On the other hand, at this time, the distribution chute section 12 moves in the direction of the arrow in the figure in order to chute the ICx ₃ and x ₄ stored in _the chute row 121 to the test head section ₁₃₁ . During this time, the test head section 13
In _{step 2} , the set ICy ₁ and y ₂ are tested. (v) Next, the distribution chute section 12
ICx ₃ and ICx 4 stop at the position directly above the test head section ₁₃₁ , and start shooting ICx ₃ and ICx ₄ to the test head section ₁₃₁ . At the same time, in the other chute row ₁₂₂ of the distribution chute section 12 , ICy ₃ and y ₄ are shunted from the pre-test chute section 11 (as shown in FIG. 4e). At this time, in the test head section ₁₃₂ , ICy ₁ , y ₂
It is assumed that the test for ICy ₁ and y 2 has been completed, and both ICy 1 and y ₂ have been determined to be good products. On the other hand, the sorting chute section 14
is already waiting to be fired from the test head ₁₃₂ in order to select ICy ₁ , y ₂ at the stage of FIG. 4d. (vi) Next, both ICy ₁ and y ₂ determined to be non-defective after the test in the test head section ₁₃₁ are shunted into the chute row ₁₄₂ of the sorting chute section 14 and stored therein. This operation is performed in response to a command from the tester (not shown) that has determined ICy ₁ and y ₂ to be non-defective products (as shown in FIG. 4f). At this time, the test head section ₁₃₁ completes the shooting of ICx ₃ and x ₄ from the distribution shoot train 12 ₁ , and ICx ₃ and x ₄ are set for testing. (vii) Next, the sorting chute section 14
In order to throw out the good ICy ₁ and y ₂ stored in the ICy 4 ₂ to the good product chute section 15, the ICy 1 and y 2 are moved to the left as shown by the arrow (as shown in FIG. 4g). At this time, the distribution chute section 12 also moves to the right as shown by the arrow in order to chute ICy ₃ and y ₄ accommodated in its chute row ₁₂₂ to the test head section ₁₃₂ . On the other hand, the test head section 13
At _{step 1} , testing of the set ICx ₃ and x ₄ is started. (viii) Next, the sorting chute section 14 stops at the position where its chute row ₁₄₂ is directly above the non-defective product chute section 15, and shoots the accommodated ICy ₁ and y ₂ to the non-defective product chute section 15. On the other hand, the distribution chute section 12 also stops at the position where its chute row _{122 is} directly above the test head section ₁₃₂ , and starts to shoot ICy ₃ and y ₄ from the chute row ₁₂₂ to the test head section 132 ( (Illustrated in Figure 4h). During this time, the test head section ₁₃₁ continues testing ICx ₃ and x ₄ . Thereafter, by repeating the processes from a to h in FIG. 4, the electrical characteristics of the IC are continuously tested, and if a defective product is found in the upper test area of the test head ₁₃₁ , this defective product and other It is possible to sort out the good products and the good ones. Operation example 2 (i) Figure 5a shows the same situation as Figure 4a. However, this case differs from FIG. 4a in that the IC set in the lower test portion of the test head ₁₃₁ is determined to be defective.
This defective IC is sorted out from other good ICs by the following process. (ii) First, among the ICs, x ₂ set in the test head section ₁₃₁ , only the defective ICs are sent to the chute row ₁₄₁ of the sorting chute section 14 , and the sorting chute section 14 Based on a command from a tester (not shown) that has determined that the IC is defective, the IC is allowed to pass through without being stopped. In this way, the defective IC is sent to the defective product storage section (as shown in FIG. 5b). During this time, the distribution chute section 12 finishes throwing ICy ₁ and y ₂ from the chute row ₁₂₂ to the test head section ₁₃₂ , and the test head section ₁₃₂
ICy ₁ and y ₂ are set. Further, the next shoots of ICx ₃ and x ₄ are performed in another shoot column 12 ₁ of the distribution shoot section 12 . In addition, in this example, unlike the case of action example 1,
Defective product ICs are shunted to the defective product storage section through the chute row ₁₄₁ of the sorting chute section 14 (as explained in operation example 1, the defective product chute section is usually arranged directly below the chute row ₁₄₁ ). ). This is because after the IC 〓〓 is shunted to the defective product storage section, the next good ICx ₂ must be received into the chute row ₁₄₁ of the sorting chute section 14 . That is, if the sorting chute section 1 is
4 to the right side and pass the defective product through the bypass chute row provided on the left side of chute row ₁₄ .
When IC〓〓 is shut down, the next good ICx ₂
The sorting chute section 14 must be moved to the left again in order to receive it, which complicates the operation and causes loss time. (iii) Subsequently, the non-defective ICx ₂ remaining in the test head section ₁₃₁ is shunted into the chute row ₁₄₁ of the sorting chute section 14 and stored (as shown in FIG. 5c). At this time, the test head unit ₁₃₂ starts testing the set ICy ₁ and y ₂ , and the distribution chute unit 12 has completed the chute of ICx ₃ and x ₄ in the shoot row ₁₂₁ . (iv) Next, the sorting chute section 14
The good ICx ₂ housed in ₁ is transferred to the good chute part 1.
5, move to the left as shown by the arrow in the figure (as shown in Figure 5d). At the same time, the distribution chute section 12 moves to the left as shown by the arrow in the figure in order to throw the ICx ₃ and _{x 4 accommodated} in the chute row ₁₂₁ to the test head section 131 (as shown in FIG. ). During this time, the set ICy ₁ and y ₂ are tested in the test head section ₁₃₂ . (v) Next, the sorting chute section 14
₁ stops directly above the good product chute section 15, and the good product stored in the chute row ₁₄₁ stops.
Shute ICx ₂ to the good product chute section (5th
Figure e). At the same time, the distribution chute section 12 also stops at the position where its chute row ₁₂₁ is directly above the test head section ₁₃₁ , and the ICx ₃ and x ₄ housed in the chute row ₁₂₁ are transferred to the test head section _131. Shooting action and the other shooting row 12
At _{step 2} , the operation of receiving ICy ₃ and y ₄ from the pre-test shoot section 11 is started. In addition, the test head section 1
At step ₃₂ , the test of the set ICy ₁ and y ₂ is completed (both ICy ₁ and y ₂ are determined to be non-defective products). (vi) After that, ICy ₁ and y ₂ that were determined to be good products were sorted using the same procedure as explained in Example 1.
Also, subsequent IC distribution, testing and sorting is carried out (as shown in FIG. 5f-h). Operation example 3 (i) Figure 6a shows the same situation as Figure 4a. However, this differs from FIG. 4a in that the ICs set in the test head ₁₃₁ are both determined to be defective. The selection process in this case is as follows. (ii) Test head section ₁₃₁ determined to be a defective product
IC〓〓〓〓〓〓 are as they are in the sorting chute section 14
is shot to the shoot column ₁₄₁ . Then, the sorting chute section 14 receives a command from the test equipment that has determined that the ICs 〓〓,〓〓 are defective.
The ICs 〓〓〓, 〓〓 are passed through as they are and sent to the defective product storage section through the defective product chute section which is normally arranged in parallel next to the good product chute section 15 (as shown in Fig. 6b). (iii) Next, the sorting chute section 14
In order to receive and sort the ICy _{1 and} y ₂ thrown from the test head section 132, the chute row ₁₄₂ starts moving to the right as shown by the arrow in the figure (shown in _FIG . It stops at the position directly below it (as shown in Figure 6d). During this period, the pre-test chute section 11, the distribution chute section 12 , and the test head sections ₁₃₁ , ₁₃₂
The operation in is exactly the same as that already explained in the first and second working examples. (iv) Thereafter, the ICy ₁ and y ₂ determined to be good by the test head section ₁₃₂ are shunted to the good product shoot section 15 according to the procedure exactly similar to that described in Example 1, and the subsequent IC distribution, Testing and sorting are carried out (as shown in Figures 6e-h). In this way, the two test parts set in the upper test part and the lower test part of the test head part ₁₃₁
Even if one or both of the ICs are defective, the defective product will be separated from other non-defective products. It goes without saying that even if defective products are found in the test head section ₁₃₂ , they are sorted out in the same manner as in Examples 1 to 3 above. In the test apparatus for semiconductor devices of the above embodiment, two test heads 13 ₁ and 13 ₂ are provided in parallel, which can test the electrical characteristics of two semiconductor devices at the same time.
Further, a distribution chute section 12 and a sorting chute section 1
4 constitutes two parallel chute circuit systems including the test head section.
It is possible to test and screen semiconductor devices much more quickly and efficiently than conventional test equipment. In particular, in the above embodiment, the distribution chute section 12 is provided with two chute rows 12 ₁ and 12 ₂ , and one chute row receives semiconductor devices from the pre-test chute section 11, and one chute row receives semiconductor devices from the other chute row. Because the operation of distributing and shunting semiconductor devices to the test head is performed at the same time,
As explained in detail in Operation Examples 1 to 3 above, it is now possible to operate the entire test apparatus in a state where a test is always being performed on either the test head section ₁₃₁ or ₁₃₂ . . Furthermore, even if the test head portions 13 ₁ and 13 ₂ are fully tested in this manner, as detailed in the above example of operation,
The sorting chute section 14 can perform a sorting operation in a sufficient manner. As a result, in the above embodiment, it is possible to achieve operation in a state in which the testers (not shown) connected to the test heads 13 ₁ and 13 ₂ are always operating, that is, in a state in which the overall machine index is zero. can. In the above embodiment, the present invention was implemented as including two shute circuit systems in parallel, but it is also possible to implement the invention as having three or more shute circuit systems in parallel. It is also possible to test three or more semiconductor devices at the same time with each test head. [Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a semiconductor device testing apparatus that can quickly and efficiently perform electrical characteristic tests and sorting of continuously supplied semiconductor devices. , which can greatly contribute to improving productivity.

[Brief explanation of the drawing]

1a to 2e are explanatory diagrams showing the schematic configuration of a conventional semiconductor device testing device and the function of testing and sorting semiconductor devices using the testing device, and FIG. A schematic explanatory diagram showing the configuration of a semiconductor device test apparatus according to an embodiment, FIG. 4a
to h, FIGS. 5a to 5h, and 6a to 6h are explanatory diagrams showing an example of the operation of testing and sorting semiconductor devices by the test apparatus according to the embodiment of FIG. 3. 11... Pre-test chute section, 12 ... Distribution chute section, 12 ₁ , 12 ₂ ... Distribution chute row, 1
3 ₁ , 13 ₂ ... test head section, 14 ... sorting chute section, 14 ₁ , 14 ₂ ... sorting chute row,
15...Good product shoot part.

Claims (1)

[Scope of Claims] 1. One fixed pre-test chute section for arranging continuously supplied semiconductor devices in a single line and shunting them to the next stage, and a plurality of fixed pre-test chute sections fixed downstream of the pre-test chute section. It consists of test heads arranged in parallel, each test head sets a plurality of semiconductor devices, and
A test head section configured to perform electrical characteristic tests on a plurality of set semiconductor devices at the same time and then shunt the devices to the next stage; one non-defective chute section connected to a non-defective product storage section of the apparatus; and a plurality of chute rows arranged in parallel and movable in the lateral direction between the pre-test chute section and the test head section. The distribution chute section is arranged such that when one chute row is in communication with the pre-test chute section, the other chute row is in communication with the test head section. By simultaneously performing the operation of throwing semiconductor devices from the front chute section to one chute row and the operation of shunting semiconductor devices from the other chute row to the test head section, the semiconductor devices being thrown from the pre-test chute section can be removed. a distribution chute section that accommodates a plurality of products in each chute row and sequentially shoots the plurality of products to the respective test heads; and a distributing chute section that is movable in the lateral direction between the test head section and the non-defective product chute section; A sorting chute section that accommodates only semiconductor devices judged to be good among the semiconductor devices thrown out from each test head and sends them to a good chute section. By arranging these so that when one chute row communicates with one of the test heads, the other chute row communicates with the non-defective chute section, good semiconductor devices can be shunted from the test head section to the sorting chute section. 1. A testing apparatus for semiconductor devices, comprising a sorting chute section that simultaneously performs an operation of accommodating good semiconductor devices and an operation of shunting good semiconductor devices from the sorting chute section to a good-goods chute section.