JPS6231433B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to semiconductor memories, particularly field effect transistors (hereinafter referred to as field effect transistors) having an insulated gate structure.
It is written as IGFET. ) with large capacity as the main component,
Concerning high speed storage devices.

(Prior Art) Fig. 1 shows an electrically programmable and erasable memory device (hereinafter referred to as EEPROM) in which low-energy electrons or holes are passed through an insulating film using an electric field. , which shows the configuration of a memory cell when a floating gate type IGFET that performs erasing is used as a storage element. The memory cell M _A consists of a selection IGFET (hereinafter referred to as selection cell) K _A and a floating gate type IGFET (hereinafter referred to as memory cell) that is actually written and erased and stores "0" or "1". ) L
It is constructed by connecting _A in series.

The gate electrode of the selection cell has a mail address line _XA , and the gate electrode of the storage cell has a mail address line XA.
A control line _CGA to which a desired voltage is applied is connected during writing, erasing, and reading.

The storage cell operates as shown in (A) and (B) below.
From now on, we will discuss charges passing through an insulating film as electrons.

(A) When electrons are injected into the floating gate, the floating gate becomes negatively charged. At this time, the threshold value of the memory cell equivalently appears to have increased, so even if a read voltage is applied to the gate electrode, the memory cell does not become conductive. This state is defined as an erased state, and "1" is written.

(B) When electrons are emitted from the floating gate, the floating gate equivalently becomes positively charged. At this time, even if 0V is applied to the gate electrode, the memory cell becomes conductive, resulting in a so-called normally on state. Let this state be the written state,
It is defined that “0” is written.

Generally, it is desirable for a memory cell to consist of one transistor/cell for large capacity and high integration, but as an EEPROM storage element, it is possible to use a method in which electrons or holes are passed through an insulating film using an electric field. When using a floating gate type IGFET,
As shown in (B) above, since the memory cell in the written state is conductive even when not selected, a selection cell is required as shown in Figure 1, and 2 transistors/cell are required. configured. FIG. 2 is a partial circuit diagram of an EEPROM according to the prior art. K ₁ , K ₂ ,
K ₃ , K ₄ are selection cells, L ₁ , L ₂ , L ₃ ,
L ₄ is a memory cell.

A first memory cell M ₁ in which a selection cell K ₁ and a storage cell L ₁ are connected in series, as well as K ₂ and L ₂
A second memory cell _M2 is connected in series, and...
... are connected in parallel to point B ₁ of the first digit line, and a third memory cell M ₃ has K ₃ and L ₃ connected in series, and likewise K ₄ and L ₄ are connected in series. are connected in parallel to the point _B2 of the second digit line, and the X address line _X1 , which is connected to the gate electrode of the selection cell, _respectively . X ₂ , ..., Y address lines specifying the Y address Y ₁ , Y ₂ , ..., control lines respectively connected to the gate electrodes of the memory cells
CG ₁ , CG ₂ , ..., 1 of the Y address lines
For Y address switching with book connected to gate electrode
IGFETS _{1 ,} S ₂ , . . _. , S ₁ , S ₂ , _.
It is composed of an inverting amplifier I ₁ which receives A ₁ as an input, and an output O ₁ of the inverting amplifier.

When reading, the X address line, Y address line,
When one of the control lines becomes "1" and the other becomes "0", memory cell _M1 is selected. At this time, memory cell L ₁ of selected memory cell M ₁
The information written in memory cell _L1
It is determined whether or not conduction occurs. Memory cell L ₁
When "1" is written in A1, _L1 becomes non-conductive, so the capacitance of the digit line is charged through the load resistance element R _L1 , and the voltage at point _A1 increases.

Conversely, if “0” is written to _L1 ,
The storage cell becomes conductive, and the charge stored in the capacitance added to the digit line becomes K ₁ ,
L ₁ is discharged, and the voltage at point A ₁ decreases.

As described above, the present memory device functions by amplifying the voltage of the digit line, which changes depending on whether the memory cell of the selected memory cell is conductive or non-conductive, by the inverting amplifier _I1 .

FIG. 3 shows a conventional example of an inverting amplifier used in a large-capacity, high-speed storage device.

A conventional example will be explained using FIGS. 3 and 4. The portion labeled MC in FIG. 3 is exactly the same as the portion labeled MC in FIG. 2, and therefore a description thereof will be omitted. This embodiment uses a push-pull type inverting amplifier IV ₁ whose input is the digit line DL, which is the output of the MC.
, a feedback resistor R _F connected between the output P ₁ of the inverting amplifier IV ₁ and the digit line DL, a feedback resistor R F connected between the output P 1 of the inverting amplifier IV 1 and the digit line DL, and a feedback resistor R F connected to the inverting amplifier IV ₁ with its source connected to the digit line DL and its drain and gate in common. It consists of an enhancement type feedback IGET _QF connected between output _P1 . Q ₁ is depression type
IGFET, Q ₂ is an enhancement type IGFET, Q ₃
is a shallow depression type IGFET, and _Q4 is an enhancement type IGFET. When Q ₄ conducts, a voltage is applied to the gate electrode of Q ₃ that reduces the current, so there is no need to increase the ratio of the sizes of Q ₄ and Q ₃ . Therefore, the capacitance between the digit line DL and the output _P1 of the inverting amplifier can be reduced. Therefore, since the influence of Miller capacitance is small, the push-pull type inverting amplifier of this example operates at high speed.

FIG. 4 shows a schematic diagram of the input/output characteristics of the inverting amplifier _IV1 .

The operation of the conventional example will be explained with reference to FIGS. 3 and 4. First, the case where "1" is written in the storage cell of the selected memory cell, that is, the case where the digit line is charged will be explained.

In the worst case, the voltage on the digit line _DL is 0V.
shall be. The output voltage V _P1 of the inverting amplifier IV ₁ is the power supply voltage V _CC or a value close to it. (Corresponding to point a of curve E in Figure 4) In this case, [V _P1 −V _D
Since _L ] is sufficiently larger than the threshold voltage V _Th of the feedback IGFET Q _F , an extremely large current flows through the feedback IGFET Q _F to charge the large capacitance added to the digit line DL. When the voltage V _DL on the digit line DL rises to the voltage corresponding to point b ₁ in FIG. 4, the output voltage V _P1 of the inverting amplifier changes due to the change in the voltage V _DL on the digit line, as is clear from FIG. The amplification factor of the inverting amplifier changes by -A times.

For example, if A is designed to be 30, the voltage will change by about 3V in response to a 0.1V change in the digit line voltage _VDL . In this way, when the voltage V _DL of the digit line increases and reaches point C ₁ in FIG.
_P1 −V _DL ] is equal to the threshold value V _Th of the feedback IGFET Q _F , and the feedback IGFET Q _F
becomes non-conducting. From this point on, the current charging the capacitance of the digit line flows through the feedback resistor _RF , and the voltage V _DL of the digit line DL is balanced at the point where it matches the output voltage V _P1 of the inverting amplifier. (Corresponds to point d ₁ of curve E in Figure 4)
Let the voltage of the digit line DL at this time be V _R1 .

Next, a case where the address is switched and a memory cell in which "0" is written in the storage cell is selected, that is, the case where the digit line is discharged will be explained.

The electric charge accumulated in the capacitance of the digit line is discharged by the current I _ON flowing through the memory cell, and the voltage of the digit line decreases. Accordingly, the output voltage V _P1 of the inverting amplifier has an amplification factor of -
It rises by A times, and becomes vague [V _P1 = V _R1 + R _F I _O
Equilibrate with _N ]. (Corresponds to point C ₁ of curve E in Figure 4)
The voltage of the digit line DL at this time is assumed to be _VDL1 .

However, in this case, the output voltage V of the inverting amplifier
_p1 is limited where the feedback IGFET becomes conductive.

As mentioned above, EEPROM memory cells are
Because it is composed of 2 transistors/cell,
It is disadvantageous in increasing capacity compared to one transistor/cell configuration such as UVPROM.
In order to increase capacity, it is necessary to reduce the area occupied by one cell and increase integration.

Therefore, the gate width of the selection cell must necessarily become small. When the gate width of the selection cell becomes smaller and its drive capability drops, the current I _ON flowing through the storage cell causes a potential drop in the selection cell, and the voltage applied to the drain of the storage cell V _DL '
is expressed by equation (1), and is lower than the voltage _VDL of the digit line.

V _DL '=V _DL -R I _ON (R: equivalent resistance of the selection cell) ......(1) Figure 5a shows the drain voltage _VD of the memory cell and the memory cell drain voltage VD in Figure 5b. Current flowing through the cell I _O
This shows the relationship between _N. For high integration,
Since the gate length of the memory cell is designed to be as small as possible, there is no clear saturation region, and the current I _ON flowing through the memory cell is equal to the drain voltage V _D
become dependent on.

Therefore, as the drain voltage of the memory cell becomes lower, the current I _ON flowing through the memory cell becomes smaller.

In order to operate EEPROM at high speed in order to meet the demands for larger capacity and higher integration, it is necessary to quickly charge and discharge the capacitance of the digit line.

During charging, in the case of this conventional example, the feedback IGFET Q
By increasing the driving capacity of _F , it is possible to operate at high speed relatively easily.

During discharging, high-speed operation can be achieved by increasing the current I _ON flowing through the memory cell. However, as memory cells are miniaturized for larger capacity and higher integration, The current I flowing through
It is difficult to increase _ON .

Therefore, normally the speed at which the digit line is discharged is
It determines the operating speed of EEPROM.

In Figure 3, enhancement type IGFET
Suppose that the threshold value V _Th of is lower than the set value.
Curve F in FIG. 4 shows a schematic diagram of the input/output characteristics of the inverting amplifier IV ₁ in this case.

Since the E/D inverter composed of Q ₁ and Q ₂ is inverted quickly, curve F is the input/output characteristic of inverting amplifier IV ₁ when threshold value V _Th is the set value. The result is a parallel shift to the left by the amount that the value V _Th has changed. In this case, “1” is stored in the memory cell.
If you select a memory cell in which "0" is written, the equilibrium point is point d _11. If you select a memory cell in which "0" is written, the equilibrium point is point C ₁₁ .
move to each. Therefore, the bias voltage due to the feedback resistor R _F of the voltage V _DL of the digit line is
When the threshold V _Th is at the set value, it is V _R1 , but when the threshold V _Th becomes lower, it becomes V _R11 , and the inverting amplifier will It will operate at a relatively low value. The drain voltage of the storage cell with respect to the digit line voltage V _DL11 when the threshold value V _Th becomes low is V _DL ' ₁₁ , and the drain voltage of the storage cell with respect to the digit line V DL1 when the threshold value V _Th is the set value is V _{DL ' 11} . Assuming that the drain voltage is V _DL ' ₁ , as is clear from FIG. 5-a, the current I _ON flowing through the cell is smaller when the threshold value V _Th is lowered.

Therefore, the operating speed during discharging will be reduced. In the extreme case, the output amplitude of the inverting amplifier R _F I _O
Since _N becomes small, it becomes impossible to determine the state of the memory cell.

Furthermore, as is clear from the curve F in Fig. 4, when the threshold value V _Th becomes lower than the set value, as the bias voltage V _R11 of the digit line becomes lower, the bias is applied to the most sensitive point of the inverting amplifier. As a result, the speed of charging and discharging will decrease.

As described above, in this example using the conventional technology, if the integration is increased and the gate width of the selection cell is made smaller, the potential drop in the selection cell becomes larger.
Since the drain voltage of the memory cell is reduced, the flowing current I _ON is reduced. Also, when the threshold V _Th is lower than the set value, I _ON is further reduced and the voltage on the digit line is no longer biased to the most sensitive point of the inverting amplifier. Therefore, the speed is low, making it unsuitable for large-capacity, high-speed storage devices.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a large-capacity, efficient, high-speed storage device.

(Structure of the Invention) A memory device of the present invention includes at least a plurality of memory elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the memory contents of the memory element. In the storage device, the storage element is a storage element in which it is determined whether or not a current can flow through the storage element itself depending on the stored content, and the detection means includes a level shifter stage that receives the digit line as an input; It is composed of an inverting amplifier that receives the output of the level shifter stage as an input.

(Example) An embodiment of the present invention is shown in FIG.

The portion labeled MC is exactly the same as the portion labeled MC in FIG. 2, so the explanation will be omitted. One embodiment of the present invention includes a plurality of memory cells as memory elements connected in a matrix, one memory cell selected in response to an address signal,
A functional block MC electrically connected to the digit line DL, an enhancement type IGFET Q _L1 whose input is the digit line DL, and a depletion type IGFET whose source is connected to the drain of Q _L1 .
Level shifter stage LS consisting of IGFET Q _L2
, a push-pull type inverting amplifier IV ₁ which inputs the output LO of the level shifter stage, a feedback resistor R _F connected between the digit line DL and the output P ₂ of the inverting amplifier IV ₁ , and a source connected to the digit. line
DL is composed of an enhancement type feedback IGFET _QF whose drain and gate are commonly connected between the output _P2 of the inverting amplifier.

(Operation of the embodiment) The operation of the embodiment of the present invention is shown in FIG. 5a, FIG.
This will be explained using FIGS. 7 and 8.

As explained in the conventional example, FIG. 5a shows the drain voltage dependence of the current I _ON flowing through the memory cell.

FIG. 6 is a circuit diagram showing one embodiment.

FIG. 7 shows the input/output characteristics (curve E) of the conventional inverting amplifier IV ₁ and the input/output characteristics (curve G) of the inverting amplifier IV with level shifter stage according to the embodiment of FIG. 6.
This is a comparison of the schematic diagrams.

Figure 8 shows the digit line DL in Figure 6.
This figure shows the relationship between the voltage V _DL of the output LO of the level shifter stage and the voltage V _LO of the output LO of the level shifter stage. In FIG. 6, the voltage V _LO of the output LO of the level shifter stage LS is:
IGET is determined by the ratio of the driving capabilities of Q _L1 and Q _L2 , and if the voltage V _DL of the digit line DL does not rise to the threshold value V _Th of Q _L1 , Q _L1 will not conduct, so the level shifter stage The relationship between the output V _LS of the LS and the voltage V _DL of the digit line DL is, for example, as shown by the straight line I in FIG. 8, and the following relationship always holds: V _LO <V _DL (2). J is a straight line with a slope of 1. Therefore, when considering an inverting amplifier IV with level shifter stages, in which the digit line DL is input and the output _P2 of inverting amplifier IV ₁ is output, the input/output characteristics of the inverting amplifier IV with level shifter stages are as follows.
As shown by curve G in FIG. 7, the curve E, which is the input/output characteristic of the conventional inverting amplifier _IV1 , is shifted in parallel to the right. As is clear from the curve G, in this example, when a memory cell in which "1" is written is selected, the digit line is charged in exactly the same order as in the conventional example, and the action of the feedback resistor R _F is equilibrium at point d ₂ . Let the voltage of the digit line at this time be V _R2 . On the other hand, when a memory cell in which "0" is written is selected, the digit line is discharged in exactly the same order as in the conventional example, and the voltage V _P2 of the output _P2 of the inverting amplifier with level shifter stage becomes V _P2 = V _R2 + R _F I _ON ......(3) and equilibrium is reached at point _C2 . Digit line at this time
Let the voltage of DL be _VDL2 . The voltage V _DL2 of the digit line DL with respect to point C ₂ is clearly larger than the voltage V _DL1 of the digit line with respect to point C ₁ , which is the equilibrium point in the conventional case.

The voltage applied to the drain of the memory cell is lower than the voltage of the digit line DL for the reason stated in the conventional example. Let V _DL2 ' be the drain voltage of the storage cell with respect to the balanced voltage V _DL2 of the digit line DL in this example, and V DL1 ' be the drain voltage of the storage cell with respect to the balanced voltage V _DL1 of the digit line _DL in the conventional example. Then, as is clear from Figure 5-a, the current I _ON flowing through the storage cell is greater when using the inverting amplifier IV with level shifter stages of this example than when using the conventional inverting amplifier IV ₁ . can generally be larger. In addition, since the voltage of the digit line is biased to a higher value than in the conventional case, even if the threshold value V _Th becomes lower, I _ON can be larger than in the conventional case, and the highest voltage of the inverting amplifier The disadvantage of not being biased toward sensitive points is also eliminated.

(Effects of the Invention) As described above, the memory device of the present invention can increase the current I _ON flowing through the memory cell, which tends to decrease with higher integration, and the threshold value V _Th can be set. Even if the value changes, there is no disadvantage that the inverting amplifier is no longer biased to the most sensitive point, so it is suitable for storage devices that require large capacity and high speed.

The above embodiment has been explained using an EEPROM as an example, but it is effective as long as the voltage of the digit line containing the selected memory cell changes depending on the stored contents, and the structure can detect this change. , not limited to EEPROM.

Regarding the level shifter stage, although an enhancement type IGFET and a depressing type IGFET are connected in series, it is effective as long as it has a configuration in which the output level is shifted relative to the input. Further, although the inverting amplifier has been described using a push-pull type as an example, the configuration is not particularly limited.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an EEPROM memory cell. FIG. 2 is a partial circuit diagram of a storage device according to the prior art. FIG. 3 is a diagram showing the configuration of a conventional inverting amplifier. Figure 4 shows the input/output characteristics of the conventional inverting amplifier IV ₁ , where E is the threshold value V
When _T is a set value, F indicates a case where the value becomes lower than the set value. FIG. 5a shows the drain voltage dependence of the current I _ON flowing through the memory cell, and FIG. 5b shows the measurement conditions for obtaining FIG. 5a. FIG. 6 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 7, E shows the input/output characteristics of the conventional inverting amplifier _IV1 , and G shows the input/output characteristics of the inverting amplifier IV of the embodiment of the present invention. FIG. 8 shows the input/output characteristics of the level shifter stage.

Claims (1)

[Claims] 1. A memory device including a plurality of memory elements, an address line, a digit line, and a detection means for detecting a voltage of the digit line that changes depending on the storage contents of the memory element, wherein the memory element includes: It is a memory element in which it is determined whether or not a current can flow through the memory element itself depending on the memory contents, and the detecting means includes a level shifter stage that receives the digit line as an input, and an output of the level shifter stage that receives the output of the level shifter stage as an input. the digit line is short-circuited to the output of the inverting amplifier via an element having a resistance component during at least a read period;
Furthermore, an insulated gate field effect transistor is connected between the digit line and the inverting amplifier so as to become conductive when the output voltage of the inverting amplifier becomes higher than a certain level in the direction of the power supply compared to the voltage of the digit line. A storage device comprising: