JPS6252398B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device.

FIG. 1 shows a block diagram showing the read state of an electrically writable read-only memory (hereinafter referred to as EPROM) having an insulated gate.

Generally, a memory cell has a written state and a non-written state. The threshold value (V _T ) in the write state is higher than the voltage applied to the gate electrode during reading. Therefore, when this memory cell is selected, the memory cell becomes non-conductive (OFF). Now, this is defined as "0" being stored. When a memory cell in a non-written state is selected, the memory cell becomes conductive (ON). This is defined as "1" being stored.

In FIG. 1, it is assumed that memory cell _M1 is selected by address line _X1 and address line _Y1 . When “0” is stored in memory cell _M1 , the potential of point L is Voff(L), and the potential of point M is
Let it be Voff (M).

On the other hand, due to address line X ₂ and address line Y ₁ ,
Memory cell M ₂ is selected and this memory cell
When “1” is stored in M ₂ , the potential at point L is
Von(L), and the potential at point M is Von(M). The amplifier 1 amplifies the potential difference between the Voff (L) and Von (L). Since the digit line is connected to point L, it has a large capacity. The comparison detector 3 compares the potential Voff (M) at point M when "0" is written in the memory cell with the reference voltage V _REF obtained by the reference voltage generation circuit 2, and calculates the equation (1). When the relationship holds true, it is determined that "0" is written in the memory cell, the difference between the potential at point M and the reference voltage is amplified, and "0" is output to the output Vo through output buffer 4. be done.

Voff (M) > V _REF +α ...(1) (α: Minimum potential difference that can be detected by the comparison detector) On the other hand, when "1" is written in the memory cell, the potential Von of point M (M) and the reference voltage V _REF obtained by the reference voltage generation circuit 2,
When the relationship in equation (2) holds true, it is determined that "1" is written in the memory cell, and the difference between the potential at point M and the reference voltage is amplified and output through the output buffer 4. “1” is output to Vo.

Von (M) + α < V _REF ... (2) (α: Minimum potential difference that can be detected by the comparison detector) As stated above, whether the EPROM operates normally or not depends on the reference voltage , it depends on whether the relationship in equation (2) is satisfied or not. Therefore, it is necessary to create a stable reference voltage against manufacturing variations and power supply voltage fluctuations.

FIG. 2 is a partial circuit diagram of an EPROM according to the prior art. MOS transistors Tr ₁₀ , Tr ₁₁ ,
Tr ₁₂ and Tr ₁₄ constitute the amplifier in FIG. The MOS transistor _Tr15 is a selection transistor whose gate electrode receives the address line _Y11 . Both MOS transistors Tr ₁₆ and Tr ₁₇ are memory cells. Now, to simplify the explanation, it is assumed that "0" is written in the transistor Tr ₁₆ and "1" is written in the transistor Tr ₁₇ . Above, transistor Tr ₁₀ ,
A partial circuit composed of Tr ₁₁ , Tr ₁₂ , Tr ₁₃ , Tr ₁₄ , Tr ₁₅ , Tr ₁₆ and Tr ₁₇ is designated as A in FIG. Transistors Tr ₃ , Tr ₄ , Tr ₅ , Tr ₆ , and Tr ₇ also constitute an amplifier, and have the same characteristics as the amplifier in A. The transistor Tr ₈ has the same characteristics as the transistor Tr ₁₅ , and the signal Y ₁₁ (power supply voltage) at the time of selection is applied to the gate electrode. transistor
Tr ₉ is a transistor (hereinafter referred to as a dummy cell) that has the same structure and characteristics as a memory cell,
A voltage obtained by resistance division between transistors Tr ₁ and Tr ₂ , which are depletion type MOS transistors, is applied to the gate electrode, thereby limiting the current flowing through the transistor Tr ₉ . that's all,
Transistors Tr ₁ , Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ , Tr ₆ ,
The partial circuit composed of Tr ₇ is designated as B in Fig. 2.

The operation of the conventional example will be explained using FIGS. 2 and 3. Now, address lines X ₁₁ and Y ₁₁ connect memory cells.
Suppose Tr ₁₆ is selected. Since "0" is written in Tr ₁₆ , the threshold value (V _T ) is normally higher than the power supply voltage, so even if the power supply voltage is applied to the address line X ₁₁ , Tr ₁₆ will not conduct. The potential V _D (off) at point D at this time is expressed by equation (3).

V _D (off) = V _CC −V _T12
(V _T12 :Threshold value of Tr ₁₂ ) ...(3) On the other hand, assume that memory cell Tr ₁₇ is selected by the address lines X ₂₁ and Y ₁₁ . Since “1” is written in Tr ₁₇ , the power supply voltage is _connected to the address line
Tr ₁₇ becomes conductive since the threshold voltage (V _T ) is normally below the power supply voltage. The potential V _D (on) at point D at this time is Tr ₁₂ , Tr ₁₃ , Tr ₁₄ ,
The value is determined by the resistance of Tr ₁₅ and Tr ₁₇ . The potential at point E at point B is lower than the current flowing through Tr ₉ compared to the current flowing when a memory cell written with "1" is selected because the potential at point F is lower than the power supply voltage. The potential V _REF1 of E is
The value of the potential V _D (off) at point D when a memory cell written with “0” is selected and the potential V D at point _D when a memory cell written with “1” is selected.
(on).

FIG. 3 shows the potential V _D (off) at point D when "0" is written in the selected memory cell, and
This shows the power supply voltage dependence of the potential V _D (on) at point D when “1” is written in the selected memory cell and the reference voltage V _REF1 obtained from the reference voltage generation circuit at B. It is.

Referring to FIG. 3, the values of the potential V _D (off) at point D, V _D (on) and potential V _REF1 at point E when the power supply voltage is sequentially increased from 0 will be explained.

When a memory cell in which “0” is written by the address line is selected, V _D
(off)=V _CC −V _T12 . The threshold value (V _TM
If it is made larger than ₀ ), it will not follow the curve of equation (3), but this voltage is usually high, so it is not shown in Figure 3. When a memory cell in which "1" is written is selected by the address line, when the power supply voltage becomes larger than the threshold value (V _TM ) of the memory cell, the memory cell becomes conductive, so the point D
As the power supply voltage increases, the potential _D (on) of
It becomes far away from the value represented by the V _D (off) curve, and can be approximated by a curve with a smaller slope than the V _D (off) straight line.

On the other hand, since a voltage lower than the power supply voltage is applied to the gate electrode of the dummy cell, when the dependence of the value of V _REF1 on the power supply voltage is shown, the threshold value (V _T ) appears to be higher. Let this equivalent threshold be V _TM '. While the power supply voltage is slightly higher than V _TM ', the conductivity of the dummy cell is poor, so even if the power supply voltage is increased, the potential at point E is close to the value represented by the V _D (off) curve, and V _D (off ) and the value of V _REF1 cannot be detected by the comparison detector.
(Region P) When the power supply voltage is further increased, the comparison detector operates normally. (Area of Q) However,
As the power supply voltage increases, Tr ₂ in Figure 2B
Since the increase in the conductivity of Tr 1 is greater than the increase in the conductivity of Tr ₁ , the potential at point F rises rapidly. Therefore, the potential at point E now approaches the value represented by the straight line of V _D (on), and the comparison detector can detect the difference between the value of V _REF1 and the value of V _D (on). become unable.

(Region of R) As described above, in this example using the conventional technology, it is difficult to appropriately set the reference voltage in a wide range of power supply voltages, and the lowest voltage V _CC min at which the EPROM operates normally is When a memory cell written with “0” is selected, it is limited to the highest voltage V _CC
max is limited when a memory cell in which "1" is written is selected, and there is a drawback that even if one is tried to improve one, the other becomes worse.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference voltage generation circuit for a comparison detector which eliminates the above-mentioned drawbacks, can be easily set, and operates normally over a wide range of power supply voltages.

The storage device of the present invention includes a plurality of memory cells, and one memory cell is selected by an X address line and a Y address line,
a first amplifier that determines the memory content by changing the voltage of the digit line connected to the memory cell in accordance with the memory content of the selected memory cell, and amplifies the voltage of the digit line;
a first partial circuit consisting of the memory cell; and an element having the same structure and characteristics as the memory cell, to which the same voltage as the X address line is applied at the time of selection to the gate electrode, and the first amplifier; A reference voltage consisting of a plurality of resistive elements inserted between the output section of a second amplifier having the same characteristics as the constant voltage source and the output from the connection point of the plurality of resistive elements. a generation circuit and a differential amplifier, the output of the first amplifier of the first partial circuit;
It is characterized in that the output of the reference voltage generation circuit is used as the input of the differential amplifier, and the output of the reference voltage generation circuit is used as the reference voltage input of the differential amplifier.

FIG. 4 is a circuit diagram showing an embodiment according to the present invention. The part A on the left side is the same as the part A in FIG. Transistors Tr ₂₀ , Tr ₂₁ , Tr ₂₂ ,
The amplifier composed of Tr ₂₃ and Tr ₂₄ has the same characteristics as the amplifier composed of transistors Tr ₁₀ , Tr ₁₁ , Tr ₁₂ , Tr ₁₃ and Tr ₁₄ in A. The transistor Tr ₂₅ has the same characteristics as the transistor Tr ₁₅ in A, and the signal Y ₁₁ (power supply voltage) at the time of selection is applied to the gate electrode.

Tr ₂₆ is a dummy cell having the same structure and characteristics as the memory cells such as Tr ₁₆ in A, and a signal (power supply voltage) such as X ₁₁ at the time of selection is applied to the gate electrode. Transistors Tr ₂₇ and Tr ₂₈ are depletion type MOS transistors with large resistance. Transistor Tr ₂₉ is a transistor having the same characteristics as transistor Tr ₁₂ in A.

The operation of the embodiment according to the present invention will be explained using FIGS. 4 and 5.

The portion for obtaining the output voltages V _D (on) and V _D (off) of A has the same configuration as that in FIG. 2, so a description thereof will be omitted. The potential V _H at point H in C is approximately the same value as the potential V _D (on) at point D when the memory cell Tr ₁₇ in which "1" is written in A is selected. Also, the potential V _G at point G is the potential at point D when the memory cell Tr ₁₆ in which “0” is written at A is selected.
This value is almost the same as the potential V _D (off) of . This is because, in A, if a memory cell in which "0" is written is selected, even if a signal is applied to the gate of the memory cell, the memory cell will not become conductive, so current will flow through the memory cell. do not have. Therefore, the potential at point D is the value expressed by equation (3), but this value can be obtained by approximating it with one transistor expressed by Tr ₂₉ of C, which has the same characteristics as Tr ₁₂ of A. . Tr ₂₇ and Tr ₂₈ are depletion type MOS transistors used to divide the value of the potential V _H at point H and the value of the potential V _G at point G by resistance, and the resistance of Tr ₂₇ is divided by the resistance of R ₁ and Tr ₂₈ . resistance
When R ₂ is assumed, the potential at point I, V _REF2 , is expressed as in equation (4).

V _REF2 = R ₂ V _H + R ₁ V _G /R ₁ + R ₂ ...(4) In the conventional circuit shown in Fig. 2, as mentioned above, the V of V _REF1
It is highly dependent _{on CC} . However, as described above, the reference voltage generation circuit of the present invention generates a voltage corresponding to V _D (off) at point G (V _G ), and generates a voltage corresponding to V _D (on) at point H ( V _H ) and point G and point H
It is constructed by connecting resistors R ₁ and R ₂ . Therefore, V _REF2 is expressed by equation (4). By expressing V _REF2 by equation (4), V
_REF2 is always between V _G and _H , that is, between V _D (off) and V
_D (on), so that the comparison detector in the next stage always operates stably even if the process parameters change slightly. Also, by setting R ₁ = R ₂ , even if V _CC changes, V _REF2 remains V _D (off).
and V _D (on).

Similar to FIG. 3, FIG. 5 shows the output voltage V D (off) at point D when "0" is written in the selected memory cell, and the output voltage V _D (off) when "1" is written in the selected memory cell. It shows the power supply voltage dependence of the output voltage V _D (on) at point D in the case of writing and the reference voltage V _REF2 obtained from the reference voltage generation circuit C of the present invention. In the figure, V _D (off), V _D (on)
The curve represented by corresponds to that in FIG.
The power supply voltage dependence of the potential V _G at point G at C is
As mentioned above, it is almost the same as V _D (off), and the dependence of the potential V _H at point H on the power supply voltage is also V _D
It is almost the same as (on). Here, I say almost because there is an extra current path from the power supply to point G - point I - point H, but this can be ignored by increasing the resistance of Tr ₂₇ and Tr ₂₈ . .
In the conventional reference voltage generation circuit shown in FIG. 2, the gate voltage of dummy cell Tr ₉ is controlled by Tr ₁ and Tr ₂ , but in the reference voltage generation circuit of the present invention, the gate of dummy cell Tr ₂₆ is connected to V _CC. has been done. Therefore, the current values flowing through the memory cell and dummy cell _Tr26 are always the same even if V _CC changes. Therefore, since the V _CC dependence of V _H is almost the same as V _D (on), from equation (4), even if V _CC changes, V _REF2
is always set near the midpoint between V _D (off) and V _D (on), so that the range of V _CC in which the comparison detector in the next stage normally operates is wider than in the case of the prior art. Therefore, for example, if the resistance R ₁ of Tr ₂₇ and the resistance R ₂ of Tr ₂₈ are made equal, and the power supply voltage is gradually increased from 0, the reference voltage V _REF2 will be equal to the value of the memory cell in which "0" is written. The voltage at point D when V _D (off) is selected and the potential at point _D when a memory cell in which "1" is written is selected.
It is always set near the middle position of (on), and the range in which the comparison detector operates normally is
The lowest voltage (V _CC 'min) at which the comparison detector operates normally, regardless of whether a memory cell in which "0" or "1" is written is selected, is:
It is determined by the threshold value (V _TM ) of the memory cell in which "1" is written, and the maximum voltage (V _CC
max) is considered to be determined by the threshold value (V _TM0) of the memory cell in which "0" is written, and the power supply voltage range in which the EPROM operates normally is wide, and the reference voltage can be easily set. be able to.

As described above, in the storage device of the present invention, the reference voltage used for the comparison detector can be easily set at an appropriate position over a wide power supply voltage range.
Since the power supply voltage range for normal operation is wide, there is no burden on the comparison detector. Therefore,
Effective for storage devices such as EPROM.

The above embodiments have been explained using an EPROM as an example, but the present invention is effective as long as the potential of the digit line containing the selected memory cell changes depending on the contents of the memory cell. Not limited to EPROM. In addition, although Fig. 4 shows an example in which two depletion type MOS transistors are used, it is also possible to use multiple resistive elements.
The present invention is also effective when generating a potential to be set. In addition, in FIG. 4, the potential V at point D when "0" is written in the selected memory cell
Although _D (off) can be achieved with one Tr ₂₉ , the present invention is effective with any configuration as long as it produces a potential close to V _D (off).

[Brief explanation of the drawing]

FIG. 1 is a block diagram when reading data from a nonvolatile memory. FIG. 2 is an example of a conventional circuit for generating a reference voltage. Figure 3 shows the potential V _D at point D when a memory cell written with "0" is selected in Figure 2A.
(off), the potential V _D (on) at point D when a memory cell in which "1" is written is selected, and the dependence of the value of the reference voltage V _REF1 on the power supply voltage. FIG. 4 shows an embodiment of the present invention. Figure 5 shows the potential V at point D when the memory cell in which "0" is written in Figure 4 is selected.
It shows the power supply voltage dependence of the potential V _D (on) at point D and the value of the reference voltage V _REF2 when a memory cell in which _D (off) and "1" are written is selected.
Here, V _D (off) and V _D (on) correspond to those in FIG. Also, the potential V _H at point H in FIG.
The dependence of the potential V _G at point G on the power supply voltage is approximately equal to the curves represented by V _D (on) and V _D (off), respectively. 1... An amplifier that amplifies the potential change at point L, 2...
. . . a reference voltage generation circuit, 3 . . . a comparison detector that compares and amplifies the difference between the output of the amplifier 1 and the output of the reference voltage generation circuit 2, and 4 . . . an output buffer.
X ₁ , X ₂ , X ₃ , X _o . . . address lines to which a power supply voltage is applied when one of them is selected; Y _{1 .} . . a Y address line to which a power supply voltage is applied when selected.

Claims (1)

[Claims] 1 Including a plurality of memory cells, one memory cell is selected by an X address line and a Y address line, and the voltage of a digit line connected to the memory cell is set to the memory of the selected memory cell. a first subcircuit consisting of a first amplifier for determining the memory content and amplifying the voltage of the digit line by changing it depending on the content; and a first partial circuit comprising the memory cell; a second partial circuit comprising a second amplifier having the same characteristics as the first amplifier; A reference voltage consisting of a plurality of resistive elements inserted between the output part of the second amplifier of the partial circuit and a constant voltage source, and an output taken from an intermediate connection point of the plurality of resistive elements. a generation circuit and a differential amplifier, the output of the first amplifier of the first partial circuit is used as an input of the differential amplifier, and the output of the reference voltage generation circuit is used as the reference voltage of the differential amplifier. A storage device characterized in that it is used as an input.