JPS6231828B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit incorporating power elements.

Generally, a power element such as a power transistor is assembled on a substrate together with other elements such as a resistor, a capacitor, an IC (integrated circuit), a small signal transistor, etc., to create a circuit function of a hybrid integrated circuit.

By the way, in a hybrid integrated circuit using such a power transistor, heat is generated due to the large amount of power, and a heat dissipation structure for dissipating the generated heat to the outside is important. Conventionally, this heat dissipation structure, for example,
It is as shown in the figure. In the same figure, 1 is a power transistor, 2 is a power transistor 1
3 is a Cu layer to diffuse the heat generated in the power transistor 1.
(copper) block layer, 4 is a solder layer for fixing the Cu block layer 3, 5 is a Cu conductor pattern, 6 is an insulating layer made of epoxy resin adhesive, 7 is Al
(aluminum) substrate, 8 is a heat sink, and 9 is a screw for attaching the Al substrate 7 to the heat sink 8. In other words, the heat dissipation path of this hybrid integrated circuit is as follows:
Focusing on conduction among conduction, convection, and radiation, the heat generated in the power transistor 1 is transferred to the high-temperature solder layer 2, the Cu block layer 3, the solder layer 4, the Cu conductor pattern 5, the insulating layer 6, the Al substrate 7, and the heat sink. 8 and are designed to conduct in the order in which they are connected.

Incidentally, in order for the heat generated in the power transistor 1 to be quickly transmitted to the heat sink 8, it is necessary that each of the above-mentioned elements have good thermal conductivity. Generally, the amount of heat conducted is given by the following equation (1).

Q=K・A・_ΔT / _ΔX …(1) Here, Q: amount of heat transferred, K: thermal conductivity,
A: Area of the part where heat moves, _ΔX : Thickness of the material, _ΔT : Temperature difference at both ends of the thickness _ΔX of the material. Transforming equation (1), Δ _T = _Δ Correspondingly, _ΔX /K·A (=Rth) is called thermal resistance. The quality of heat conduction can be determined by the magnitude of this value. That is,
The thinner the thickness, the larger the area, and the larger the thermal conductivity, the smaller the thermal resistance (Rth). here,
Assuming that the heat generated in the power transistor 1 spreads in the 45° direction as shown in Figure 2 and is thermally diffused, the thermal resistance between W ₁ and W ₂ shown in the figure is given by the following equation (3). is given by

Rth=1/K∫ ^W _2W1 1/(2x+B) ² dx...(3) Calculating the thermal resistance of each element shown in Figure 1 using equation (3), Rth(1)=0.172℃/W( Power transistor: A=
_3mm ² , _Δ
m, K=0.63W/cm・℃), Rth(3)=0.248℃/W (Cu block layer; A=13
_mm ² , _Δ
=0.471W/cm・℃), Rth(5)=0.001℃/W (Cu conductor pattern; _ΔX =
3.5μm, K=3.88W/cm・℃), Rth(6)=0.571℃/W (epoxy resin insulation layer; Δ
_X = 25μm, K = 0.0035W/cm・℃), Rth(7) = 0.076℃/W (Al substrate; _ΔX = 2mm, K=
2.06W/cm・℃), total Rth=1.162℃/W.

The high temperature solder layer 2, the Cu block layer 3, and the insulating layer 6 account for a large proportion of these thermal resistances. Therefore, it can be seen that in order to lower the overall thermal resistance, it is necessary to lower these thermal resistances. However, among these, the high temperature solder layer 2
It is impossible to make it any thinner due to property problems such as TFT (thermal fatigue testing), and the thickness of the Cu block layer 3 is also made thinner because it plays the role of absorbing heat that is instantaneously generated. is also difficult. If the remaining insulating layer 6 is a conventionally used resin-based insulating layer, such as epoxy resin,
As mentioned above, it has the largest thermal resistance of 0.571°C/W. Therefore, it is most effective to lower the thermal resistance of this insulating layer 6. Conventionally, this resin-based insulating layer 6 has been coated with inorganic powder (for example, Al ₂ O ₃ , SiO ₂
There is also a method of increasing thermal conductivity by mixing in aluminum (e.g.), but due to adhesiveness with the Al substrate 6, it is
% is the limit. Moreover, since these inorganic powders are not continuously bonded in the resin but are dispersed, heat conduction is blocked by the resin layer, and the thermal conductivity can only be expected to improve by about twice as much at most.

In addition, it is possible to lower the thermal resistance by making this resin-based insulating layer 6 even thinner, but pinholes are likely to occur, and the thickness is limited to 25 mm from the viewpoint of withstand voltage characteristics.
The limit seems to be around μm. Moreover, this insulating layer 6
Because it uses epoxy resin, it has low heat resistance, and the maximum temperature for regular use is 100℃. Another fundamental problem is that when the insulating layer 6 has a thickness of 25 μm, a stray capacitance of about 140 pF/cm ² (C =ε _O
ε _S S/α, ε _O =8.855×10 ^-12 F/m, ε _S =4). In other words, when forming a hybrid integrated circuit,
A capacitance exists parasitically between each conductor in proportion to the area of each conductor, resulting in disadvantages such as the circuit itself becoming more likely to oscillate and the distortion rate increasing.

This invention was made in view of the above circumstances.
The purpose is to provide a hybrid integrated circuit that can effectively lower the thermal resistance of the entire circuit, has excellent heat resistance, and can perform stable operation.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. That is, as a means to eliminate the above-mentioned conventional drawbacks, this invention attempts to continuously deposit insulating ceramic on a metal substrate instead of a resin-based insulating layer, and form a circuit thereon. . In FIG. 4, 11 is a power transistor, 12 is a high-temperature solder layer, 13 is a Cu block layer,
14 is a solder layer, 15 is a Cu conductor pattern, 16 is an insulating layer of metal oxide such as Al ₂ O ₃ (alumina), 17 is an Al substrate, 18 is a heat sink, and 19 is a screw.

The thickness of the Al ₂ O ₃ insulating layer 16 is, for example, 100μ.
m, the thermal resistance Rth of the insulating layer 16 is 0.041°C/W (thermal conductivity K=
0.260W/cm・℃), which is approximately 1/14th of that of the conventional resin-based insulating layer (Rth=0.571℃/W).
Furthermore, its heat resistance is extremely high at 1,650°C, so it does not pose any practical problems for hybrid integrated circuits. moreover,
The stray capacitance that exists between the Al substrate 17 and the Cu conductor pattern 15 is 83 pF/cm ² , which is significantly reduced compared to the conventional resin-based insulating layer (140 pF/cm ² ), and prevents circuit oscillation. , it becomes possible to improve the distortion rate.

Next, a method of manufacturing the above hybrid integrated circuit will be explained. First, the surface of a pure Al substrate 17 with a thickness of 2 mm, for example, is roughened to 10 to 20 μm by spraying coarse powder of Al ₂ O ₃ . After that, within 30 minutes to 1 hour, use a plasma spraying device (for example, Metco 7M type manufactured by Daiichi Metco Co., Ltd.).
Al ₂ O ₃ is deposited to a thickness of 100 to 120 μm using a method to form an insulating layer 16 . Thermal spraying involves passing an inert gas, or a mixture of an inert gas and hydrogen or helium, between electrodes called a plasma spray gun, generating an electric arc and exciting the gas, creating a thermal plasma that can be adjusted up to 1600 degrees Celsius. In the flame generated by this thermal plasma, Al ₂ O ₃ with an average particle size of about 10 μm
Al substrate 1 was introduced with powder of Al ₂ O ₃ dissolved in it.
Attach it to 7. Next, on the Al substrate 17 on which Al ₂ O ₃ has been deposited to a thickness of 100 to 120 μm, a Cu paste (for example, ACP-030 manufactured by Asahi Chemical) is screen printed and baked at 150° C. for 30 minutes to form a Cu conductor pattern. form 15. Then, a solder layer 14 containing Cu is deposited on the Cu conductor pattern 15 on the Al substrate 17 at 230°C. Next, for example, the circuit diagram shown in FIG. 5 is formed on the Al substrate 17, and as shown in FIG. do.

FIG. 6 shows the relationship between the temperature on the Cu block layer and the output power when the conventional resin-based insulating layer 6 is used and when the Al ₂ O ₃ insulating layer 16 is used. In the same figure, ○A is the case of the resin-based insulating layer 6, and ○B is the case of the Al ₂ O ₃ insulating layer 16. This clearly shows that the Al ₂ O ₃ insulating layer 16 has better thermal conductivity than the resin-based insulating layer 6 (there is a difference of about 10° C. in temperature on the Cu block layer).

In the above embodiment, the insulating layer 16 is made of metal oxide Al ₂ O ₃ (K=0.260W/cm・℃, ε _S
= 9.4F/m), but other metal oxides, such as MgO・SiO ₂ (Steatite; K=
0.025, ε _S = 6.3), 2MgO・SiO ₂ (forsterite; K = 0.034, ε _S = 6.2), ZrO ₂・SiO ₂ (zircon; K = 0.050, ε _S = 8.8), MgO (magnesia; K = 0.363, ε _S = 5.6), BeO (beryria; K
= 1.173, ε _S = 6.4), TiO ₂ (titanium oxide; K =
0.121, ε _S = 8.6), etc. Furthermore, the material is not limited to metal oxides, but may also be metal nitrides, such as AlN (aluminum nitride; K=0.60, ε _S =8.9) and BN (boron nitride; K=0.287, ε _S =4.2).

As described above, according to the present invention, an insulating ceramic is continuously deposited on a metal substrate by a thermal spraying method, and a circuit is formed on this ceramic, so that thermal resistance can be significantly reduced. It also has excellent heat resistance. Therefore, the size of the Cu block layer can be reduced, and the operating temperature range of the device can be increased, so that the size of the hybrid integrated circuit can be made smaller than that of conventional circuits. Furthermore, since stray capacitance between the conductor and the substrate is reduced, it is effective in improving circuit stability and distortion rate, and is extremely effective in practice.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the configuration of a conventional hybrid integrated circuit, Figure 2 is a diagram illustrating the state of diffusion of heat generated in a power transistor, and Figures 3a and b are the formation of stray capacitance in the above circuit. 4 is a cross-sectional view showing the configuration of a hybrid integrated circuit according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of the insulating layer portion, b is an equivalent circuit diagram, and FIG. A specific electrical circuit diagram of the above circuit, FIG. 6, is a diagram showing the relationship between the output power and the temperature of the Cu block layer by comparing the circuits shown in FIGS. 1 and 4, respectively. DESCRIPTION OF SYMBOLS 11...Power transistor, 12...High temperature solder layer, 13...Cu block layer, 14...Solder layer, 15
...Cu conductor pattern, 16...Insulating layer (Al ₂ O ₃ ), 1
7...Al substrate, 18...heat sink.

Claims (1)

[Scope of Claims] 1. A metal substrate, an insulating ceramic layer deposited on the metal substrate by plasma spraying, a copper conductor pattern formed on the ceramic layer, and a copper conductor pattern formed on the copper conductor pattern. 1. A hybrid integrated circuit comprising: a copper block layer fixed to a semiconductor device through a solder layer; and a semiconductor element fixed onto the copper block layer via a solder layer.