Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS6236396B2 - - Google Patents
[go: Go Back, main page]

JPS6236396B2 - - Google Patents

Info

Publication number
JPS6236396B2
JPS6236396B2 JP53125574A JP12557478A JPS6236396B2 JP S6236396 B2 JPS6236396 B2 JP S6236396B2 JP 53125574 A JP53125574 A JP 53125574A JP 12557478 A JP12557478 A JP 12557478A JP S6236396 B2 JPS6236396 B2 JP S6236396B2
Authority
JP
Japan
Prior art keywords
resistor
polycrystalline silicon
resistance value
layer resistance
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53125574A
Other languages
Japanese (ja)
Other versions
JPS5552252A (en
Inventor
Kenjiro Mitake
Takashi Okuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12557478A priority Critical patent/JPS5552252A/en
Publication of JPS5552252A publication Critical patent/JPS5552252A/en
Publication of JPS6236396B2 publication Critical patent/JPS6236396B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体集積回路装置の抵抗体およびそ
の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resistor for a semiconductor integrated circuit device and a method for manufacturing the same.

半導体集積回路装置において、小さな面積内に
高い層抵抗値を有する抵抗体として、不純物を含
まない、ないしは微量しか含まない多結晶シリコ
ーンにより形成された抵抗体が用いられている。
2. Description of the Related Art In semiconductor integrated circuit devices, a resistor made of polycrystalline silicone that does not contain impurities or contains only a trace amount of impurities is used as a resistor that has a high layer resistance value within a small area.

従来のこの種の抵抗体は、一種類の層抵抗値を
有する知結晶シリコンからなるものであつた。ま
たその製造方法は、最初に多結晶シリコンを写真
食刻工程により配線部分と抵抗体部分を同時に形
成し、次に抵抗体と成る部分の上に不純物の添加
に対するマスクを写真食刻工程により設け、その
後不純物の添加を行なうと配線部分の多結晶シリ
コンには不純物が高濃度に添加され、マスクがあ
る部分の下の多結晶シリコンには不純物が添加さ
れずに高い抵抗値を有する抵抗体となる。
Conventional resistors of this type have been made of crystalline silicon having one type of layer resistance value. In addition, the manufacturing method involves first forming a wiring part and a resistor part at the same time in polycrystalline silicon using a photo-etching process, and then using a photo-etching process to form a mask for adding impurities over the part that will become the resistor. Then, when impurities are added, the impurities are added to the polycrystalline silicon in the wiring area at a high concentration, and the polycrystalline silicon under the mask area is not doped with impurities and becomes a resistor with a high resistance value. Become.

この従来技術によると、2種類以上の抵抗値を
得るには抵抗体の長さ又は幅を変えなければなら
ない。特に抵抗値の大きく違う2つ以上の抵抗体
を形成しようとした場合に抵抗値の小さな抵抗体
の幅を大きく、抵抗値の大きな抵抗体の長さを長
くしなければならなく、この事は、半導体集積回
路装置の面積を小さくすることの妨げになつてい
た。
According to this prior art, in order to obtain two or more types of resistance values, the length or width of the resistor must be changed. Especially when trying to form two or more resistors with significantly different resistance values, the width of the resistor with the lower resistance value must be increased and the length of the resistor with the higher resistance value must be increased. This has been an obstacle to reducing the area of semiconductor integrated circuit devices.

本発明は、抵抗値の異なる2種以上の抵抗体を
有する半導体集積回路装置において、抵抗体の所
要面積を減らし、集積度を高めることを目的とす
るものである。
An object of the present invention is to reduce the area required for the resistors and increase the degree of integration in a semiconductor integrated circuit device having two or more types of resistors having different resistance values.

本発明の半導体集積回路装置は、層抵抗値を異
にする多結晶シリコンからなる2種類以上の高抵
抗体を備えることを特徴とするものである。
The semiconductor integrated circuit device of the present invention is characterized by comprising two or more types of high resistance bodies made of polycrystalline silicon having different layer resistance values.

本発明の半導体集積回路装置の製造方法は、絶
縁膜を介して半導体基板上に一定濃度の不純物を
含む複数個の多結晶シリコンのパターンを形成す
る工程と、前記多結晶シリコンの表面を異なる厚
さだけ酸化することにより層抵抗値の異なる2種
類以上の抵抗体を形成する工程を含むことを特徴
とするものである。
The method for manufacturing a semiconductor integrated circuit device of the present invention includes the steps of forming a plurality of polycrystalline silicon patterns containing impurities at a constant concentration on a semiconductor substrate via an insulating film, and forming the surface of the polycrystalline silicon with different thicknesses. This method is characterized by including a step of forming two or more types of resistors having different layer resistance values by slight oxidation.

本発明によれば、層抵抗値を変えるだけで抵抗
値の異なる何種類もの抵抗体を得ることができる
ので、抵抗体の長さや幅を変える必要がなく、抵
抗体の所要面積を減らすことができ、半導体集積
回路装置の集積度を向上させることができる。
According to the present invention, many types of resistors with different resistance values can be obtained by simply changing the layer resistance value, so there is no need to change the length or width of the resistor, and the area required for the resistor can be reduced. Therefore, the degree of integration of the semiconductor integrated circuit device can be improved.

以下、本発明の実施例として、層抵抗値の異な
る3種類の抵抗体を備える半導体集積回路につい
て図面を参照して説明する。
EMBODIMENT OF THE INVENTION Hereinafter, as an example of the present invention, a semiconductor integrated circuit including three types of resistors having different layer resistance values will be described with reference to the drawings.

まず、第1図に示すように、シリコン基板1に
フイールド絶縁膜2を形成し、その上に多結晶シ
リコン3を化学気相成長法により全面に被着す
る。その後、この多結晶シリコンが層抵抗値の一
番高い抵抗体を形成するのに必要な層抵抗となる
ように不純物を添加する。この場合、多結晶シリ
コンを化学気相成長する時に、ソースガスに不純
物を添加し、所望の層抵抗の多結晶シリコンを被
着してもよい。
First, as shown in FIG. 1, a field insulating film 2 is formed on a silicon substrate 1, and polycrystalline silicon 3 is deposited on the entire surface thereof by chemical vapor deposition. Thereafter, impurities are added so that this polycrystalline silicon has a layer resistance necessary to form a resistor with the highest layer resistance value. In this case, when polycrystalline silicon is grown by chemical vapor deposition, impurities may be added to the source gas to deposit polycrystalline silicon having a desired layer resistance.

その後、第2図に示すように、多結晶シリコン
を写真食刻工程によりパターン化し、配線部分4
と抵抗体部となるべき部分を含む配線5を形成す
る。この場合ゲート部の多結晶シリコンを同時に
形成してもよい。
Thereafter, as shown in FIG. 2, the polycrystalline silicon is patterned using a photolithography process to
A wiring 5 including a portion to become a resistor portion is formed. In this case, the polycrystalline silicon of the gate portion may be formed at the same time.

次に、第3図に示すように、前記多結晶シリコ
ン5のうち、すべての抵抗体を形成する部分に熱
酸化マスク(SiO2)6を形成する。この場合、マ
スク6以外の部分を耐酸化物7(例えば窒化シリ
コン膜)で被つておき、マスク6の部分だけ多結
晶シリコンを酸化する。酸化膜厚は、後の工程で
行なわれる配線部多結晶シリコンへの不純物をド
ープする時に、マスク6の下の多結晶シリコンへ
不純物がドープされないだけの厚さが必要であ
る。マスク6によつて形成された抵抗体の層抵抗
値が、作ろうとする各種の層抵抗値のうち一番高
い層抵抗値となるような多結晶シリコンの不純物
濃度にしておく。尚、1番層抵抗値の高い抵抗体
を8、2番目に層抵抗値の高くなる抵抗体を9、
3番目に層抵抗値の高くなる抵抗体を10とす
る。
Next, as shown in FIG. 3, a thermal oxidation mask (SiO 2 ) 6 is formed on the portions of the polycrystalline silicon 5 where all the resistors will be formed. In this case, the portions other than the mask 6 are covered with an oxide resistant material 7 (for example, a silicon nitride film), and the polycrystalline silicon is oxidized only in the mask 6 portions. The oxide film needs to be thick enough to prevent the polycrystalline silicon under the mask 6 from being doped with impurities when the wiring polycrystalline silicon is doped with impurities in a later step. The impurity concentration of the polycrystalline silicon is set such that the layer resistance value of the resistor formed by the mask 6 is the highest layer resistance value among the various layer resistance values to be created. In addition, the resistor with the highest layer resistance value is 8, the resistor with the second highest layer resistance value is 9,
The resistor having the third highest layer resistance value is designated as 10.

次に第4図に示すように、耐酸化物7を除去
し、層抵抗値が2番目に高い抵抗体9と層抵抗値
が3番目に高い抵抗体10以外の部分に前記耐酸
化物7と同様の耐酸化物11を形成する。その
後、熱酸化すると、抵抗体9と抵抗体10の多結
晶シリコンの熱酸化が進み、熱酸化膜12の膜厚
が増加する。この時、抵抗体9と抵抗体10の多
結晶シリコン中では、不純物の偏析が進み、抵抗
体8に比較し、層抵抗値が小さくなる。これは、
不純物がSiO2中に入らずに多結晶シリコン中に
偏析するため抵抗体9,10において酸化膜との
界面近くの多結晶シリコン中に不純物の濃度が他
の部分の濃度より高い部分ができ、その部分が層
抵抗値を決定する要因となるため層抵抗値がさが
る。
Next, as shown in FIG. 4, the oxide resistor 7 is removed, and the same oxide resistor 7 is applied to the parts other than the resistor 9 having the second highest layer resistance value and the resistor 10 having the third highest layer resistance value. oxidation-resistant material 11 is formed. Thereafter, when thermal oxidation is performed, the polycrystalline silicon of the resistors 9 and 10 is thermally oxidized, and the thickness of the thermal oxide film 12 increases. At this time, impurity segregation progresses in the polycrystalline silicon of the resistors 9 and 10, and the layer resistance value becomes smaller than that of the resistor 8. this is,
Since the impurities do not enter SiO 2 and segregate in the polycrystalline silicon, there are parts of the polycrystalline silicon near the interface with the oxide film in the resistors 9 and 10 where the impurity concentration is higher than other parts. Since that portion becomes a factor that determines the layer resistance value, the layer resistance value decreases.

次に第5図に示すように、前工程と同様に、耐
酸化物11を除去し、層抵抗値が3番目に高い抵
抗体10以外の部分に、耐酸化物7と同様の耐酸
化物13を形成する。その後、熱酸化すると、抵
抗体10の多結晶シリコンの熱酸化が進み、熱酸
化膜14の膜厚が増加する。この時、抵抗体10
の多結晶シリコン中で不純物の偏析が進み、抵抗
体9に比較し、層抵抗値が小さくなる。
Next, as shown in FIG. 5, as in the previous step, the oxide resistant material 11 is removed, and an oxidized resistant material 13 similar to the oxidized material 7 is formed in the area other than the resistor 10 having the third highest layer resistance value. do. Thereafter, when thermal oxidation is performed, the polycrystalline silicon of the resistor 10 is thermally oxidized, and the thickness of the thermal oxide film 14 increases. At this time, resistor 10
Segregation of impurities progresses in the polycrystalline silicon of the resistor 9, and the layer resistance value becomes smaller than that of the resistor 9.

その後第6図に示すように、耐酸化物13を除
去し、多結晶シリコンに不純物をドーブすると、
抵抗体8,9,10の部分は各々マスク6,1
2,14により不純物がドープされずにそれ以外
の部分に不純物がドープされ配線部分となる。
After that, as shown in FIG. 6, the oxide resistor 13 is removed and the polycrystalline silicon is doped with impurities.
The resistor elements 8, 9, 10 are covered with masks 6, 1, respectively.
2 and 14, the impurity is not doped into the other portions and becomes a wiring portion.

上記実施例において、例えば多結晶シリコン中
に不純物としてリンを1×1014原子/cm2だけ添加
し、多結晶シリコンの酸化膜の厚さを3000Å、
5000Å、9000Åの3種類とした場合に、それぞれ
の層抵抗値は500〜1000kΩ/口、50〜100kΩ/
口、5〜10kΩ/口が得られる。この場合、多結
晶シリコンの厚さを6000Å、長さを10μm、幅を
5μmとしたとき、抵抗値はそれぞれ1〜2M
Ω、100〜200kΩ、10k〜20kΩとなる。
In the above example, for example, 1×10 14 atoms/cm 2 of phosphorus was added as an impurity into polycrystalline silicon, and the thickness of the polycrystalline silicon oxide film was increased to 3000 Å.
When using three types of 5000 Å and 9000 Å, the respective layer resistance values are 500 to 1000 kΩ/mouth and 50 to 100 kΩ/
mouth, 5-10 kΩ/mouth is obtained. In this case, when the thickness of polycrystalline silicon is 6000 Å, the length is 10 μm, and the width is 5 μm, the resistance value is 1 to 2 M.
Ω, 100 to 200kΩ, and 10k to 20kΩ.

この実施例では、酸化工程をくり返す毎に耐酸
化物を除去し、再び耐酸化物を被着しているが、
他の方法例えば写真食刻工程により、最初に一番
抵抗値の低くなる抵抗体の部分の耐酸化物を除去
して酸化し、次に二番目に抵抗値の低くなる抵抗
体の部分の耐酸化物を除去して酸化するというよ
うに、抵抗値が低くなる抵抗体の部分から順番に
耐酸化物を除去し酸化する事をくり返しても、実
施例と同じ結果が得られる。
In this example, each time the oxidation process is repeated, the oxidation resistant material is removed and the oxidation resistant material is deposited again.
Other methods, such as a photo-etching process, first remove and oxidize the oxidation resistant material on the part of the resistor that has the lowest resistance value, and then oxidize the oxidation resistant material on the part of the resistor that has the second lowest resistance value. Even if the oxidation-resistant material is removed and oxidized in order from the portion of the resistor where the resistance value decreases, the same result as in the example can be obtained.

尚、ここでは3種類の層抵抗値を有する抵抗体
を製造する場合について説明したが、2種類の層
抵抗値を有する抵抗体を製造する場合は第5図で
説明した工程を省略すればよい。又層抵抗値が4
種類以上の抵抗値を有する抵抗体を製造する場合
は、耐酸化物で被う抵抗体を変え第5図で説明し
た工程を追加すれば製造可能である。
Note that although the case of manufacturing a resistor having three types of layer resistance values has been described here, when manufacturing a resistor having two types of layer resistance values, the process explained in FIG. 5 may be omitted. . Also, the layer resistance value is 4
In the case of manufacturing a resistor having more than one type of resistance value, it is possible to manufacture the resistor by changing the resistor covered with the oxide resistant material and adding the process explained in FIG. 5.

又、多結晶シリコンの下の部分をフイールド絶
縁膜としたが、絶縁膜があれば、その下に素子や
配線があつても本発明の効果は影響をうけない。
又、絶縁物基板上に形成した多結晶シリコンに対
しても本発明の効果は同一である。
Further, although the portion under the polycrystalline silicon is made into a field insulating film, the effect of the present invention is not affected even if there is an element or wiring under the insulating film.
Furthermore, the effects of the present invention are the same for polycrystalline silicon formed on an insulating substrate.

以上のように、本発明では抵抗体となるべき部
分を含だ多結晶シリコン全体に不純物を添加して
おき、抵抗体となる部分に熱酸化膜を形成し、そ
の酸化膜厚を変えることにより多結晶シリコン中
の不純物の偏析の程度を変え、同一の大きさの抵
抗体で、2種類以上の層抵抗値を有する抵抗体を
製造することができる。この製造方法によれば層
抵抗値が大きく異なる抵抗体も同一の大きさで形
成することができるという利点があり、半導体集
積回路装置の抵抗体の所要面積を大幅に減少さ
せ、集積度を向上させることができる。
As described above, in the present invention, impurities are added to the entire polycrystalline silicon including the part that will become the resistor, a thermal oxide film is formed on the part that will become the resistor, and the thickness of the oxide film is changed. By changing the degree of segregation of impurities in polycrystalline silicon, it is possible to manufacture resistors of the same size having two or more types of layer resistance values. This manufacturing method has the advantage that resistors with significantly different layer resistance values can be formed in the same size, greatly reducing the area required for resistors in semiconductor integrated circuit devices and improving the degree of integration. can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第6図は本発明の実施例を説明するた
めの断面図である。ここで図中の符号は 1……基板、2……フイールド絶縁膜、3……
多結晶シリコン膜、4……配線多結晶シリコン、
5,8,9,10……抵抗体多結晶シリコン、
6,12,14……熱酸化膜、7,11,13…
…耐酸化物、である。
1 to 6 are cross-sectional views for explaining embodiments of the present invention. Here, the symbols in the figure are 1...Substrate, 2...Field insulating film, 3...
Polycrystalline silicon film, 4... Wiring polycrystalline silicon,
5, 8, 9, 10...Resistor polycrystalline silicon,
6, 12, 14... thermal oxide film, 7, 11, 13...
...It is an oxidation-resistant material.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁膜を介して半導体基板上に一定濃度の不
純物を含む複数個の多結晶シリコンのパターンを
形成する工程と、前記多結晶シリコンの表面を異
なる厚さだけ酸化することにより層抵抗値の異な
る2種類以上の抵抗体を形成する工程を含むこと
を特徴とする半導体集積回路装置の製造方法。
1 A step of forming a plurality of polycrystalline silicon patterns containing impurities at a constant concentration on a semiconductor substrate via an insulating film, and oxidizing the surface of the polycrystalline silicon by different thicknesses to create different layer resistance values. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming two or more types of resistors.
JP12557478A 1978-10-11 1978-10-11 Semiconductor integrated circuit device and manufacturing of them Granted JPS5552252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12557478A JPS5552252A (en) 1978-10-11 1978-10-11 Semiconductor integrated circuit device and manufacturing of them

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12557478A JPS5552252A (en) 1978-10-11 1978-10-11 Semiconductor integrated circuit device and manufacturing of them

Publications (2)

Publication Number Publication Date
JPS5552252A JPS5552252A (en) 1980-04-16
JPS6236396B2 true JPS6236396B2 (en) 1987-08-06

Family

ID=14913543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12557478A Granted JPS5552252A (en) 1978-10-11 1978-10-11 Semiconductor integrated circuit device and manufacturing of them

Country Status (1)

Country Link
JP (1) JPS5552252A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS629662A (en) * 1985-07-06 1987-01-17 Toshiba Corp Semiconductor device and manufacture thereof
JP3404064B2 (en) 1993-03-09 2003-05-06 株式会社日立製作所 Semiconductor device and manufacturing method thereof
US9704944B2 (en) * 2013-02-28 2017-07-11 Texas Instruments Deutschland Gmbh Three precision resistors of different sheet resistance at same level

Also Published As

Publication number Publication date
JPS5552252A (en) 1980-04-16

Similar Documents

Publication Publication Date Title
JPS5922380B2 (en) Handout Taisoshino Seizouhouhou
JPS6236396B2 (en)
JPS60208855A (en) Method of producing simultaneously semiconductor regions having different dopings
JPS6022502B2 (en) Manufacturing method of semiconductor device
JPH04112532A (en) Manufacturing method of semiconductor integrated circuit
JPS61191061A (en) Semiconductor resistor device
JPS63152164A (en) Semiconductor device
JP3147930B2 (en) Method for manufacturing polycrystalline silicon high resistance element
JPS5922381B2 (en) Handout Taisoshino Seizouhouhou
JP2989831B2 (en) Method for manufacturing semiconductor device
JPH0563143A (en) Resistance formation method
JPS6038872B2 (en) Manufacturing method of semiconductor device
JPS63296277A (en) Semiconductor integrated circuit device
JP2771999B2 (en) Method for manufacturing semiconductor device
JPH05315333A (en) Method for manufacturing semiconductor device
JPH02248068A (en) Manufacturing method of semiconductor device
CA1170783A (en) Method for making an integrated injection logic structure including a self-aligned base contact
JPS61248547A (en) Manufacture of semiconductor device
JPS6120154B2 (en)
JPS60145650A (en) Manufacture of thin film semiconductor device
JPS60124845A (en) Manufacture of semiconductor device
JPH03157925A (en) Manufacture of semiconductor device
JPS6018144B2 (en) Manufacturing method of semiconductor device
JPS628540A (en) Manufacture of semiconductor device
JPS61174649A (en) Semiconductor device