JPS6244473B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is directed to slicing information (hereinafter referred to as character data signal) superimposed on a predetermined horizontal scanning period of a television signal in a teletext receiver. The present invention relates to a data slicing circuit that can be used in cases where data is converted into a binary digital signal.

Conventional structure and problems The data signal of television teletext broadcasting is generally a binary NRZ signal, which is in the form of a data packet in units of one horizontal scanning period (1H) and is divided into vertical blanking periods of the television video signal. superimposed on

FIG. 1 shows a waveform diagram of a superimposed character data signal. 1 in FIG. 1A is a horizontal synchronizing signal, and 2 is a color burst signal. 3, 4, and 5 are binary signals to be superimposed, the portion 3 is a clock line signal (hereinafter abbreviated as CR signal), and 6 is an enlarged view of this. Part 4 is a framing code signal (hereinafter abbreviated as FC signal), and part 7 is an enlarged view of this. The CR signal is a synchronization signal for regenerating the data sampling clock, and the FC signal is a signal for synchronizing data packets. These signals are common to all multiplexed character data. Part 5 is a part that includes various data information.

As shown in FIG. 1B, the multiplexed data signal is band-limited and therefore forms a sinusoidal pulse train. Now, if the waveform in FIG. 1B is compared with the level shown by the dashed-dotted line 8 and sliced, the sliced output waveform will be as shown in FIG.
NRZ signal is played. In the character multiplex receiver, data is read by reading the sliced data using an appropriate sampling clock.

An example of a conventional circuit for creating the above slice level 8 and slicing the superimposed character data signal is shown in FIG. The antenna 9 receives the RF signal, and the video demodulator 10 outputs the television video signal 1 corresponding to FIG. 1A.
Get 1. This television composite video signal 11 is applied to one terminal of the voltage comparator 12, and further,
Applying the television composite video signal 11 to each of the positive peak detection circuit 13 and the negative peak detection circuit 14,
By applying the intermediate voltage between the outputs of the peak detection circuits 13 and 14 to the other terminal of the voltage comparator 12 as a slice level, the superimposed signal is reproduced into a binary digital signal.

However, in this method, the peak detection circuits 13, 1
4, when the RF input is small, noise peaks are detected, which often results in errors in reproducing the superimposed signal. Additionally, when waveform distortion occurs due to group delay characteristics of a video demodulator, it is often impossible to set an appropriate slice level to perform peak detection on the distorted waveform. be.

Purpose of the Invention The present invention eliminates such conventional drawbacks, has excellent anti-noise characteristics and group delay characteristics, and is capable of suppressing level fluctuations in the superimposed signal on the transmitting side and fluctuations in the signal amplitude of the detection output of the receiver. It is an object of the present invention to provide a data slicing circuit that can always provide an appropriate slicing level without adjustment and obtain good slicing characteristics. Furthermore, the present invention can be realized at low cost by configuring it with a circuit suitable for an integrated circuit.

Structure of the Invention As shown in Figure 1A, the first 16 bits of "1010..." (CR signal) of the character multiplex signal and the next 8 bits of "11100101" (FC signal) are This is a common signal for data. In the present invention, by passing the CR signal and FC signal parts common to all character multiplexed data through an integrating circuit,
Focusing on the fact that the average voltage is almost the center voltage of the data, this is held after FC detection and used as the slice voltage of the character data signal.

With this configuration, even if the RF input signal is small and the noise in the video demodulated signal increases,
The effect of the integrating circuit can suppress slice voltage noise. Furthermore, even if waveform distortion occurs due to deterioration of group delay characteristics of the video demodulator, the average voltage is not easily affected, so errors in reproduced data can be reduced.

Further, even if the output of the video demodulator varies, this average voltage becomes the average value of the data, that is, approximately the center voltage, so there is an advantage that no adjustment is required to determine the slice voltage. In addition, since it passes through an integrating circuit, the period until reaching the average value, that is,
In the first half of the CR signal, the sliced data width is irregular, but this can be improved by presetting the slice voltage to approximately the center voltage of the data immediately before the CR signal.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of this circuit. Figure 4,
FIG. 5 is a waveform diagram explaining the operation. Blocks that are the same as those in FIG. 2 are given the same numbers.

15 is a data slice circuit, 16 is an input terminal for a television composite video signal, 17 is an input terminal for a clamp pulse, 18 is an input terminal for an average value detection gate pulse, and 19 is an output terminal for slice data.

The television composite video signal output from the video demodulator 10 is input to the data slice circuit 15 through the input terminal 16, and is also input to the sync separation circuit 2.
0 (including horizontal AFC and horizontal oscillation circuit as necessary) and data sampling clock generation circuit 2
1.

FIG. 4 shows the timing relationship of the clamp pulse and the average value detection gate pulse with respect to the horizontal synchronization signal and character data signal of the television composite video signal input to the input terminal 16. Figure 4 D is the third
This is a television composite video signal input to the input terminal 16 in the figure, which is the same as that in FIG. 1A. 4E shows the horizontal sync pulse output from the sync separation circuit 20, and FIG. 4F shows the clamp pulse input to the input terminal 17, which triggers the mono multivibrator 22 at the trailing edge of the horizontal sync pulse E. It can be obtained by The pulse width is made as wide as possible without being affected by the CR signal shown in FIG. 4D. 4G is the average value detection gate pulse inputted to the input terminal 18, and is the average value detection gate pulse inputted to the input terminal 18.
3 at the trailing edge of the clamp pulse F and reset by the output pulse of the framing code detector 24. Here, since the framing code signal of the output pulse of the framing code detector 24 consists of the code "11100101" as shown in FIG. 1C, this code is built into the framing code detector 24 as a comparison pattern. This is obtained by reading the slice data with a data sampling clock and matching the detected framing code. When the framing code is correctly detected, the pulse G is output at the last bit of the framing code signal. In general, a text multiplex receiver starts reading subsequent data only after this framing code is detected.

The data slicing circuit 15 uses a television composite video signal D on which character data is superimposed, a clamp pulse F, and an average value detection gate pulse G to slice data in the manner described below.

The television composite video signal D, in which character data is multiplexed, input to the input terminal 16 is passed through a clamp circuit 25, where the pedestal level of the television composite video signal D is clamped by the clamp pulse F input from the input terminal 17. After clamping, it is amplified by an amplifier 26, and its output is divided into three,
One is supplied directly to one input terminal of voltage comparator 27. One of the other two is input to the integrator 29 through the analog gate 28, and the other is input to the integrator 29 through the level shift circuit 30 and the analog gate 31. The output waveform of the integrator 29 at that time is shown in FIG. 5H. In FIG. 5H, t ₁ is the period of the clamp pulse F, t ₂ is the period of the average value detection gate pulse G, and the analog gates 31 and 28 are respectively
Indicates the period during which the is closed. Further, a in FIG. 5H is the output waveform of the amplifier 26, and the CR signal and FC signal portions are shown enlarged.

Here, considering the case where the level shift circuit 30 and the analog gate 31 are not provided, the analog gate 28 is conductive during the period t ₂ and the waveform a is integrated by the integrator 29. After t ₂ , analog gate 28 is opened and the last voltage at t ₂ is held. Integrator 2
If an integrator 29 whose step response is approximately constant during the period of the CR signal is used, an output like b in FIG. 5H is obtained as the output of the integrator 29.
That is, b converges to the intermediate level of the superimposed data during the CR period, and maintains almost the intermediate level during the FC signal period, although it is slightly higher because the FC signal is "11100101".
After that, that level is held. Therefore, by supplying the signal b to the other input terminal of the voltage comparator 27, slicing the waveform a and shaping it in the pulse shaping circuit 32, the sliced character data as shown in FIG. The signal is output terminal 19
More can be obtained.

Next, if there is a level shift circuit 30 and an analog gate ₃₁ , the analog gate 31
conducts, and the level shift circuit 3 changes the pedestal voltage.
An integrator 29 is configured with the voltage increased by 0, and the capacitor is charged and preset. During period t ₂ , analog gate 31 is open and analog gate 2
8 becomes conductive, the integration operation starts from the preset voltage, and the same operation as described above is performed. If the output impedance of the analog gate 31 during conduction is selected to be sufficiently small so that the output of the integrator 29 rises by the level shift amount of the level shift circuit 30 during the period _t1 , the output of the integrator 29 at this time In this case, an output as shown in c in FIG. 5H is obtained, and the output of the character data signal after slicing is as shown in FIG. 5J. d in FIG. 5H indicates the level shift amount of the level shift circuit 30,
The duty ratio of the CR signal after slicing may be set to be close to 50% throughout.

When comparing I and J, there is no difference after the FC signal, and it can be said that the bit error rates of the data portion are the same. However, when the framing code detector 24 detects the framing code, in the I waveform, especially the first half of the CR signal becomes similar to the FC signal pattern, so the RF input becomes weak and the detected television composite image When the signal-to-noise ratio of the signal deteriorates, there is a high probability that the first half of the CR signal will be mistakenly detected as a framing code. If the framing code is detected erroneously, the subsequent data will be read incorrectly, resulting in defects such as line omissions in pattern transmission type teletext broadcasting and line omissions in code type teletext broadcasting.

This characteristic can be greatly improved by presetting the front part of the CR signal to approximately the intermediate level of the data amplitude, as shown in c in FIG. When the framing code is "11100101" as in the Japanese system, the level width of "1" in the first half of the CR signal is narrowed by setting the level a little higher than the intermediate level, making it easier to detect incorrect framing codes. It becomes difficult to do.

FIG. 6 shows the data slice circuit 15 in FIG.
This is a specific example of a circuit in which the part shown in FIG. The same parts as in FIG. 3 are designated by the same numbers. Bias power supply blocks 33 and 34 supply the necessary voltage and current to each part of this circuit. In particular, 34 uses a Zener diode D ₁ and temperature compensation transistors Q ₄₃ and Q ₄₄ to keep the emitter voltage V _Z of the transistor Q ₄₁ unchanged even when power supply fluctuations or temperature changes occur.

35 is a power supply for this circuit, to which, for example, 12V is applied. Further, 36 is a power supply that determines the amplitude of the sliced character data signal output, and when the output is connected to TTL, 5V is selected.

The television composite video signal on which the character data signal is superimposed is transmitted through the input terminal 16 and capacitor _C1 to transistors _Q9 , _Q10 , resistors _R11 , _R12 , _R13.
The signal is input to a differential amplifier consisting of: capacitor
C ₁ also serves as a clamp capacitor, and when a clamp pulse is input to input terminal 17, transistor Q ₇ or Q ₈ becomes conductive, and the pedestal portion of the signal input to the base of transistor Q ₉ is transferred to the emitter of transistor Q ₃ . Clamp to voltage (V ₁ ).
On the other hand, the base bias of the transistor Q ₁₀ is determined to be the voltage (V ₂ ) midway between the character data signal section as shown in FIG. By determining the bias in this way, the dynamic range of the differential amplifier 26 can be maximized. This is because the function of this amplifier is only to be able to amplify the signal portion of character data.

Furthermore, as shown in FIG. 1B, the character data signal before slicing is band-limited and has a blunted waveform, so the amplitude of the signal when slicing should be as large as the power supply voltage 35 allows. The larger it is, the better the phase jitter after slicing will be.

The clamp circuit 25 is effective as a means for maximizing the dynamic range of the character data signal _.
When input to the voltage comparison circuit 27 by AC coupling, the dynamic range is narrowed due to changes in the average level of the video signal, and the amplitude of character data that can be input to the voltage comparator circuit 27 is limited. The amplified output obtained from the collector of transistor _Q10 is divided into three parts through emitter-follower transistor _Q12 , and one is inputted to one input terminal of voltage comparator 27 (base of transistor _Q34 ) through level shift diode _Q13 . be done. A level shift diode _Q13 is inserted to compensate for a voltage drop between the base and emitter of a transistor _Q31 , which will be described later. One of the latter two is input to the base of transistor _Q24 , and the other to the base of transistor _Q22 .

The analog gate 28 is constituted by the transistors Q ₂₃ to Q ₃₀ and the resistors R ₂₁ to _{R 23} , and a pulse that becomes high level during the period t ₂ in FIG. 5H is applied to the input terminal 18. This pulse causes transistor Q ₂₉ ,
Q ₂₇ and Q ₂₅ are on (Q ₂₈ and Q ₂₅ are off), and the base input signal of transistor Q ₂₄ is
Resistor R ₂₄ , R ₂₅ , capacitor through Q ₂₄ , Q ₂₇
C ₂ and coil L ₁ is input to an integrator 29. When the input pulse at input terminal 18 becomes low level, transistor Q ₂₉ turns off, and transistor Q ₂₈
turns on. Therefore, the base of transistor Q ₂₅ becomes a low voltage, so transistor Q ₂₅ is turned on, transistor Q ₂₄ is turned off, and the base of transistor Q ₂₇ becomes a low voltage. Since the emitter of the transistor Q ₂₇ is connected to the capacitor C ₂ and has the integrated voltage, the base and emitter of the transistor Q ₂₇ are reverse biased, and the transistor Q ₂₇ is turned off.
The potential of capacitor _C2 is maintained. Charge capacitor C ₂ due to base current to transistor Q ₃₁
However, by reducing the current value of the emitter current source of transistor Q ₃₁ (consisting of transistor Q ₃₂ and resistor R ₂₆ ) and increasing the value of capacitor C ₂ as much as possible, the potential due to the above discharge can be reduced. The voltage drop can be suppressed to a negligible range.

The output of the integrator 29 is applied to the other input terminal of the voltage comparator 27 (base of the transistor Q ₃₅ ) through the emitter follower transistor Q ₃₁ .
A sliced character data signal can be obtained as the output of the circuit. This is further shaped by a pulse shaping transistor Q ₃₈ and an inverter 37 and output.

Note that the transistor Q ₃₆ in the voltage comparator 27,
Q ₃₇ is an active load, transistor Q ₃₇ and resistor
The circuit consisting of R ₂₇ constitutes the current source of this circuit.

Also, resistors R ₂₄ , R ₂₅ , capacitor C ₂ , coil
The integrator consisting of L ₁ has each constant value R,
If r, C, and L, the transfer function G(S) is G(S) = (L/r)S+1/S ² LC(1+R/r)+S(CR
+L/r)+1...(1) The values of R, r, L, and C may be determined so that the step response of G(S) becomes a substantially constant value during the period of the CR signal.

Then the signal input to transistor Q ₂₂ is
During the _period when the clamp pulse input to the input terminal ₁₇ is at _a high level (period _{t 1} in FIG _.
(off), the level is shifted by the voltage drop across resistor _R19 , and the resulting voltage is charged to capacitor _C2 of integrator 29 through transistor _Q16 and resistor _R20 . If the resistor R ₂₀ is selected to be small, the capacitor C ₂ can be charged and raised to the level-shifted voltage within the period t ₁ described above. analog gate 28
In the same way as explained above, when the input to the input terminal 17 becomes low level, transistors Q ₁₇ and Q ₂₁ turn on, transistors Q ₁₈ , Q ₂₂ .Q ₁₆ turn off, and the level shift is cut off from the capacitor C ₂ . It can be done. As a result, the output of the integrator 29 is H
The waveform becomes as shown in c of FIG. 5, and as slice data output, slice data with a duty close to 50% is obtained from the front part of the CR signal as shown in FIG. 5J.

Furthermore, the amount of level shift obtained from the voltage across the resistor R ₁₉ will not change even with power supply fluctuations or temperature changes by supplying the current flowing through the resistor R ₁₉ through a current mirror circuit of transistors Q ₂₀ and Q ₃₉ . I'm trying not to do that. That is, if the base current of the transistor is ignored, the voltage V _S across the resistor R ₁₉ is: V _S =V _Z /R ₃₀ ×R ₂₉ /R ₁₈ ×R ₁₉ =R ₂₉・
R ₁₉ /R ₃₀ ·R ₁₈ V _Z (2) As mentioned above, since V _Z does not change due to power supply fluctuations or temperature changes, V _S divided by the resistance ratio also does not change. On the other hand, the character data to be compared does not change even if there are power fluctuations or temperature changes because the degree of amplification of the amplifier 26 is determined by the ratio of the resistance (R ₁₂ + R ₁₃ ) and R ₁₁ , so it is not affected by external changes. It can be a stable slice voltage preset.

Effects of the Invention As described above, according to the present invention, firstly, since the data slice level is created using an integrator, the integrator circuit has the effect of averaging noise, so that the RF input signal is Even when a lot of noise is mixed in, as when the slice level is small, the slice level is less likely to be affected. Furthermore, since the integrating circuit used in the present invention is a linear circuit, its output is not easily affected by waveform distortion caused by group delay distortion of the video demodulator, etc., and good slice characteristics with few errors can be obtained. .

Second, even if there are variations in the level of the superimposed signal on the transmitting side or the signal amplitude of the video detection output of the receiver, the average value (slice level) after passing through the integrator is the amplitude of the character data signal. Since it converges to the average value, that is, the intermediate level, there is no need for adjustment even if there is the above fluctuation.

Third, by presetting the slice voltage to approximately the mid-level of the character data signal before passing it through the integrator, the time required to ramp it up to the average level of the character data signal through the integrator can be made very short. The probability of erroneous FC detection, which tends to occur in the first half of a CR signal, can be significantly reduced. Further, according to the circuit of the present invention, the preset voltage can be made very stable against power supply fluctuations and temperature changes.

Fourth, because the character data signal before slicing is band-limited and sluggish as described above, if the amplitude at the time of slicing is small, the slice data is likely to jitter due to fluctuations in the slice level due to noise, etc. The above amplification can be achieved by clamping and amplifying the pedestal portion of the input video signal as in the present invention so that the center operating point of the amplifier does not change even if the average level of the video signal changes. The dynamic range for the character data signal portion of the device can be increased, the amplification degree can also be increased, and jitter after slicing can be reduced.

Fifth, the circuit of the present invention is a circuit that is easy to integrate except for the integrator portion, and therefore, it can be obtained at a very low cost by fabricating it with an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of a character data signal multiplexed into a television signal, FIG. 2 is a block diagram of a conventional data slicing circuit, and FIG. 3 is a block diagram of a data slicing circuit according to an embodiment of the present invention. ,
Figures 4 and 5 are waveform diagrams for explaining its operation, Figure 6 is a circuit diagram of a part of the specific circuit, and Figure 7 is a diagram of the specific circuit.
The figure is a waveform diagram for explaining the operating points of the amplifier therein. 3, 6...Clock run-in signal, 4, 7...
Framing code signal, 9...Antenna, 10
...Video demodulator, 11...Television composite video signal, 15...Data slice circuit, 16...Television composite video input terminal, 17...Clamp pulse input terminal, 18...Average value detection gate pulse input terminal , 19...slice data output terminal,
20... Synchronization separation circuit, 21... Data sampling clock generation circuit, 22... Mono multi, 2
3...Flip-flop, 24...Framing code detector, 25...Clamp circuit, 26...
Amplifier, 27... Voltage comparator, 28... First analog gate, 29... Integrator, 30... Level shift circuit, 31... Second analog gate, 3
2... Pulse shaping circuit, 33, 34... Bias power supply, 37... Inverter.

Claims (1)

[Claims] 1. Data for receiving a first binary signal that is superimposed on a predetermined horizontal scanning period of a television signal and subjected to a band limit, and slicing it to reproduce a second binary signal. The data slicing circuit includes amplifying means for amplifying the composite video signal on which the first binary signal is superimposed to obtain a third signal, and amplifying means for amplifying the composite video signal on which the first binary signal is superimposed to obtain a third signal; The output is supplied to the integrator through the gate, and during the period when the first analog gate is closed, the output is integrated according to the input of the integrator, and after the first analog gate is opened, the output is supplied to the integrator just before it is opened. means for obtaining a fourth signal holding the output of the third signal, means for level-shifting the third signal by a constant voltage, and passing the level-shifted signal through a second analog gate to adjust the luminance at the rear of the horizontal synchronization signal. means for setting a fourth signal output of the integrator to the pedestal level for a certain period when the signal is at the pedestal level; and means for comparing the voltages of the third signal and the fourth signal and outputting the voltage as the voltage comparison output signal. Second
A data slicing circuit comprising: a voltage comparator for reproducing a binary signal. 2. The data slice circuit according to claim 1, wherein the amplification means includes means for clamping the input signal so that the first binary signal can be amplified to the maximum extent.