JPS6244658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a highly integrated logic device such as an LSI, which has a circuit in which tri-state gate outputs are commonly connected in order to reduce the number of input/output terminals. When a flip-flop (hereinafter referred to as FF) that controls a gate is subject to so-called scan-in/out, multiple commonly connected tri-state gates are simultaneously enabled (so-called bus fight state). The purpose is to prevent element destruction and to improve the degree of freedom in diagnosis.

In highly integrated logic devices, multiple types of signals (for example, data and address, or upper data and lower data, etc.) can multiplex one set of terminals in order to make effective use of input/output terminals. will be carried out. One way to do this is to connect the outputs of the tristate gates in common (wired-OR) and enable only one tristate gate at a time, leaving the others in a high impedance state.

In addition, in order to diagnose such a highly integrated device, a means for serially connecting the FF groups included therein is provided separately from the connection for its original function, and during diagnosis, A desired pattern of "1" and "0" is shifted in to the FFs connected in series to perform a diagnostic operation, and the result is then shifted out by connecting the FFs in series again, a so-called scan in/out. It is.

By the way, the control signal for the above-mentioned tri-state gate is generated directly or indirectly by the FF, and the FF is generally included in the scan-in/out target. and during normal operation these
The value of FF should be such that two or more tristate gates are not enabled at the same time, but what value is temporarily set during the scan in/out operation is not guaranteed. Not as long as the. And if two or more tristate gates are enabled at the same time and their output data is different, there is a risk of device destruction.

Also, as a method of diagnosis, if a series of operations can be performed with only a specific tristate gate enabled, detailed diagnosis will be possible, but the control FF for this will naturally also need to be scanned in/out. However, it is difficult to guarantee the value during scan operation.

The present invention aims to solve these problems, prevent bus fights, and enable only an arbitrary tristate gate to operate during diagnosis. This will be explained in detail below with reference to the drawings.

Figure 1 is an example of a circuit using conventional tri-state gates, where 1, 2, and 3 are tri-states, 4 to 8 are FFs, 9 is an OR gate, and 10 are tri-state gates.
indicates a wired or (actually just a common connection). FFs 5 to 7 are FFs used to control tristate gates 1 to 3, respectively;
Also, FF4 and FF8 are FFs for other controls.
Under normal conditions, FFs 5 to 7 are not turned on at the same time. However, depending on the setting pattern for other FF, scan
During the in/out process, it is possible that a plurality of FFs 5 to 7 are turned on, and in that case, a so-called bus fight may occur and the elements of tristate gates 1 to 3 may be destroyed.

FIG. 2 is a circuit diagram of one embodiment of the present invention.
The same symbols as in the figure indicate the same thing, and 11, 1
2 is a control FF provided according to the present invention, and 13 regards the output from the control FFs 11 and 12 as a binary number, decodes it, and turns on only one of the plurality of output lines. This is the so-called nC ₁ decoder.

For example, if the input binary number is 2 bits, there are four output lines, and only the first to fourth lines are turned on, corresponding to the input binary value "00" to "11", and the others are turned off. , here, on and off mean, for example, logical values "1" and "0"). 14 to 16 are AND gates, and 17 to 19 are gates as shown in FIG. FFs 11 and 12 are also included in the scan in/out target and are connected in series with FFs 4 to 8.

In the above embodiment, four types of states can exist depending on the combination of two conditions: whether or not a test is in progress and whether or not a scan is in progress. First, in a state where neither a test nor a scan is in progress, that is, in a normal operating state, as is clear from FIG. Therefore, the output of NOR gate 161 becomes "1" and the output of gate 17 becomes "1". Similarly, the outputs of gates 18 and 19 become "1", and tristate gates 1-3 are controlled according to the values of FFs 5-7.

Also, if you are not testing but scanning,
That is, if it happens to be necessary to scan out the internal state during normal operation, as is clear from FIG. 3, since TEST=0, the output of the AND gate 162 that inverts one input will be "0", and since SCAN=1, the output of the NOR gate 161 becomes "0". Similarly, the outputs of gates 18 and 19 also become "0". That is, all tristate gates 1-3 are disabled. Therefore, no matter what values temporarily appear in FFs 5 to 7 during the scan operation, the tristate gate input to wired OR 10 is in a high impedance state. Further, when testing is in progress and not scanning, since TEST=1, the output of the AND gate 162 with one input inverted becomes the same as the output of the _nC1 decoder 13. Because SCAN=0,
The output of NOR gate 161 becomes the same as the output of _nC1 decoder 13, and depending on the values of FF55-7, one of the tristate gates can be controlled to test the operation of the logic device. Similarly, if you are testing and scanning,
Because TEST=1, one input was inverted.
The output of the AND gate 162 is the same as the output of the _nC1 decoder 13, and since SCAN=1, the NOR161
The output of gate 17 is “0” and the output of gate 17 is “0”
becomes. Similarly, the outputs of gates 18 and 19 are also “0”
becomes. Therefore, similarly to the above, wired OR 10
becomes a high impedance state.

According to the embodiment as described above, the gates 14 to 16
By providing gates 17 to 19 and inhibiting control signals during the scan operation, the wired OR 10 enters a high impedance state. Furthermore, even if the pattern set in FF11 and FF12 is a wrong pattern during testing, by using _nC1 logic via decoder 13, at most only one output of decoder 13 is turned on. Among them, prevention of bus fights is guaranteed.

FIG. 4 is a schematic block diagram showing another embodiment of the present invention, where 20 is a general FF such as FFs 4 to 8 in FIG. 2, and 21 is a general FF such as FF 11 in FIG.
22 and 23 are FFs for controlling a group of commonly connected tri-state gates such as ~12, 24-26 are FFs for controlling another group of tri-state gates similar to those shown in FIG. Control FF groups 21 to 23 corresponding to the decoder 13 of
This is a decoding circuit in which a general FF group 20 and all control FF groups 21 to 23 are connected in series and scanned in/out.

Figure 5 shows a general FF group 20 and a diagnostic control FF group 2.
This is another embodiment of the present invention in which the scan operation is performed by dividing the signals 1 to 23 by a multiplexer 27.

As described above, in the present invention,
By providing the FFs 11 and 12 and the gates 14 to 16, it is possible to designate a desired tristate gate and perform detailed testing. In addition, by providing gates 17 to 19 and disabling all tristate gates during scanning, bus fights due to transient confusion of FF values that may occur during scanning are prevented, and nC ₁ decoder 13 By providing FF1
Even if there is an error in the scan-in pattern to 1 or 12, bus fights are guaranteed to be prevented, and this is highly effective in diagnosing highly integrated LSIs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional example of a logic device using tri-state gates, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a partial detailed circuit diagram of Fig. 2, and Fig. 4 5 is a schematic block diagram of another embodiment of the present invention, and FIG. 5 is a schematic block diagram of still another embodiment of the present invention. In Fig. 2, 1 to 3 are tri-state gates, 4 to 8 are FFs, 9 is an OR gate, 10 is a wired OR gate, 11 and 12 are FFs for control during diagnosis,
13 is nC ₁ decoder, 17 to 19 are gates, 16
1,171 is a NOR gate, 162,172 is 1
AND gate with input inversion.

Claims (1)

[Claims] 1. A first group of flip-flops to be scanned in or scanned out, controlled by the outputs of the first group of flip-flops, and whose outputs are commonly connected. a logic device having a plurality of tri-state gates, a second group of flip-flops to be scanned in; an _nC1 decoder circuit for decoding the outputs of the second group of flip-flops;
a first gate means that completely disables the output of the _nC1 decoder circuit during scan operation, transmits it as is during diagnosis, and enables all outputs when neither diagnosis nor scan operation is performed; Accordingly, a logic device comprising second gate means for respectively gating the outputs of the first group of flip-flops and applying the gates to each of the tristate gates.