JPS6245735B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM stereo demodulation circuit that multiplies a composite signal by a switching signal and thereby performs an FM demodulation operation, and in particular reduces odd harmonics of an output signal and This invention relates to an FM stereo demodulation circuit that reduces crosstalk components.

As is well known, in a switching type FM stereo demodulation circuit, the switching signal s(t)
As such, a 38KHz sine wave synchronized with the subcarrier is preferable.

However, in reality, it is difficult to obtain such a sine wave multiplier with ideal linearity. Conventionally, as shown in Fig. 1, the composite signal Ei is split into two systems, and then the switching elements TR1 and TR2 convert the composite signal Ei into a rectangular waveform with a duty ratio of 50% and a frequency of 38 KHz as shown in Fig. 2. The signal is multiplied by the switching signal s(t), and the audio component included in the multiplication result is extracted by low-pass filters F1 and F2.

In this case, the composite signal Ei (excluding the pilot signal) is expressed as Ei = (L + R) + (L - R) sinωt (ω: subcarrier frequency), and the switching signal s
If the square wave with a duty ratio of 50% used as (t) is expressed as s(t)=1/2±(2/π)sinωt±(2/3π)sin3ωt±..., these multiplication results Ei・s(t)
The value of is Ei·s(t)={(L+R)+(LR)sinωt}·{1/2±(2/π)sinωt±(2/3π)sin3ωt±...}.

Therefore, as the composite signal Ei, 3ω,
When frequency components such as 5ω are included, demodulation sensitivity is also achieved for these.

In this way, if a square wave with a duty ratio of 50% is used as the switching signal s(t), for example, 114KHz (38KHz x 3), 190KHz
(38KHz x 5)
As shown in the figure, it has relatively high demodulation sensitivity. Therefore, during FM detection output, 3ω,
If a frequency component such as 5ω is included, the S/N
This appears as effects such as deterioration of the ratio and beat interference.

Therefore, a method is used to attenuate these bands in the FM detection output using a filter, but this method reduces the flatness (both amplitude and phase) up to 53KHz, which is the subcarrier region. Therefore, there is a problem that the frequency characteristics of the stereo separation after demodulation deteriorate.

Furthermore, if the audio component (for example, the left side component) is extracted from the equation for the multiplication result above using a low-pass filter, it becomes (1/2 + 1/π)L + (1/2 - 1/π)R, and from the top of the equation, (1 /2−1/π)R crosstalk component is generated. As a result, if a rectangular wave with a duty ratio of 50% is used as the switching signal s(t) as described above, there is an essential problem in that the maximum separation degree in principle cannot be improved to 13 dB or more.

This invention was made to solve the above problem, and its purpose is to improve the S/N ratio even when frequency components such as 3ω and 5ω are included in the FM detection output. The objective is to prevent effects such as deterioration and beat disturbance from occurring, and further to significantly reduce the aforementioned crosstalk components and improve the degree of stereo separation.

In order to achieve the above object, the first invention of this application simultaneously level-shifts an input composite signal to opposite polarities at a shift ratio of 3:1 to generate two systems of signals. a resistor voltage divider circuit that divides the output potential difference between both systems of the level shift circuit into a plurality of voltage levels corresponding to each time-division instantaneous value of the reference sine wave; and the resistor voltage divider circuit. a first analog multiplexer that sequentially outputs each divided voltage output value of the resistor voltage divider circuit in synchronization with the pilot signal in the composite signal and scans back and forth every half cycle; , a second analog multiplexer that is synchronized with the pilot signal in the composite signal and that scans back and forth every half period of the first analog multiplexer and sequentially outputs the signal with a phase difference of 180 degrees with respect to the scanning timing of the first analog multiplexer; The present invention is characterized in that it includes the following: and extracts left and right demodulated outputs from the first and second analog multiplexers.

A second invention of this application, in order to achieve the above object, includes one left and right level shift circuit for adding a DC component by shifting the level of an input composite signal by a certain amount to the positive side; In synchronization with the pilot signal in the composite signal, the signal is alternately leveled at a shift ratio of 3:1 (however, the DC component level is 1) to opposite polarities every half cycle. one level inversion circuit on each of the left and right sides to be shifted, and a potential difference between the output voltage of the left level shift circuit and the output voltage of the left level inversion circuit to a plurality of voltage levels corresponding to time-division instantaneous values of the reference sine wave. a left resistive voltage divider circuit that divides the voltage, and a right side resistor voltage divider circuit that divides the potential difference between the output voltage of the right level shift circuit and the output voltage of the right level inversion circuit into a plurality of voltage levels corresponding to time-division instantaneous values of the reference sine wave. a resistive voltage divider circuit; and a left analog multiplexer that selectively outputs each divided voltage output value of the left resistive voltage divider circuit by sequentially scanning it back and forth every half cycle in synchronization with the pilot signal in the composite signal. and a right-side analog multiplexer that selectively outputs each divided voltage output value of the right-side resistive voltage divider circuit in synchronization with a pilot signal in the composite signal by sequentially reciprocally scanning it every half cycle, and either the level inversion operation in the left and right level inversion circuits or the scanning operation of the left and right analog multiplexers has a phase difference of 180° between the left side and the right side, and left and right demodulation is performed from the left and right analog multiplexers. It is characterized by extracting output.

Embodiments of the first invention will be described in detail below with reference to the accompanying drawings.

First, the basic principle of the stereo demodulation circuit according to the present invention will be explained with reference to FIGS. 4 and 5.

The basic principle of the circuit of the present invention is as shown in FIG.
For the composite signal Ei, a switching signal s containing at least a frequency component of 1+2 sinωt
(t) is multiplied by a switching signal s(t)' containing at least a frequency component of 1-2 sinωt, and Ei(1+
2 sin ωt) and Ei (1−2 sin ωt) as demodulated outputs.

Then, each of the above-mentioned switching signals s(t),
As s(t)', for example, a substantially sinusoidal staircase wave having a positive side to negative side ratio of +3 to -1 as shown in FIG. 5 is used. Furthermore, these switching signals s(t) and s(t)' have the same frequency as the subcarrier. These switching signals s(t) and s(t)' are converted into composite signals.
By multiplying by Ei, the crosstalk components included in the left and right demodulated outputs can be reduced to 0 in principle. This is proved as follows.

First, the demodulated signal derived to the output terminal L is fL
(t), then fL(t)=Ei(1+2sinωt).

Also, the value of the composite signal Ei is Ei=L+R+(L-R) sinωt It is expressed as

Therefore, the above fL(t) becomes fL(t)={L+R+(L-R)sinωt}×(1+2sinωt)=L(2+3sinωt−cos2ωt)+R(sinωt+cos2ωt), and from this, the audio component is processed using LPF. If we take it out, fL(t) = 2L, which proves that the crosstalk from the right side system is completely eliminated.

Similarly, for the composite signal Ei,
Multiplying by (1-2sinωt), fR(t)={L+R(L-R)sinωt}×(1-2sinωt)=L(cos2ωt-sinωt) +R(2-3sinωt-cos2ωt) From this, the audio If the signal is extracted using the LPF, fR(t) = 2R, which proves that the crosstalk component from the left system is completely removed.

Further, in the present invention, a multiplication circuit constituted by a composite signal level shift circuit, a resistance ladder circuit, and an analog multiplexer is used as each multiplication means shown in FIG. This multiplier circuit does not require consideration of the nonlinearity of the multiplier, unlike when using a conventional multiplier, and therefore can convert a substantially sinusoidal staircase wave signal as shown in FIG. The signal Ei can be multiplied.

Next, FIG. 6 is an electric circuit diagram showing a specific embodiment of the first invention, and FIG. 7 is a waveform diagram showing signal states at various parts in FIG. 6. In FIG. 6, a composite signal Ei supplied to the input terminal IN is supplied to two operational amplifiers OP1 and OP2 constituting a level shift circuit.

Operational amplifier OP1 outputs the composite signal Ei with a level shift of +3 times, and
In OP2, the level of the composite signal Ei is shifted by -1 times and outputted. These operational amplifiers OP
The outputs of 1 and OP2 are applied to both ends of a resistor ladder circuit LAD consisting of resistors r1 to r7.

At both ends of the resistor ladder LAD and at each connection point,
Analog switches S1 to S8 forming a first analog multiplexer and analog switches S9 to S16 forming a second analog multiplexer
are connected to each other, and by these analog multiplexers, each divided voltage output of the resistor ladder circuit LAD is selectively led out to two operational amplifiers OP3 and OP4 constituting a buffer, respectively. The outputs of these buffers OP3 and OP4 are the left demodulation output terminal OUTL and the right demodulation output terminal OUTL.
Output to OUTR.

On the other hand, the analog switches S1 to S16 constituting each of the analog multiplexers are selectively turned on or turned off by switching pulses output from a switching pulse generation circuit SP, which will be described later. The switching pulse generation circuit SP is
It is structured as follows.

Voltage controlled oscillator circuit (hereinafter referred to as VCO) 1
The oscillation frequency of BCD/U/D counter 2,
BCD decimal decoder 3, NAND gate 4,
It is locked to 532KHz by a phase locked loop consisting of 5, 6, D-type flip-flops 7, 8, a phase detector 9, and a DC amplifier 10.

The BCD/U/D counter 2 counts the clock pulses output from the VCO 1 and outputs it as a BCD code.

The decoder 3 converts the BCD code output from the BCD/U/D counter 2 into decimal numbers 0 to 7 and outputs the converted code.

The RS flip-flop 11 is reset by the Q0 output of the BCD decimal decoder 3 and set by the Q7 output. Then, by the Q output of this RS flip-flop 11, Q(UD),
The BCD/U/D counter 2 is controlled by up/down switching.

As a result, BCD/U/D counter 2 is
The 532KHz clock pulse output from 1,
Every time you count 8 pieces, alternately count up and count down.

Therefore, each output terminal of the decoder 3, Q0 to Q7
, a "1" pulse is output at the timing shown in FIG. These pulse signals are then supplied as switching pulses to the aforementioned analog switches S1 to S16.

On the other hand, from the Q output of the D-type flip-flop 7, as shown in FIG.
This rectangular wave Q38 is further frequency-divided by 1/2 by the D-type flip-flop 12, and this frequency-divided output Q(P) is used to generate a cancel signal for canceling the pilot signal. be done.

According to the above configuration, the left demodulation output terminal OUTL
And the right side demodulation output terminal OUTR is connected to analog switches S1, S9, S2, S10, and S1 connected to each symmetrical connection point of the resistance ladder circuit LAD.
3, S11... are alternately derived every clock. For example, it is assumed that the resistance values of resistors r1 to r7 are all set to the same value, and that the composite signal Ei is a constant DC voltage. Then, as shown in FIG. 7, a staircase wave having a phase difference of 180 degrees and having the frequency of the subcarrier as the fundamental wave is output to the left and right output terminals OUTL and OUTR. That is, if an arbitrary composite signal is Ei and each staircase wave shown in FIG. (t)
The multiplication result Ei・s(t) is output,
Ei·s(t)′, which is the multiplication result of Ei and the right staircase wave s(t)′, is output to the right demodulation output terminal OUTR, and multiplication with the switching signal is performed here to perform stereo demodulation. It will be done.

Moreover, the waveform of the staircase wave s(t) has a resistance value r1~
The value of r7 can be arbitrarily set depending on how the value of r7 is selected, and by appropriately selecting the values of each resistance value r1 to r7, the staircase wave s(t) can be roughly expressed as shown in FIG. It can also be sinusoidal. Also, the 8th
The figure is a graph showing the demodulation sensitivity of this stereo demodulation circuit when the staircase wave s(t) is approximately sinusoidal. As shown in Fig. 3, in the conventional circuit, there is only a difference of about 10 dB between the fundamental wave ω component and the third harmonic 3 ω component, and
While harmonic components such as the next and seventh harmonics are not attenuated much, in the case of the circuit of the present invention, as shown in FIG. 8, between the fundamental wave ω component and the third harmonic 3ω component, There is a level difference of about 40dB, and 5
The harmonic components such as the 7th and 7th harmonics were also significantly reduced compared to the conventional circuit.

Moreover, these switching signals s(t), s
(t)′ is (1+2sinω
t), (1-2sinωt), so as proven by the above formula, there is no mutual crosstalk component mixed into the left and right demodulated outputs in principle, and stereo separation is possible. It is possible to improve the degree significantly.

Thus, the FM stereo demodulation circuit according to this embodiment converts the composite signal Ei with a shift ratio of +
The level is shifted simultaneously to the positive side and negative side so that the ratio is 3:-1, and a resistor ladder circuit is connected between these outputs.
The voltage is divided in advance into 8 levels by LAD, and each divided voltage is selectively led out to each demodulation output terminal OUTL, OUTR via analog switches S1 to S16. Because of this, unlike conventional examples that use nonlinear performance elements as multipliers, composite signals
Switching signal s of arbitrary waveform for Ei
(t) and s(t)' can be accurately multiplied without distortion.

Therefore, if the number of voltage division levels is increased and the resistance values are selected more strictly, the waveform of the staircase wave signal s(t) can be made closer to a sine wave.
Ideal stereo demodulation operation can be performed.
Moreover, according to this demodulation circuit, as mentioned above, the third order,
Since the fifth-order and other low-order harmonic components can be significantly reduced, it is no longer necessary to provide a filter to remove these components before the demodulation circuit, and this reduces the frequency dependence of stereo separation. can also be solved.

Furthermore, since switching signals containing frequency components of (1+2 sin ωt) and (1-2 sin ωt) are used as switching signal waveforms,
In principle, there is no crosstalk component between the demodulated outputs on the left and right sides, so that the degree of stereo separation can be significantly improved.

Next, FIG. 9 is an electric circuit diagram showing an embodiment of the second invention. In FIG. 9, parts having the same configuration as those of the first embodiment are designated by the same reference numerals, and a description thereof will be omitted.

The feature of this second embodiment is that it facilitates quality control when selecting the resistor elements constituting each resistor ladder circuit, thereby preventing the generation of even-order harmonics due to variations in resistor elements among products. It is.

In FIG. 9, the composite signal Ei supplied to the input terminal IN is transmitted through four operational amplifiers OP5 to
Supplied to OP8. On the output side of the operational amplifier OP5, +3·Ei is output when the analog switch S25 is on, and -Ei is output when the analog switch S25 is off. Similarly, on the output side of operational amplifier OP7, when analog switch S26 is on,
+3・Ei is output and analog switch S26
When is off, -Ei is output. The analog switch S25 and the analog switch S26 each have a switching pulse generation circuit SP.
The Q output Q38 and the inverted Q output Q38 of the RS flip-flop 15 constituting the RS flip-flop 15 are supplied.

Therefore, a rectangular wave having a subcarrier frequency and inverted between +3Ei and -Ei is output to the output side of the operational amplifier OP5, and a subcarrier frequency is output to the output side of the operational amplifier OP7. A rectangular wave having a frequency of , inverted between +3·Ei and −Ei, and having a phase difference of 180 degrees from the rectangular wave is output.

The operational amplifiers OP6 and OP8 each operate as a buffer, and Ei is always outputted to the output side thereof. The outputs of the operational amplifiers OP5 and OP6 are applied to both ends of a resistor ladder circuit LAD1 consisting of resistors r11 to r41, respectively, and the outputs of the operational amplifiers OP7 and OP8 are applied to both ends of the resistor ladder circuit LAD1 consisting of resistors r11 to r41, respectively.
2 to r42 are applied to both ends of a resistor ladder circuit LAD, respectively.

Each divided voltage output of the resistor ladder circuit LAD1 is led out to the left demodulation output terminal OUTL by an analog multiplexer consisting of analog switches S17 to S20, and the other resistor ladder circuit LAD
Each partial pressure output of 2 is provided by analog switches S21 to S21.
Through an analog multiplexer consisting of 24
It is led out to the right demodulation output terminal OUTR. The analog switches S17 to S24 constituting each analog multiplexer are selectively controlled on and off by switching pulses supplied from the switching pulse generating circuit SP.

Next, the switching pulse generation circuit SP will be explained. The frequency of voltage controlled oscillator (hereinafter referred to as VCO) 1 is determined by up/down counter 2, BCD/DEC decoder 3, and NAND gate 1.
3, 14, RS flip-flop 15, D-type flip-flop 8, phase detector 9, and
It is locked to 532KHz by a phased locked loop consisting of 10 DC amplifiers.

BCD/U/D counter 2 counts the clock pulses output from this VCO 1 and
Output in BCD code.

The decoder 3 converts the BCD code output from the BCD/U/D counter 2 into decimal numbers 0 to 7 and outputs the converted code.

The RS flip-flop 11 is reset by the Q0 output of the BCD decimal decoder 3 and set by the Q7 output. The BCD/U/D counter 2 is switched up or down by the Q output of the RS flip-flop 11.

As a result, BCD/U/D counter 2 is
The 532KHz clock pulse output from 1 is
Each time you count, you will alternately count up and count down.

As a result, each output terminal Q0 to Q7 of the decoder 3
"1" is output at the timing shown in FIG. And each output Q0~ of these decoders 3
Q7 is further logically summed through OR gates 17-19, and the outputs of these OR gates become switching pulses for each of the analog switches S17-S24.

On the other hand, on the output side of the RS flip-flop 15, as shown in FIG. 7, a rectangular wave that becomes "1" or "0" every half cycle of the subcarrier is output.
Q38 is the Q output of RS flip-flop 15.
is supplied to an analog switch S25 inserted on the input side of the aforementioned operational amplifier OP5. Further, the Q output 38 of the RS flip-flop 15 is supplied to an analog switch S26 inserted on the input side of the operational amplifier OP7.

As a result, as mentioned above, the analog switch S25
and S26 are alternately turned on and off in synchronization with the subcarrier.

According to the above configuration, the composite signal Ei is always output as is to the output sides of the operational amplifier OP6 and the operational amplifier OP8. On the other hand, the composite signal Ei is outputted to the output sides of the operational amplifier OP5 and the operational amplifier OP7, with the level controlled to +3 times and -1 times every half cycle of the subcarrier. Then, the gain of operational amplifier OP5 is +
When the gain is set to 3x, the gain of operational amplifier OP7 is always set to -1x.
Conversely, when the gain of operational amplifier OP5 is set to -1, the gain of operational amplifier OP7 is +3.
This means that it is set to double. That is, the output of the operational amplifier OP5 and the output of the operational amplifier OP7 always have a phase difference of 180 degrees.

On the other hand, analog switches S17 to S2
0 corresponds to the period in which the analog switch S25 is on and the period in which it is off, respectively.
Sequentially S20→S19→S18→S17→S18→
They will be turned on sequentially like S19 → S20,
Similarly, the analog switches S21 to S24 are sequentially switched to S24→S23→S2 during the period corresponding to when the analog switch S26 is turned on or off.
2→S21→S22→S23→S24.

Therefore, if we assume that the level of the composite signal supplied to the input terminal IN is DC, a staircase-like pseudo sine wave will be output to the left demodulation output terminal OUTL, and a pseudo sine wave in the form of a staircase wave will be output to the right demodulation output terminal OUTL.
Similarly, a staircase-like pseudo sine wave having a phase difference of 180 degrees is obtained at OUTR. In other words, any composite signal Ei can be input to the input terminal IN.
, the left demodulation output terminal OUTL will have the result of multiplying this composite signal Ei by the pseudo sine wave, and the right demodulation output terminal OUTL will have the result of multiplying this composite signal Ei by the pseudo sine wave.
The result of multiplying the composite signal Ei by the right side pseudo sine wave is obtained at OUTR.
As a result, the crosstalk components included in the left and right demodulated outputs can be completely removed, as proven by the above formula.

Thus, according to the FM stereo demodulation circuit shown in this embodiment, a composite signal Ei including at least a stereo main channel signal and a stereo sub-channel signal is converted into a composite signal Ei with a shift ratio of +3 on the positive side and negative side. After the level is alternately shifted to the positive side and the negative side by half a cycle of the subcarrier so that At the shift ratio, the output is voltage-divided into a plurality of resistor ladder circuits LAD1, LAD2 that divide the voltage into a plurality of voltages symmetrically on the positive side and negative side with the potential corresponding to +1 as the center, and these resistor ladder circuits LAD1, LAD2 The divided voltage outputs are synchronized with the subcarriers in the composite signal Ei and sent to analog switches S17 to
20, the two analog multiplexers consisting of S21 to S24 perform reciprocating operation to sequentially take out data in series, so that each divided voltage output of each of the resistor ladder circuits LAD1 and LAD2 is a sine wave. If the composite signal Ei is set to be the instantaneous value at each division point that divides one cycle into 8 equal parts, the composite signal Ei will be multiplied by the stepped sine wave accurately and without distortion, which is different from the conventional method. Compared to the case of multiplying by a rectangular wave of In addition, the resistance ladder circuit LAD1,
The voltages applied to both ends of LAD2 are +3 times the composite signal Ei on the positive side and -1 times on the negative side.
Since the levels are shifted by a factor of two,
In each left and right multiplication operation, the multiplicand signals used include (1+2sinωt), respectively.
Since a frequency component of (1-2 sin ωt) is included, the crosstalk component is completely removed from each demodulated output, as proven by the above-mentioned formula.

Furthermore, in this embodiment, since the voltage applied to both ends of each resistor ladder circuit LAD is switched every half period of the subcarrier, the upper and lower half waves of the pseudo sine wave, which is the multiplicand signal, are the same. They are formed corresponding to the resistive elements, and as a result, the upper and lower half waves of the multiplicand signal always have symmetrical waveforms. Therefore, it is possible to solve the conventional problem of even-order harmonics being included in each demodulated output due to the vertical asymmetry of the multiplicand signal. That is, the sixth
As in the first embodiment shown in the figure, one of the subcarriers
If the resistor ladder circuit LAD is constructed of a series of resistors r1 to r7 in correspondence with the period, each step output of the pseudo sine wave will correspond to the resistors r1 to r7 individually. Therefore, a pair of resistor groups located on both sides of resistor r4, that is, resistor r
3 and resistor r5, resistor r2 and resistor r6, and resistor r1 and resistor r7 are required to have the same value. On the other hand, the resistance ladder circuits LAD1 and LAD2 of the second embodiment shown in FIG.
According to , the resistance ladder circuit shown in the first embodiment
2 with exactly the same resistance value, like LAD
It is no longer necessary to prepare individual resistors, and quality control in element selection becomes easier.

In both of these embodiments, the shift ratio of the level shift circuit is +3 to -1, but there is no problem even if it is +1 to -3.

As is clear from the description of each of the embodiments above, according to the FM stereo demodulation circuits according to the first and second inventions, the odd-numbered harmonics of the subcarriers included in the left and right demodulated outputs can be significantly reduced. In addition to being able to completely eliminate crosstalk components contained in both demodulated outputs, the configuration can also be digitized, and integration technology can reduce costs. It has excellent characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an FM stereo demodulation circuit using a conventional multiplier and a square wave switching signal.
2 is a waveform diagram of the switching signal used in FIG. 1, FIG. 3 is a diagram showing demodulated output components in the circuit of FIG. 2, and FIG. 4 is a block diagram showing the basic principle of the circuit of the present invention. 5 is a waveform diagram of a staircase wave signal used in the circuit of the present invention, FIG. 6 is an electric circuit diagram showing an embodiment of the first invention, and FIG. 7 is a waveform diagram of a staircase wave signal used in the circuit of the present invention. FIG. 8 is a waveform diagram showing signal states in each part, FIG. 8 is a diagram showing frequency components included in each demodulated output in the circuit of the present invention, and FIG. 9 is an electric circuit diagram showing an embodiment of the second invention. OP1, OP2, OP5, OP7...Level shift circuit, LAD, LAD1, LAD2...Resistance ladder circuit, S1 to S24...Each analog switch forming the analog multiplexer, Ei...Composite signal.

Claims (1)

[Scope of Claims] 1. A level shift circuit that outputs two systems of signals by simultaneously level-shifting an input composite signal to opposite polarities at a shift ratio of 3:1; and the level shift circuit. A resistive voltage divider circuit that divides the output potential difference between both systems of the circuit into a plurality of voltage levels corresponding to each time-division instantaneous value of a reference sine wave, and a resistive voltage divider circuit that divides each divided voltage output value of the resistive voltage divider circuit into a composite signal. a first analog multiplexer that synchronizes with the pilot signal in the composite signal and sequentially outputs it by scanning back and forth every half cycle; and synchronizing each divided voltage output value of the resistor voltage divider circuit with the pilot signal in the composite signal; and a second analog multiplexer that performs reciprocating scanning every half cycle and sequentially outputs data with a phase difference of 180 degrees with respect to the scanning timing of the first analog multiplexer, An FM stereo demodulation circuit characterized by extracting left and right demodulated outputs from an analog multiplexer. 2 level shift circuits for each of the left and right that shift the level of the input composite signal by a certain amount to the positive side and add a DC component; one left and right level inversion circuit that alternately shifts the level to opposite polarities every cycle at a shift ratio of 3:1 (however, the DC component level is 1); and the left side level shift circuit. a left resistive voltage divider circuit that divides the potential difference between the output voltage of the left side level inversion circuit and the output voltage of the left side level inversion circuit into a plurality of voltage levels corresponding to the time-division instantaneous value of the reference sine wave; and the output voltage of the right side level shift circuit. and a right-side resistive voltage divider circuit that divides the potential difference between the voltage and the output voltage of the right-side level inversion circuit into a plurality of voltage levels corresponding to the time-division instantaneous value of the reference sine wave; and each voltage-divided output of the left-hand side resistive voltage divider circuit. A left analog multiplexer that sequentially scans the values back and forth every half cycle and selectively outputs the values in synchronization with the pilot signal in the composite signal, and a composite signal that outputs each divided voltage output value of the right resistor voltage divider circuit. a right-side analog multiplexer that sequentially scans reciprocatingly every half period of the pilot signal in synchronization with the pilot signal and selectively outputs the signal; An FM stereo demodulation circuit characterized in that one of the scanning operations of the multiplexer has a phase difference of 180° between the left side and the right side, and left and right demodulated outputs are taken out from the left and right analog multiplexers.