JPS6249775B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a loop system, and particularly to a control method for a loop network system in which a plurality of processors are connected by a unidirectional loop.

FIG. 1 shows an outline of a loop network system to which the present invention is applicable. Although the illustrated loop network consists of six nodes _N0 to _N5 , this number is not limited. Each node is connected by a loop bus whose transmission direction is unidirectional, as shown by the arrow in the figure. Each node has a commonly known node processor, and a host processor is connected to each of them, but the roles and functions of each host processor are not directly related to this invention. Since Figure 1 is for schematically explaining a loop-like network to which the present invention is applied, they are omitted from the figure.

In such a loop network system, it may be desirable to send the same command from any host processor to all other host processors at once. For example, if you want to reset all other host processors from any host processor, or if a host processor detects a failure and wants to notify all the other processors of it all at once.

An object of the present invention is to prevent the fault management flag from being erroneously set in the above-described loop network system, especially when each node detects the occurrence of a fault in its own node.

To achieve this objective, the present invention connects multiple nodes through a unidirectional loop bus, and each node always takes in signals received from the previous node and relays them to the next node. In a loop network system in which the above received signal is a fault occurrence notification signal, it is stored using a fault management flag, and when each node detects a fault occurrence in its own node, it sends a fault occurrence notification. A signal is transmitted onto the loop bus, the fault management flag is set, and fault recovery processing is performed with reception from the preceding node being blocked for a predetermined period of time longer than the time it takes for the signal to go around the loop bus. It is characterized by the following.

This will be explained below using figures.

FIG. 2 is a diagram showing an operational flow according to an embodiment of the present invention. In this embodiment, the operation at a certain node N _i when a failure occurs in a processor will be described as an example.

A failure occurs in one of the nodes preceding node N _i , and the failure signal issued from that node is sequentially transmitted and received from node N _i-1 , or the failure occurs from node N i itself. When a failure is detected, it is checked whether the failure has already been detected (what is the status of the failure management flag on the own node N _i ?). If the failure management flag is turned on)), and if it is not detected, the failure management flag is turned on and a failure occurrence signal is transmitted to the next node N _{i +1} .

If a failure is detected on the own node N _i , a timer is started, and even if the failure is recovered, the failure management flag is turned on and the failure management flag is turned off after T seconds or more. do. This allows normal use of the loop bus again. Here, the above-mentioned time T seconds is set to be longer than the time required for the failure occurrence signal to go around the loop network. Otherwise, if you finish the fault processing faster than this one-cycle time, turn off the fault management flag, and return to the normal state, when the fault signal sent from itself has completed one cycle, the system will once again enter the fault detection state. There is. For this reason, a predetermined time interval is required before the failure recovery process, but the failure recovery process itself may be performed earlier by using a circuit to be described later at each node. As methods for transmitting the fault signal, there are a method that uses a signal line for data transmission and can distinguish between data and a fault signal based on a bit pattern, and a method that provides a dedicated signal line for the fault signal.

FIG. 3 shows a circuit provided at each node to perform the above-described operation. In the figure, the node N _i is representatively shown. This circuit is constructed as follows.

The signal from the preceding node N _{i -1} is input to one input terminal of the AND gate 32 via the isolator 31 . The output of the inverter 33 is input to the other input terminal of the AND gate 32 . Note that if insulation between adjacent nodes is not required, there is no need to provide the isolator 31, and the signal from the previous node N _i-1 is directly connected to the AND gate 32.
All you have to do is input it. The output of AND gate 32 is led to OR gate 34. The input signal of the inverter 33 is a signal V _O as shown in FIG. 4A. This signal V _O is a failure occurrence signal as already described in the explanation of FIG. 2, but it goes without saying that it may be any other signal that is to be notified from the node N _i to all other nodes. . This signal V _O is also given to the pulse width shortening circuit 35, where the fourth
As shown in FIG. 2, it is converted into a pulse signal V _P having a sufficiently narrower width than the signal V _O. The signal V _P is directed to an OR gate 34 . The output of the OR gate 34 is taken into its own node as a signal V _I (FIG. 4C), and is also transmitted to the next stage node N _i+1 . Here, the width of the signal V _O is set to be T seconds or more, which corresponds to the ON period of the fault flag explained in FIG. 2, and the reason for this will become clear from the explanation of the operation described later.

The above circuit operates as follows.

First, a case where the signal V _O does not exist at the node N _i will be described. In this case, the inverter 33
is outputting an output, so the signal from the preceding node N _{i -1} passes through the AND gate 32 and is taken into its own node N _i via the OR gate 34, and is sent to the next node N _i+1 .

Next, a case where the signal V ₀ is generated at the node N _i will be explained. Since the signal V _O exists, the output of the inverter 33 disappears, and the AND gate 32
is in a blocked state. On the other hand, the signal V _O is converted by the pulse width shortening circuit 35 into a narrow pulse signal V _P as shown in FIG. 4B. The signal V _P is taken into the own node N _i as a signal V _I via the OR gate 34, and is transmitted to the next stage node N _i+1 .

At the next stage node N _i+1 , as described above (operation when signal V _O does not exist), the signal sent from node N ₁ is taken into its own node N _i+1 , and further Transmit to the next node. Similarly, other nodes receive the signals received from the previous node into their own nodes, and
Send to the next node. Therefore, node N _i
The signal sent out from the node reaches the node N _i again after going around the loop bus.

Here, if the time T of the width of the signal V _O is set to be longer than the loop time of the above-mentioned signal, the output of the inverter 33 will not exist and the AND gate 32 will still be in the blocking state, so that the signal that has made the loop will be blocked. It will not be captured by node N _i again. In this way, as described in connection with the explanation of FIG. 2, the failure recovery process can be performed early without waiting for the signal round trip time T.

The above explanation has focused on the example of notifying all other nodes of a failure signal generated at an arbitrary node, but the application of this invention is not limited to this, and all nodes within the loop As already mentioned, this method can be applied when it is desired to notify all nodes at once.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing a loop network system to which this invention is applied, FIG. 2 is a diagram showing an operation flow of an embodiment of this invention, and FIG. 3 is a diagram used in the above embodiment. FIG. 4 is a diagram showing each signal waveform for explaining the operation of the circuit shown in FIG. 3. In the figure, N ₀ to N ₅ are nodes, 31 is an isolator, 32 is an AND gate, 33 is an inverter, 34 is an OR gate, and 35 is a pulse width shortening circuit.

Claims (1)

[Claims] 1 Multiple nodes are connected by a unidirectional loop bus, and each node normally takes in the signal received from the previous node and relays it to the next node, and the received signal is used as a failure occurrence notification signal. In a loop network system that stores this using a pest management flag in the case of
When each node detects the occurrence of a fault in its own node, it transmits a fault occurrence notification signal onto the loop bus, sets the fault management flag, and waits for a predetermined period of time longer than the time it takes for the signal to travel around the loop path. 1. A loop system control method characterized in that a state is set in which reception from a preceding node is blocked.