JPS6367380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault control method in a loop network system, and particularly to a method for simultaneously sending a fault detection signal to all processors in the network.

In the network system, as shown in FIG. 1, a plurality of host processors 10 to 15 are installed.
network control processors 20 to 25, respectively;
is connected to the loop-shaped data signal line 3 via
Similarly, there is a synchronous transmission system in which data is transmitted using a clock signal on a clock signal line 4 connected in a loop.

In such a system, if an abnormality occurs in a certain processor, the effect is not limited to that processor, but also affects other processors in the same loop. If an abnormality occurs there,
It is necessary to simultaneously notify all processors in the same loop by some means to perform failure recovery processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure control method in a synchronous loop network system as described above, which can notify all other processors in the loop at once of the occurrence of a failure in a certain processor.

The present invention is characterized by a plurality of host processors, a network control processor connected to each of them, and a data signal line and a clock signal line connecting the network control processors in a loop. In a loop network system consisting of a network control circuit, if one of the network control processors detects a failure, the clock signal sent from the network control processor to the clock signal line is interrupted for a predetermined period of time. This is because we tried to maintain it at the same level.

This will be explained below with reference to the drawings.

FIG. 2 shows the configuration of a network control processor according to an embodiment of the present invention. However, only the parts related to the present invention are shown in the figure, and the parts performing other functions as a network control processor are omitted. Also, this figure is for a loop network system having four nodes, and therefore four network control processors NCP ₀ to NCP ₃ are shown, two of which (NCP ₀ and NCP 3) are shown. The detailed configuration is shown only for NCP ₁ ).

In the figure, ₀ to ₃ indicate reset signal lines in each of the network control processors _NCP0 to _NCP3 (in the following description, the reset signals themselves may be indicated). A ₀ to _{A 5} represent one shot circuits (hereinafter simply referred to as one shot), each having a time constant of T ₀ to _{T 5} . 31,
32 is an inverter, 33, 34, 35, 36 are OR gates, 37, 38 are inhibit gates, 3
9 and 40 indicate an AND gate.

Before explaining the operation of the second illustrated arrangement, for better understanding, the operation of the one shot used in the above arrangement will be explained with reference to FIG.

Figure 3 A shows the configuration of the above one shot,
A and B are input terminals, and Q is an output terminal. It is assumed that this one shot has a time constant T.
FIG. 3B shows some examples of input/output relationships. First, when the input at the A terminal is at a low level, when a high level input is input to the B terminal, the Q terminal becomes at a high level for a time T from the rising edge of the input. Similarly, when the A terminal input is low level, the B
If a high level input is input to the terminal and a high level input is input to the B terminal again within time T during which the Q terminal output is kept at a high level, the high level of the Q terminal output will change to the last rising point of the B terminal input. Connect from to time T. Also, due to the high level input to the B terminal, Q
If a high level input is input to the A terminal while the high level output of the terminal is connected, all subsequent high level inputs input to the B terminal will be ignored, and the B terminal immediately before the high level input of the A terminal will be ignored. After T time from the rise of the high level input, the Q terminal output returns to low level.

Next, the operation of the configuration shown in the second diagram will be explained with reference to the time chart of each signal shown in FIG.

Assume that a failure detection signal _Io0 is generated in the network control processor _NCP0 . in this case,
The above fault detection signal I _o0 is not instantaneous,
It is assumed that the fault occurrence signal from the network control processor NCP ₀ (described later) is in a high loop state (ON state) while it makes one circuit around the loop. this signal
_Io0 is input to the B terminal of one shot _A0 . As a result, the Q terminal output A ₀ Q of one shot A ₀ is
The output is at a high level for a time T ₀ from the rise of the signal I _o0 . The terminal output A ₁ of one shot A ₁ is
While the output A ₀ Q is low level, the AND gate 3
9. A low level _{(A 1 Q} is
high level). When the output A ₀ Q, that is, the A terminal input of the one shot A ₁ becomes high level (Fig. 4), the level immediately before A ₀ Q rises is
A ₁ Q becomes high level (A ₁ Q is low level) _one hour after CLK ₀ rises (). And the rising edge of CLK ₀ () immediately after the rising edge of A ₀ Q ()
So, A ₁ becomes a low level ().

The Q terminal output A ₂ Q of one shot A ₂ is at a high level for a time T ₂ from the rising edge of A ₁ ( ). This output A ₂ Q passes through the inverter 31,
The reset signal of the network control processor NCP ₀ becomes ₀ (). A ₂ Q and CLK ₀ are combined by an OR gate 34 and sent to the next network control processor NCP ₁ as a signal T _x C ₀ (). This signal is received by the network control processor _NCP1 as a signal R _{x C1} .

In the network control processor NCP ₁ , since the fault signal pulse I _o1 is at a low level (assuming that no fault is detected here), one shot A ₃
The Q terminal output A ₃ Q of is held at a low level.
Also, since I _o1 is at a low level, the signal T _x C ₀ sent from the network control processor NCP ₀
(i.e. R _x C ₁ ) is the inhibit gate 38,
Through or gate 35, one shot A ₄ B
input to the terminal.

One shot A ₄ is normally the input pulse of R _x C ₁ (T _x C ₀ ) (i.e. it is one shot A ₂
A clock pulse while output A ₂ Q is low level.
At the rising edge of CLK ₍₀ ), it operates in one shot with a time constant of _T4 each time. However, R _x C ₁ (T _x
When the rising edge of C ₀ ) disappears ( ), its output A ₄ is held at a high level ( ), T ₄ hours after the last pulse rising edge. When R _x C ₁ (T _x C ₀ ) starts changing again, A ₄ goes low at the rising edge of its first pulse (). one shot
As in the case of A ₂ Q described above, the Q terminal output A ₅ Q of A ₅ is at a high level for time T ₅ from the rising edge of A ₄ , and passes through the inverter 32 to the network control processor NCP ₁ . Reset signal line ₁
becomes().

Thereafter, the network control processors NCP ₂ and NCP ₃ also perform the same operations as described above. And T _x C ₃ of network control processor NCP ₃
The signal is sent to the network control processor NCP ₀ .
Given as R _x C ₀ signal. However, since the I _o0 signal of the network control processor NCP ₀ is at a high level, R _x C ₀ is blocked by the inhibit gate 37 and is not applied to the one shot A ₁ . Therefore, A ₁ is kept at a high level. In other words, the network control processor
The failure signal sent from NCP ₀ keeps the level of the looped clock signal line at a high level for a certain period of time, making a circuit, but is detected again by the network control processor NCP ₀ . Never.

Next, the time constants to be given to each of the above-mentioned one shots will be explained. Each network control processor is similarly configured. Therefore, T ₀
= T ₃ , T ₁ = T ₄ , T ₂ = T ₅ . The same applies to the network control processors NCP ₂ and NCP ₃ . Each time constant is selected as follows.

T ₀ (T ₃ ): Time constant of the first stage one-shot circuit.
This returns the terminal output of the second stage one-shot circuit to a high level, so T ₁ +t
It is set as above. However, t is the period of the clock pulse. In the above embodiment, 3t is selected.

T ₁ (T ₄ ): Time constant of the second stage one-shot circuit.
This is to detect missing clock pulses. Since 1t may cause malfunction due to the influence of noise, in the above embodiment, it is set to 2t to give a margin.

T ₂ (T ₅ ): Time constant of the third stage one-shot circuit.
If a network control processor resumes processing before all network control processors have been reset, malfunctions may occur. Therefore, the reset signal must be set for a time sufficient to complete the loop and bring all network control processors into the reset state. In other words, each time the network passes through one network control processor, T ₁
(T ₄ ), so the delay time must be greater than the value multiplied by the number of vehicles passing through. In the above example, the number of vehicles passing through is 4, and T ₁ (T ₄ ) = 2t, so it needs to be 8t or more, but with a margin of 10t.
It is said that

As explained above, in the embodiment shown in the second figure, when a fault is detected, the clock signal is set to a high level for a certain period of time, and this is detected by a simple device added to each network control processor. This allows all nodes in the loop to know the occurrence. However, the above-mentioned change in the state of the clock signal can also be detected by providing each network control processor with a function similar to the above-described function using software. The operation of this embodiment will be described below with reference to FIG.

FIG. 5 shows the state changes of the clock signal between the nodes when there are four nodes in the loop. That is, in the same figure, A is between the first node and the second node, B is between the second node and the third node, C is between the third node and the fourth node, and N is between the second node and the third node. is between the fourth node and the first node.

Now, each node activates its respective network control processor and starts data transmission. For example, assume that a failure has been detected in the first node. As a result, the network control processor of the first node sets the clock signal sent to the second node to a high level for a certain period of time _T1 (FIG. 5). Normally, the first node performs failure processing during this time.

_The network control processor of the second node, which was receiving data from the first node,
When no data comes in for a period of time (), the state of the clock signal line is checked. At that time, if the clock signal is at a high level, it knows that a failure has occurred, and, like the network control processor in the first node, changes the level of the clock signal sent from there to the third node for T ₁ time. The distance is set at a high level.
Further, when the second node is not receiving data, it checks the state of the clock signal at a constant cycle (≦T ₁ ), and if it is at a high level, performs the operation described above. Similar operations are performed at the third and fourth nodes. The network control processor of each node is provided with the above-mentioned functions in terms of software, and the network control processor that first detects a failure sets the clock signal level to high.
In a cascading manner, all nodes can be notified of the occurrence of a failure.

When each network control processor returns to normal processing after failure processing, it first changes the clock signal from high level to low level to enable reception, and then all network control processors in the loop Time when the processor is ready to receive data
After waiting T ₃ , make it ready to send (). However, the network control processor that first detects the failure ignores changes in the state of the clock signal until it becomes ready for transmission. Thereby, the failure occurrence notification signal can be stopped after completing one loop.

As described above, according to the present invention, the occurrence of a failure in a synchronous loop data transmission system can be easily notified to all nodes in the loop at once with a simple device.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a loop network system to which the present invention is applied, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG.
A diagram for explaining the operation of the one-shot circuit used in the illustrated configuration, FIG. 4 is a diagram for explaining the operation of the second illustrated embodiment, and FIG. 5 is a diagram for explaining the operation of another embodiment of the present invention. This is a diagram for 10-15...Host processor, 20-25
...Network control processor, 3...Data signal line, 4...Clock signal line, _A0 to _A5 ...
One shot circuit.

Claims (1)

[Claims] 1 A processor for controlling multiple networks,
A loop-shaped circuit consisting of a host processor connected to each network control processor and a data signal line and a clock signal line each having a predetermined signal transmission direction and connecting each of the network control processors in a loop shape. In a network system, each network control processor
When a failure is detected in the own network control processor, or when the clock signal received from the upstream network control processor via the clock signal line enters a predetermined abnormal state, the downstream clock By maintaining the clock signal to be sent to the signal line at a predetermined level for a certain period of time, the occurrence of a fault detected in one network control processor is transmitted to the other network via the clock signal line. A fault control method for a loop network system, characterized in that all network control processors are notified.