JPS6249807B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protective relay device including a plurality of processors and an interface for interconnecting them.

Conventionally, there has been a protective relay device of this type as shown in FIG. In FIG. 1, a processor 1 responsible for protection processing is connected via an interface 3 to a processor 2 responsible for transmission processing for transmitting information to a substation or the like. The interface 3 includes a detection circuit 4 connected to the address bus 1a of the processor 1 to detect a predetermined address, and a data output bus 1b of the processor 1.
A signal 4a output from the detection circuit 4
A register 5 that stores data on the data output bus 1b and a signal 5 output from the register 5.
a decoder 6 for decoding a, mono-multi vibrators (hereinafter referred to as mono-multi) 7-1 to 7-m that output one pulse when triggered by the signal 6a output from the decoder 6, and mono-multi vibrators 7-1 to 7-m; A multiplexer 8 that selectively outputs one of the pulse signals 7-1a to 7-ma output from -1 to 7-m according to a signal 9a described below.
and a register 9 connected to the bus 2a of the processor 2 to store data and output a signal 9a.
and a register 10 that stores the signal 8a output from the multiplexer 8 and outputs it as data to the bus 2a. In addition, code 1a
is the data input bus of processor 1.

To explain the operation, the processor 1 sends the address information in the register 5 to the address bus 1a, and further sends data to trigger any one of the monomultis 7-1 to 7-m to the data output bus 1b. . This address information is detected by the detection circuit 4 and output as a signal 4a. Signal 4a causes register 5 to store the data output on data output bus 1b. Signal 5a of register 5
is decoded by the decoder 6 and triggers any one of the monomultis 7-1 to 7-m. The monomultis 7-1 to 7-m correspond to the circuit breakers (not shown) provided for each phase, and their logical states are read at regular intervals by the processor 2 as shown below. It will be done.

That is, the processor 2 sends data serving as a control signal to the bus 2a in order to perform reading processing at regular intervals.
Output to. When data on bus 2a is stored in register 9, register 9 receives signal 9 which is a control signal.
Output a. When the signal 9a is output, the logic states of the monomultis 7-1 to 7-m are stored in the register 10 via the multiplexer 8. Furthermore, the contents of register 10 are read by processor 2 via bus 2a.

In this way, the data output from the processor 1, ie, the disconnection trip signal (not shown), is transferred to the processor 2. Processor 2 continues processing for transmitting this data to a substation (not shown).

Conventional protective relay devices are configured as described above, so that the transmission processing processor frequently performs reading processing in order to reliably read the logical state of the monomultiple, which automatically returns to its original state after a certain period of time. A considerable portion of the processing power is taken up by this reading process, which has the disadvantage that the overall functionality cannot be improved.

The present invention was made in order to eliminate the drawbacks of the conventional devices as described above, and an object of the present invention is to provide a protective relay device that can improve the overall functionality by operating the processor efficiently. do.

An embodiment of the present invention will be described below with reference to FIG. FIG. 2 shows the parts of the protective relay device related to the present invention, and other parts not related to the present invention are omitted. In Figure 2,
An interface 11 is provided for transferring data from processor 1 to processor 2. In the interface 11, 12 and 13 are memories with the same configuration, 14 is an address bus 1a,
15 is a multiplexer that selects data output buses 1b and 2b; 16 is a multiplexer that selects signals 12a and 13a output from memories 12 and 13;
A control flip-flop 7 controls switching of multiplexers 14, 15, and 16.

Next, the operation will be explained. flip flop 17
When is in the initial state, that is, the reset state, the control signal, that is, the signal 17a outputted from it is at the "H" level. Due to the "H" level of the signal 17a, the input terminals A1 and A2 of the multiplexers 14, 15, and 16 are selected, and the signal of the input terminal A1 is sent to the output terminal Y1, and the signal of the input terminal A1 is sent to the output terminal Y2.
The signal of input terminal A2 is outputted to. Further, if the signal 17a of the flip-flop 17 is a set state "L" level signal, the multiplexer 1
4, 15, and 16 are in a state where the input terminals B1 and B2 are selected, respectively, and the output terminal Y1 receives the signal from the input terminal B1, and the output terminal Y2 receives the signal from the input terminal B.
2 signals are output. flip flop 17
is connected to the data output bus 2b and can be set or reset by the processor 2. Processor 2 initially flip-flops 17
to the reset state. In this state, when the processor 1 detects an accident on the power transmission/distribution line, it outputs a trip signal to the relevant disconnector of the power transmission/distribution line where the accident has occurred, and at the same time outputs a trip signal to the processor 2 (A, B). , C phase-specific trip signals are passed. Specifically, when the A-phase overcurrent relay operates, it outputs an address m to the address bus 1a and outputs data "1" to the data bus 1b. At this time, since the flip-flop 17 is in the reset state, the A side of the multiplexer 14 is selected, and the address m of the address bus 1a is output to the output terminal Y1 of the multiplexer 14 and input to the memory 12. Multiplexer 15 also directs data on data bus 1b to output terminal Y1. In this way, the memory 12 has
The trip signal of the A-phase overcurrent relay is stored as present. If the B-phase also operates, the existence of the B-phase trip signal is stored in the address m+1 of the memory 12 in accordance with the data on the data bus 1b in the same manner as described above.

Furthermore, if the flip-flop 17 is in the set state, the B-side input of the multiplexer 14 is selected, and the address m is output from the output terminal Y2, and the multiplexer 15 outputs the trip signal of the A-phase overcurrent relay. Since it is output to the terminal Y2, the presence of the A-phase trip signal is stored at address m in the memory 13.

Next, the read operation of the memories 12 and 13 will be explained. The processor 2 outputs a control signal to the flip-flop 17 via the data output bus 2b to set the flip-flop 17, and also outputs an address m to the address bus 2d.
Output. The multiplexer 14 has a flip
Since the flop 17 is in the set state, the B side is selected and the address m is led from the input terminal B1 to the output terminal Y1 and supplied to the memory 12. The memory 12 reads the data at address m and inputs it to the multiplexer 16. multiplexer 16
Since the B side is selected, the data in the memory 12 is guided from the input terminal B1 to the output terminal Y1, and sent to the data input bus 2c. Processor 2 is
Data on data input bus 2c, i.e. processor 1
Receives the trip signal output by.

Next, the processor 2 that has received the data in this way writes "0" to address m of the memory 12 to indicate no trip.
Address m is output to address bus 2d, data "0" is output to data output bus 2b, and "0" is written to address m of memory 12. Similarly, the processor 2 successively changes the addresses output to the address bus 2d and stores "0" in the memory 12.
are written one after another, one for each phase trip signal.
Ends the read cycle process. Thereafter, processor 2 outputs a control signal to flip-flop 17 to set it. As a result, processor 1 writes subsequent phase-specific trip signals to memory 12, and processor 2
reads the phase-specific trip signals from the memory 13. The processor 2 then processes the memory 12 or 1.
Each time data is read from the flip-flop 17, the flip-flop 17 is set or reset, respectively. As a result, the processors 1 and 2 can mutually access the memory 12 or 13 that they are using asynchronously, so that data can be exchanged asynchronously.

In the above embodiment, data was transferred by alternately writing only the trip signals of the protective relay device into two memories, but other information such as setting values and tap values may also be transferred. . Further, in the above embodiment, the multiplexer is switched before the start of data transfer, but it may be switched after the data transfer is completed.

As explained above, by providing an interface between two processors that has a memory that can be written and read asynchronously,
Each processor can be operated efficiently,
This can be done by increasing overall functionality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional protective relay device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1, 2... Processor, 3, 11... Interface, 12, 13... Memory, 8, 14,
15, 16...multiplexer, 17...flip/flop. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] 1 In a protective relay device that transfers data between a first and a second processor via a data input/output bus and an address bus, the first or second a flip-flop that outputs a control signal;
and a second memory, and each address bus of the first and second processors are connected to the first and second memories, respectively, when the first control signal is input; a first multiplexer that connects to the second and first memories, respectively, when a signal is input;
When the first control signal is input, each data output bus of the processor is connected to the first and second memories, respectively, and when the second control signal is input, the data output buses of the processor are connected to the second and second memories, respectively. a second multiplexer connected to the first memory; and a second multiplexer connected to the first memory;
A third processor that connects the data input bus of the processor to the second memory when the first control signal is input, and connects the data input bus of the processor to the first memory when the second control signal is input. multiplexer, and by alternately controlling the control signals, both the processors are connected to different memories at the same time, and data can be written and read between the two processors asynchronously with each other. protective relay device.