JPS6252268B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides automatic gain control (hereinafter referred to as automatic gain control) of a radar receiver.
This relates to improvements for faster operation of circuits (referred to as AGC).

The basic function of a normal radar receiver is to receive a reflected signal from a target object, amplify it by a predetermined amount, detect it, convert it to a video signal, and output it to a radar target detection device such as an indicator. be. Particularly when the radar target detection device is of an automatic processing type, it is important to keep the receiver output noise level, or in other words, the receiver gain, at a constant value by dealing with various gain fluctuation factors. AGC circuit is used.

Various types of AGC circuit systems are known for radar receivers, but one that is relatively commonly used is one that sends a pilot pulse signal of a specified level from the receiver input terminal during the radar idle period (also called dead time). There is a method of configuring an automatic gain control loop so that the pilot pulse signal level at the receiver output is constant.

A conventional system diagram of such a system is shown in FIG. FIG. 2 is an explanatory diagram of the operation.

In Figure 1, 1 is a reference oscillator in the intermediate frequency (hereinafter referred to as IF) band, and 2 is a radio frequency (hereinafter referred to as IF) band reference oscillator.
The outputs V _c and V _l of both oscillators 1 and 2 are mixed in a mixer 3 to generate a transmission frequency signal of the sum frequency. Thereafter, the signal is divided into transmission pulses and power amplified by a transmission power amplifier 4, and is then radiated into the air from an antenna 7 as a transmission pulse signal _Vt via a transmission/reception switch 5 and a directional coupler 6. The directional coupler 6 is a directional coupler for injecting a pilot pulse signal V _P generated by dividing the output of the mixer 3 into pulses by the pulse generator 8 .

A reflected signal (not shown) from the target object is received by an antenna 7 on the opposite path to that of the transmitted pulse signal, and then passed through a directional coupler 6 and a transmitter/receiver switcher 5 before being amplified by a wideband RF amplifier 9. . Thereafter, it is mixed with the local oscillation signal V _l of the local oscillator 2 in the reception mixer 10 to become an IF reception signal V _i of the difference frequency. The frequency of this IF received signal V _i is equal to the frequency of the output V _c of the reference oscillator 1 . The IF received signal V _i is amplified by an IF amplifier 11 whose gain can be controlled electronically, and detected by a detector 12 to become a video signal V _d , which is sent to the target detection device 30. The AGC circuit 100 includes, in addition to the IF amplifier 11 and detector 12, an error detector 13, a sample and hold circuit 14, and a loop filter 15.

Next, the operation will be explained. Transmission pulse signal V
The time relationship between _t and the pilot pulse signal V _P is selected as shown in FIGS. 2a and 2b. In FIG. 2a, T is the transmission pulse repetition period. The pilot pulse signal V _P is injected during the so-called radar pause period, which corresponds to the distance beyond the radar maximum detection distance immediately before the transmission pulse signal V _t , and does not overlap with the reflected signal from the target. The IF received signal V _i includes a reflected signal V _T from the target and a pilot pulse signal V _P as shown in FIG. 2c. Here, assume that the pilot pulse signal level is higher than the IF reference value V _IF (reference level) due to various gain fluctuation factors. For such an IF received signal V _i , the detector 1
Assuming that the output video signal V _d of No. 2 is also output at a value larger than the video reference value V _r as shown in FIG.
The difference from _r is taken and an error signal V _e shown in FIG. 2e appears. After this, in the sample hold circuit 14 at the next stage, the sample pulse P _sh (FIG. 2 f)
The error signal is extracted and held until the next sample pulse is input. In this way, the pulse-like error signal V _e is converted into an approximately DC-like error signal.

The loop filter 15 is for providing the gain and frequency characteristics necessary to realize a predetermined closed loop response characteristic. The output V _g (see Fig. 2g) is selected in such a direction that the error signal V _e of the output of the IF amplifier 11 becomes smaller, so that the pilot pulse signal level V _d of the output of the detector 12 becomes the video reference value V _r An automatic control loop will operate to ensure that .

The response time of such an automatic control loop for sample value control is limited to about 10 times the sample time (transmission pulse repetition period T), and attempting to make it faster than that will cause the loop to oscillate, which may affect operational stability. There are limitations in that problems arise.

In other words, in order to reduce the closed-loop time constant in an automatic control loop, it is possible to make the open-loop time constant large or to make the open-loop time constant small. In order to prevent oscillation (a state in which so-called positive feedback has occurred), there is naturally an upper limit value for the closed loop constant, and a desired closed loop time constant may not be obtained.

Since the AGC circuit of a conventional radar receiver is configured as described above, it can cope with relatively slow gain changes caused by temperature changes, changes over time, etc. It has the disadvantage that it cannot sufficiently follow the high-speed gain changes of the RF amplifier 9, mixer 10, etc. due to frequency changes that occur when the frequency is changed every transmission pulse repetition period (frequency agility). .

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by configuring a closed loop control circuit so that a specified control error is achieved within the time of the pulse width of the pilot pulse signal,
The purpose of this invention is to provide a high-speed AGC circuit for a radar receiver that sufficiently responds to changes in gain at each transmission pulse repetition period.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows an embodiment of the present invention, in which some parts common to FIG. 1 are omitted, and parts common to FIG. 1 are given the same numbers. 1
6 is a threshold circuit that outputs a pulse signal when the output V _d of the wave detector 12 exceeds a specified threshold value V _r ; 17 is a first counter 18 and a first counter 18 depending on the output state of the threshold circuit 16 and its changing state; A control circuit 18 controls the operating conditions of the counter 19 of No. 2, and 18 is a first counter whose operating conditions are controlled by the control circuit 17 and roughly counts clock pulses.
9 has its operating conditions controlled by a control circuit 17;
This is a second counter that precisely counts clock pulses, and both counters 18 and 19 are constructed as shown in FIG. 5, for example. That is,
The first counter 18 is an up/down counter for the upper 4 bits, and the second counter 19 is an up/down counter for the lower 4 bits. Together, these counters 18 and 19 form an 8-bit up/down counter.
It functions as a down counter. 20
21 is a digital-to-analog converter that converts the count output from the first and second counters 18 and 19 into an analog signal and outputs it to the IF amplifier 11 as a gain control voltage V _g ; 21 is the first and second counter; Vessels 18, 19
a clock pulse generator that generates clock pulses for driving the first and second counters 1;
8 and 19, up/down counters can be switched by setting operating conditions. Furthermore, it has a function to hold the latest counting results when the counting operation is stopped.

Next, the operation will be explained using the operation explanatory diagram of FIG. 4. FIGS. 4a and 4b show the same things as FIGS. 2a and 2b. FIG. 4c shows the IF received signal V _i ,
For convenience of explanation, it is assumed that the pilot pulse signal level changes every transmission pulse repetition period T.

For example, when the pilot pulse signal level is input at a level below the specified threshold value V _r , the output V _s of the threshold circuit 16 becomes a logic output "0". The control circuit 17 receives a gate signal P from a system timing generator (not shown).
_g (Fig. 4 k) operates in the logic level "1" section, and the output V _s of the threshold circuit 16 is "0".
Therefore, the up/down control signal P _d (Fig. 4 h) is set to "1", and the first and second counters 18 and 19 are set to the up counter state, and at the same time, the first counter The operation control signal P _e (FIG. 4f) of the second counter 18 is set to "1" to start the counting operation, and the operation control signal P _f (FIG. 4g) of the second counter 19 is set to "0". to stop the counting operation and hold the counting results. As a result, the first counter 18 performs a rough counting operation using the clock pulses generated by the clock pulse generator 21, and increases the count value in a stepwise manner. Correspondingly, the output V _g (FIG. 4d) of the digital-to-analog converter 20 also increases stepwise. As a result, the gain of the IF amplifier 11 also increases stepwise, so the output V _d of the detector 12 also increases stepwise (FIG. 4j).

When the output V _d of the wave detector 12 exceeds a specified threshold V _r , the output V _s of the threshold circuit 16 changes from "0" to "1". In the control circuit 17, P _d changes from “1” to “0” due to a change in V _s .
The first and second counters 18 and 19 are set to the down-counter state, and at the same time the operation control signal P _f of the second counter 19 is set from "0" to "1", and the counting operation is started. is started, and in conjunction with the first counter 18, a detailed counting operation is performed by clock pulses, and the counted value is decreased in steps. In contrast, digital
The output V _g of analog converter 20 also decreases in steps. As a result, the gain of the IF amplifier 11 also decreases stepwise, so the output V _d of the detector 12 also decreases. To explain this using the example of FIG. 5, as shown in FIG. 4j, at the start of gain control, the first counter 18 first performs a rough counting operation using the upper 4 bits. The counting operation at this time is 16 times when the second counter 19 is also used.
Since the roughness is twice as large, the time can be significantly reduced.
Then, the output V _d of the detector 12 becomes a specified threshold value V _r
At the point in time when the value exceeds 0, the first and second counters 18 and 19 are operated as an 8-bit counter in a closely linked manner.

When the output V _d of the detector 12 exceeds the specified threshold V _r again, the output V _s of the threshold circuit 16
changes from “1” to “0”. The control circuit 17 sets P _d from "0" to "1" and P _e and P _f from "1" to "0" as V _s changes again, and the first and second counters 18 , 19 is stopped and the latest count value is held until the next P _g arrives, and the gain is held constant. The control error corresponds to fine counting steps caused by the interlocking operation of the first and second counters 18 and 19.

When the output V _d of the detector 12 is input at a level equal to or higher than the specified threshold value V _r , the operation diagram shown on the right side of Fig. 4 shows that V _d is equal to or lower than the specified threshold value V _r . It is easy to understand that the operation sequence is the opposite when inputted with .

Note that the maximum time required for control (ie, the minimum pulse width of the pilot pulse signal) Tmax is expressed by equation (1).

Tmax=(G/△G ₁ +△G ₁ /△G ₂ )t…(1) where G: Receiver gain change range △G ₁ : Gain control sensitivity for one clock pulse by the first counter 18 △G ₂ : Gain control sensitivity for one clock pulse by the first and second counters 18 and 19 t: Repetition period of clock pulse Tmax: Maximum required control time For example, when the first and second counters 18 and 19 perform 4-bit up/down First counter 18 with down counter
If the second counter 19 is 4 bits from the maximum bit (referred to as MSB) and 4 bits from the minimum bit (LSB) and is configured with 8 bits during interlocking operation, the LSB is 0.1 dB, that is, the control error △ G ₂ =
Assuming 0.1 dB, △G ₁ is 1.6 dB, the controllable receiver gain range G is 25.6 dB, and the maximum time required for control Tmax is the clock pulse period t = 0.1
If it is μs, it is 3.2μs.

Although the AGC circuit has been described in the above embodiment, it goes without saying that the present invention can also be applied to an inter-channel gain balancing circuit in a multi-channel receiver configuration.

As described above, according to the present invention, the open-loop control circuit is configured so that a specified control error is achieved within the time of the pulse width of the pilot pulse signal. This has the effect of realizing a high-speed AGC circuit that responds sufficiently to fast gain changes.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of the AGC circuit of a conventional radar receiver, FIGS. 2 a to g are signal waveform diagrams of each part of FIG. 1, and FIG. 4A to 4L are waveform diagrams of each part in FIG. 3, and FIG. 5 is a diagram showing a specific example of the first and second counters shown in FIG. 3. 11...gain control circuit, 12...detector, 16
...Threshold circuit, 17...Control circuit, 1
8...First counter, 19...Second counter, 2
0...Digital/analog converter, 21...Clock pulse generator, 100...AGC circuit. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1 Automatic gain control of a radar receiver that injects a pilot pulse signal of a specified level from the receiver input terminal during the radar idle period and performs automatic gain control so that the pilot pulse signal level at the receiver output terminal becomes a constant value. The circuit includes a clock generator that generates clock pulses, a first counter that roughly down-counts or up-counts the clock pulses, and a clock pulse that finely down-counts or up-counts the clock pulses in conjunction with the first counter. a second counter that converts the counting outputs of the two counters into analog signals; a gain control circuit that is controlled by the analog signal; and a detector that detects the output of the gain control circuit. a threshold circuit that compares the output level of the detector with a predetermined threshold; and a threshold circuit that determines operating conditions for up-counting or down-counting of both counters based on the output of the threshold circuit, Only the first counter is operated from the edge point until the output of the threshold circuit changes, and the first,
An automatic gain control circuit for a radar receiver, comprising: a control circuit that operates a second counter in conjunction with each other and stops the operation of both counters when the output of the threshold circuit changes again.