JPS6256675B2 - - Google Patents
Info
- Publication number
- JPS6256675B2 JPS6256675B2 JP58008774A JP877483A JPS6256675B2 JP S6256675 B2 JPS6256675 B2 JP S6256675B2 JP 58008774 A JP58008774 A JP 58008774A JP 877483 A JP877483 A JP 877483A JP S6256675 B2 JPS6256675 B2 JP S6256675B2
- Authority
- JP
- Japan
- Prior art keywords
- junction
- damping
- disposed
- josephson
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000013016 damping Methods 0.000 claims description 30
- 239000002887 superconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 15
- 239000010931 gold Substances 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000010955 niobium Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910000765 intermetallic Inorganic materials 0.000 description 2
- HTUMBQDCCIXGCV-UHFFFAOYSA-N lead oxide Chemical compound [O-2].[Pb+2] HTUMBQDCCIXGCV-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- GPYPVKIFOKLUGD-UHFFFAOYSA-N gold indium Chemical class [In].[Au] GPYPVKIFOKLUGD-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 229910000464 lead oxide Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は共振による回路の誤動作を防止するダ
ンピング抵抗を具備したジヨセフソン３接合量子
干渉素子に係り、詳しくは該ジヨセフソン３接合
量子干渉素子に於けるダンピング抵抗の配設構造
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a Josephson three-junction quantum interference device equipped with a damping resistor to prevent circuit malfunctions due to resonance, and more specifically, to a Josephson three-junction quantum interference device. This invention relates to the arrangement structure of damping resistors.
(b) 技術の背景
第１図はジヨセフソン３接合量子干渉素子の等
価回路を示したもので、図中Ｌはインダクタン
ス、Ｒは抵抗、J1，J2，J3はジヨセフソン接合を
表わしている。(b) Technical background Figure 1 shows the equivalent circuit of a Josephson three-junction quantum interference device, in which L represents inductance, R represents resistance, and J 1 , J 2 , and J 3 represent Josephson junctions. .
該図に示すように３接合量子干渉素子に於て、
接合J1，J2，J3に流れる電流比はI0，2I0：I0（I0
は接合に流れる臨界電流）に定められる。そして
接合は等価的にはコンデンサＣに置きかえられ、
超伝導配線のもつインダクタンスＬとともにLC
並列回路を構成する。従つてこの回路は共振を起
こし、第２図に示す電流（Ｉ）−電圧（Ｖ）特性
図のように、ギヤツプ電圧（Vg）より低い電圧
（Vres）で電流のピーク（Ires）を生じる。この
ため該３接合量子干渉素子は超伝導状態から常伝
導状態への図中直線abで示すような正常な遷移
が妨げられ、スイツチング・ゲートとしての正常
な動作が阻害される。 As shown in the figure, in the three-junction quantum interference device,
The current ratio flowing through junctions J 1 , J 2 , J 3 is I 0 , 2I 0 :I 0 (I 0
is defined as the critical current flowing through the junction). And the junction is equivalently replaced with a capacitor C,
LC along with the inductance L of superconducting wiring
Configure a parallel circuit. Therefore, this circuit causes resonance, and as shown in the current (I)-voltage (V) characteristic diagram shown in FIG. 2, a current peak (Ires) occurs at a voltage (Vres) lower than the gap voltage (Vg). For this reason, the three-junction quantum interference device is prevented from making a normal transition from a superconducting state to a normal conducting state as shown by the straight line ab in the figure, and its normal operation as a switching gate is inhibited.
(c) 従来技術と問題点
第３図は従来の３接合量子干渉素子に於ける制
御線を省略した状態の透視上面図イ及びそのＡ−
A′矢視断面図ロである。（制御線は図示平面の上
部に酸化シリコン等の絶縁膜を介し、一点鎖線Ｂ
−B′に沿つて通常２本配設される）
同図に示すように、従来回路の共振を防ぐ手段
として超伝導体からなるベース電極ＥBの下部
に、例えばAu：In＝１：２の組成を有する金−
インジウム金属間化合物AuIn2からなるダンピン
グ抵抗ＲD1，ＲD2，ＲD3を、各ジヨセフソン接合
J1，J2，J3間をそれぞれ接続する形で三角形に配
設していた。なお第３図に於て、１はシリコン基
板、２は熱酸化膜、３はニオブ（Nb）からなる
グランド・フレーン、４は酸化ニオブ（Nb2O5）
膜、５は酸化シリコン（SiO）絶縁膜、６はゲー
ト酸化膜、７はSiO絶縁膜、ＥCはカウンタ電極
を示している。(c) Prior art and problems Figure 3 is a perspective top view of a conventional three-junction quantum interference device with control lines omitted.
It is a cross-sectional view B as viewed from the A′ arrow. (The control line is connected to the upper part of the illustrated plane through an insulating film such as silicon oxide, and
-B')) As shown in the figure, as a means to prevent resonance in the conventional circuit, a base electrode E B made of a superconductor, for example, with Au:In=1: Gold with the composition -
Damping resistors R D1 , R D2 , R D3 made of indium intermetallic compound AuIn 2 are connected to each Josephson junction.
They were arranged in a triangle with J 1 , J 2 , and J 3 connected to each other. In Fig. 3, 1 is a silicon substrate, 2 is a thermal oxide film, 3 is a ground plane made of niobium (Nb), and 4 is niobium oxide (Nb 2 O 5 ).
5 is a silicon oxide (SiO) insulating film, 6 is a gate oxide film, 7 is a SiO insulating film, and E C is a counter electrode.
第４図は上記のようにダンピング抵抗を三角形
に配接した従来の３接合量子干渉素子の等価回路
図を示したものであるが、この図から明らかなよ
うに上記抵抗配置に於ては各接合間の共振をおさ
えるダンピング効果を、それぞれの抵抗でうけも
つことになる。（図中J1，J2，J3はジヨセフソン
接合、ＲD1，ＲD2，ＲD3は三角形の一辺を形成す
るダンピング抵抗、Ｌはインダクタンス、I0は臨
界電流、Ｒは回路抵抗）
この場合ダンピング抵抗の抵抗値は次のように
して求められる。即ち接合を流れる電流比がI0：
2I0：I0の３接合量子干渉素子は、第５図に２次等
価回路を示すような、接合を流れる電流比がI0：
I0の２接合量子干渉素子が並列になつたものと等
価と考えられる。（Ｌはインダクタンス、Ｒはダ
ンピング抵抗、Ｃは接合のキヤパシタンス、Ｊは
接合）
そして、該等価回路の対称性から片側のLCR
回路で考えてよい。そこでこの時の回路方程式は
次式のように置ける。 Figure 4 shows an equivalent circuit diagram of a conventional three-junction quantum interference device in which damping resistors are arranged in a triangular shape as described above.As is clear from this figure, in the above resistor arrangement, each Each resistor has a damping effect that suppresses resonance between the junctions. (In the figure, J 1 , J 2 , and J 3 are Josephson junctions, R D1 , R D2 , and R D3 are damping resistors forming one side of the triangle, L is inductance, I 0 is critical current, and R is circuit resistance.) In this case The resistance value of the damping resistor is determined as follows. In other words, the current ratio flowing through the junction is I 0 :
In a three-junction quantum interference device with 2I 0 :I 0 , the current ratio flowing through the junction is I 0 :
This is considered to be equivalent to two I 0 junction quantum interference devices arranged in parallel. (L is the inductance, R is the damping resistance, C is the capacitance of the junction, and J is the junction) From the symmetry of the equivalent circuit, one side of the LCR
You can think of it in terms of circuits. Therefore, the circuit equation at this time can be set as follows.
２／ＬＶ＋２／Ｒ ｄＶ／ｄｔ＋Ｃｄ２Ｖ／ｄｔ２＝
０ （Ｖ：電圧）
Ｖ＝Ae〓t（α：定数、ｔ：時間、Ａ：定数）
と置くと
共振を起こさない条件としてはαが一重根を持つ
ことが必要で、その時の抵抗Rcrは
Rcr＝（Ｌ／２Ｃ）〓
で与えられる。 2/LV+2/R dV/dt+Cd 2 V/dt 2 =
0 (V: voltage) V=Ae〓 t (α: constant, t: time, A: constant)
If you put it as As a condition for not causing resonance, it is necessary that α has a single root, and the resistance Rcr in this case is given by Rcr=(L/2C)〓.
この抵抗値が３接合量子干渉素子に於て、外側
の接合と内側の接合間の共振をおさえるダンピン
グ抵抗となる。即ちＲD1＝R′D2＝（Ｌ／2C）〓と
なる。又外側の接合間の共振をおさえるダンピン
グ抵抗ＲD3はインダクタンスを2Lとして求めら
れＲD3＝（Ｌ／Ｃ）〓で与えられる。 This resistance value becomes a damping resistance that suppresses resonance between the outer junction and the inner junction in the three-junction quantum interference device. That is, R D1 =R' D2 =(L/2C). Furthermore, the damping resistance R D3 for suppressing resonance between the outer junctions is determined by setting the inductance to 2L and is given by R D3 =(L/C).
量子化条件LI0＝Φ０／４（Φ：磁束量子2.07〔Ｖ／
ｍ〕）から各接合を流れる電流I0をI0＝0.044
〔mA〕とすると、インダクタンスＬ＝11.8
〔PH〕となる。接合の電流密度はj0＝1400〔Ａ／
cm2〕であり、電極が鉛合金の場合電流密度j0と酸
化膜厚djの関係式
j0〔Ａ／cm2〕＝２．２０７×１０５／ｄｊ〔ｎｍ〕e
−1.57872djから酸化
膜厚djを求めＣ＝εrε0S／dj（εr：比誘電率、
ε０：真空誘電率、Ｓ：接合面積）より接合のキ
ヤパシタンスＣを求めるとＣ＝0.14〔PF〕とな
り、これからダンピング抵抗ＲD1，ＲD2，ＲD3は
次のように定まる。 From the quantization condition LI 0 = Φ 0 /4 (Φ: magnetic flux quantum 2.07 [V/m]), the current I 0 flowing through each junction is I 0 = 0.044
If [mA], inductance L = 11.8
It becomes [PH]. The current density of the junction is j 0 = 1400 [A/
cm 2 ], and when the electrode is a lead alloy, the relation between current density j 0 and oxide film thickness dj is j 0 [A/cm 2 ]=2.207×10 5 /dj [nm] e
Calculate the oxide film thickness dj from −1.57872dj C=ε r ε 0 S/dj (ε r : relative dielectric constant,
The capacitance C of the junction is determined from ε0 : vacuum dielectric constant, S: junction area), and it becomes C=0.14 [PF]. From this, the damping resistances R D1 , R D2 , and R D3 are determined as follows.
ＲD1＝ＲD2＝（Ｌ／2C）〓＝6.49〔Ω〕
ＲD3＝（Ｌ／Ｃ）〓＝9.18〔Ω〕
電極が鉛系合金の場合に、抵抗材料はふつ化カ
ルシウム（CaF2）型結晶構造を持つ金属間化合物
AuIn2が用いられ、その抵抗領域はシート抵抗で
２〜0.1〔Ω／□〕である。このことから今シー
ト抵抗を２〔Ω／□〕とし幅２〔μｍ〕としてダ
ンピング抵抗ＲD1，ＲD2，ＲD3の長さを求めると
ＲD1及びＲD2の長さl1及びl2が6.49〔μｍ〕に、Ｒ
D3の長さl3が9.18〔μｍ〕となる。そこで第６図
に示すパターン形状図のように、ループ間隔ｄL
が6.5〔μｍ〕程度必要になるので、セル寸法は
下部電極の幅ｗEを２〔μｍ〕ルール（配線幅を
２〔μｍ〕に規定する設計基準）で通常用いられ
る10〔μｍ〕に規定すると、セルの長さｌC＝210
〔μｍ〕、セルの幅ｗC＝26〔μｍ〕となり、セル
面積は5460〔μm2〕となる。なお図中l1はＲD1の
長さ6.49〔μｍ〕、l2はＲD2の長さ6.49〔μｍ〕、l3
はＲD3の長さ9.18〔μｍ〕、J1，J2，J3は接合を示
す。 R D1 = R D2 = (L/2C) = 6.49 [Ω] R D3 = (L/C) = 9.18 [Ω] When the electrode is a lead-based alloy, the resistance material is calcium fluoride (CaF 2 ). Intermetallic compounds with type crystal structure
AuIn 2 is used, and its resistance range is 2 to 0.1 [Ω/□] in terms of sheet resistance. From this, if the sheet resistance is 2 [Ω/□] and the width is 2 [μm], and the lengths of the damping resistors R D1 , R D2 , and R D3 are calculated, the lengths l 1 and l 2 of R D1 and R D2 are 6.49 [μm], R
The length l 3 of D3 is 9.18 [μm]. Therefore, as shown in the pattern shape diagram shown in Fig. 6, the loop interval d L
Since approximately 6.5 [μm] is required for the cell dimensions, the width of the lower electrode w E is set to 10 [μm], which is normally used in the 2 [μm] rule (design standard that specifies the wiring width as 2 [μm]). Then, the cell length l C = 210
[μm], the cell width w C =26 [μm], and the cell area is 5460 [μm 2 ]. In the figure, l 1 is the length of R D1 , 6.49 [μm], l 2 is the length of R D2 , 6.49 [μm], and l 3
The length of R D3 is 9.18 [μm], and J 1 , J 2 , and J 3 indicate junctions.
以上説明したように、ダンピング抵抗を三角形
に配設した従来の３接合量子干渉素子に於ては、
共振による誤動作を防止する抵抗を設けたことに
よつて、この抵抗に必要な長さのために外側の接
合J1及びJ3と内側の接合J2の間のループ間隔ｄL
が6.5〔μｍ〕程度必要であり、そのためにセル
面積が増大してジヨセフソン集積回路の集積度が
低下するという問題があつた。 As explained above, in the conventional three-junction quantum interference device in which the damping resistors are arranged in a triangle,
By providing a resistor to prevent malfunctions due to resonance, the loop spacing d L between the outer junctions J 1 and J 3 and the inner junction J 2 due to the required length of this resistor
The cell area is required to be about 6.5 [μm], which causes the problem that the cell area increases and the degree of integration of Josephson integrated circuits decreases.
(d) 発明の目的
本発明はジヨセフソン３接合量子干渉素子に於
て、共振による回路の誤動作を防止するためのダ
ンピング抵抗の、セル面積を増大せしめることの
ない配設構造を提供するものであり、その目的と
するところはジヨセフソン集積回路素子の集積度
を向上せしめるにある。(d) Purpose of the Invention The present invention provides a structure for arranging a damping resistor for preventing malfunction of the circuit due to resonance in a Josephson three-junction quantum interference device without increasing the cell area. Its purpose is to improve the degree of integration of Josephson integrated circuit devices.
(e) 発明の構成
即ち本発明はジヨセフソン集積回路素子に於
て、基板と、基板上に配設された超伝導体よりな
るグランド・プレーンと、該グランド・プレーン
上に配設された絶縁皮膜と、該絶縁皮膜上に配設
され３端子の星形形状を有するダンピング抵抗
と、一部が該ダンピング抵抗の端子上に延在され
該ダンピング抵抗によりほぼ中央部と２つの開放
端部とが橋絡状に接続された超伝導体よりなるベ
ース電極と、該ベース電極の表面に配設されたゲ
ート酸化膜と、前記３つの端子に対応して該ゲー
ト酸化膜上に配設された超伝導体よりなるカウン
タ電極とを備えてなることを特徴とする。(e) Structure of the Invention In other words, the present invention provides a Josephson integrated circuit device that includes a substrate, a ground plane made of a superconductor disposed on the substrate, and an insulating film disposed on the ground plane. , a damping resistor disposed on the insulating film and having a three-terminal star shape, and a portion extending over the terminals of the damping resistor, the damping resistor forming a substantially central portion and two open ends. A base electrode made of a superconductor connected in a bridge shape, a gate oxide film disposed on the surface of the base electrode, and a superconductor disposed on the gate oxide film corresponding to the three terminals. It is characterized by comprising a counter electrode made of a conductor.
(f) 発明の実施例
以下本発明を実施例について第７図に示す星形
のダンピング抵抗配置図、第８図に示す同星形配
置等価回路図、第９図に示すセル上面の模式図、
第１０図に示す一実施例の透視上面図イ及びＡ−
A′矢視断面図ロを用いて詳細に説明する。(f) Embodiments of the Invention Examples of the present invention will be described below with reference to the star-shaped damping resistor arrangement diagram shown in FIG. 7, the star-shaped equivalent circuit diagram shown in FIG. 8, and the schematic diagram of the top surface of the cell shown in FIG. ,
Transparent top views A and A- of one embodiment shown in FIG.
This will be explained in detail using A' arrow sectional view B.
第７図に示すようにダンピング抵抗として抵抗
R1，R2，R3を星形に接続する本発明の構造に於
ては、先に示した従来の三角形配置の場合と異な
り、各接合J1，J2，J3間のダンピングは、星形に
接続された抵抗の二つの和R1＋R2，R1＋R3，R2
＋R3で利くことになる。（ＥBは下部電極）
この状態の等価回路図が第８図で、図中J1，
J2，J3はジヨセフソン接合、R1，R2，R3はダン
ピング抵抗を構成する抵抗、Ｌはインダクタン
ス、I0は臨界電流、Ｒは回路抵抗を示す。 As shown in Figure 7, a resistor is used as a damping resistor.
In the structure of the present invention in which R 1 , R 2 , and R 3 are connected in a star shape, the damping between each junction J 1 , J 2 , and J 3 is different from the conventional triangular arrangement shown above. , the sum of two resistors connected in a star shape R 1 + R 2 , R 1 + R 3 , R 2
+R 3 will give you an advantage. (E B is the lower electrode) The equivalent circuit diagram in this state is shown in Figure 8, where J 1 ,
J 2 and J 3 are Josephson junctions, R 1 , R 2 , and R 3 are resistances forming damping resistances, L is inductance, I 0 is critical current, and R is circuit resistance.
従来と同様の設計基準に基づいて計算すると外
側の接合J1，J3と内側の接合J2の間（インナー・
ループ）に対するダンピング抵抗R1＋R2及びR1
＋R3＝6.49〔Ω〕、外側の接合J1とJ3の間（アウ
タ・ループ）に対するダンピング抵抗R2＋R3＝
9.18〔Ω〕となり、対称性よりR2＝R3であること
からR1＝1.9〔Ω〕となる。 When calculated based on the same design criteria as before, the difference between the outer joints J 1 and J 3 and the inner joint J 2 (inner joint
damping resistance R 1 + R 2 and R 1
+R 3 = 6.49 [Ω], damping resistance between outer junctions J 1 and J 3 (outer loop) R 2 + R 3 =
9.18 [Ω], and since R 2 = R 3 due to symmetry, R 1 = 1.9 [Ω].
これらの値を用い、前述同様抵抗層のシート抵
抗Ｒ□＝２〔Ω／□〕とし２〔μｍ〕ルール（線
幅を２〔μｍ〕とする設計基準）で設計すると、
第９図に示すようにR1に相当する抵抗の長さl1＝
2.0〔μｍ〕、R2，R3に相当する抵抗の長さl2＝l3
＝4.59〔μｍ〕となり、従来構造で6.5〔μｍ〕
程度必要であつたループ間隔ｄLは２〔μｍ〕で
すむことになる。この２〔μｍ〕というループ間
隔は２〔μｍ〕ルールで設計する場合に、ダンピ
ング抵抗を設けない場合に必要な最小の間隔であ
るので、本発明の構造に於てはダンピング抵抗を
設けることによるセル面積の増大がないことを意
味している。そしてこの場合ベース電極幅ｗEを
従来通り10〔μｍ〕に規定すると、セルの長さｌ
C＝214〔μｍ〕、セルの幅ｗC＝22〔μｍ〕とな
り、セル面積は4708〔μm2〕となる。なおこのセ
ル面積は従来の約86〔％〕にあたる。 Using these values and designing with the 2 [μm] rule (design standard where the line width is 2 [μm]) with the sheet resistance R of the resistance layer = 2 [Ω/□] as described above,
As shown in Figure 9, the length of the resistor corresponding to R 1 1 =
2.0 [μm], length of the resistor corresponding to R 2 and R 3 l 2 = l 3
= 4.59 [μm], and 6.5 [μm] with the conventional structure
The loop spacing d L that was required is now only 2 [μm]. This loop spacing of 2 [μm] is the minimum spacing required when no damping resistor is provided when designing according to the 2 [μm] rule, so in the structure of the present invention, it is possible to This means that there is no increase in cell area. In this case, if the base electrode width w E is defined as 10 [μm] as before, the cell length l
C = 214 [μm], the cell width w C = 22 [μm], and the cell area is 4708 [μm 2 ]. This cell area is approximately 86% of the conventional cell area.
第１０図は上記算出値を用いて形成したジヨセ
フソン３接合量子干渉素子の一実施例に於ける、
制御線を省略した状態を示す透視上面図イ及びＡ
−A′矢視断面図ロである。 FIG. 10 shows an example of a Josephson three-junction quantum interference device formed using the above calculated values.
Transparent top views A and A showing a state where control lines are omitted
-A′ arrow cross-sectional view (b).
これらの図に於て、１はシリコン基板、２は厚
さ3000〔Å〕程度の熱酸化膜、３はスパツタリン
グ法等で形成した厚さ3000〔Å〕程度のニオブ
（Nb）超伝導接地膜（グランド・プレーン）、４
は陽極酸化法で形成した厚さ300〔Å〕程度の酸
化ニオブ（Nb2O5）膜、５は蒸着法で形成した厚
さ3000〔Å〕程度の一酸化シリコン（SiO）絶縁
膜、６は高周波プラズマ酸化法で形成した鉛・イ
ンジウムの酸化膜（PbO・In2O3）からなる厚さ50
〔Å〕程度のゲート酸化膜、７は蒸着法で形成し
たSiO絶縁膜、R1及びR2＋R3は蒸着後熱処理を行
う方法で形成した金・インジウム化合物
（AuIn2）からなる厚さ400〔Å〕程度のダンピン
グ抵抗、ＥBは蒸着法で形成した鉛（Pb）−イン
ジウム（In）−金（Au）・合金等超伝導体層から
なる厚さ2400〔Å〕程度のベース電極、ＥCは鉛
（Pb）−金（Au）あるいは鉛（Pb）−ビスマス
（Bi）金合等の超伝導体からなる厚さ5000〔Å〕
程度のカウンタ電極、J1，J2，J3はジヨセフソン
接合、ｄLはループ間隔（２μｍ）を示してい
る。 In these figures, 1 is a silicon substrate, 2 is a thermal oxide film with a thickness of about 3000 [Å], and 3 is a niobium (Nb) superconducting ground film with a thickness of about 3000 [Å] formed by sputtering method etc. (ground plane), 4
5 is a niobium oxide (Nb 2 O 5 ) film with a thickness of about 300 [Å] formed by an anodic oxidation method, 5 is a silicon monoxide (SiO) insulating film with a thickness of about 3000 [Å] formed by a vapor deposition method, 6 is a 50 mm thick lead/indium oxide film (PbO/In 2 O 3 ) formed by high-frequency plasma oxidation.
7 is a SiO insulating film formed by vapor deposition, and R 1 and R 2 + R 3 are gold-indium compounds (AuIn 2 ) formed by heat treatment after vapor deposition, with a thickness of 400 nm. A damping resistance of about [Å], E B is a base electrode with a thickness of about 2400 [Å] made of a superconductor layer such as lead (Pb)-indium (In)-gold (Au) alloy formed by vapor deposition, E C is made of a superconductor such as lead (Pb)-gold (Au) or lead (Pb)-bismuth (Bi) alloy with a thickness of 5000 Å.
J 1 , J 2 , and J 3 are Josephson junctions, and d L is the loop spacing (2 μm).
(g) 発明の効果
以上説明したように本発明によれば、ジヨセフ
ソン３接合量子干渉素子に、外側の接合と内側の
接合の間のループ間隔を増大せしめずに、共振に
よる回路の誤動作を防止するダンピング抵抗を具
備せしめることができる。(g) Effects of the Invention As explained above, according to the present invention, malfunction of the circuit due to resonance can be prevented in the Josephson three-junction quantum interference device without increasing the loop interval between the outer junction and the inner junction. A damping resistor can be provided.
従つて本発明はジヨセフソン集積回路素子の誤
動作防止及び集積度向上に極めて有効である。 Therefore, the present invention is extremely effective in preventing malfunctions and improving the degree of integration of Josephson integrated circuit devices.
第１図はジヨセフソン３接合量子干渉素子の等
価回路図、第２図は同電流−電圧・特性図、第３
図は従来構造の３接合量子干渉素子に於ける透視
上面図イ及びＡ−A′矢視断面図ロ、第４図は従
来の３接合量子干渉素子の等価回路図、第５図は
同２次等価回路図、第６図は従来構造のパターン
形状図、第７図は星形のダンピング抵抗配置図、
第８図は同星形配置の等価回路図、第９図は同セ
ル上面模式図、第１０図は本発明の一実施例に於
ける透視上面図イ及びＡ−A′矢視断面図ロであ
る。
図に於て、R1，R2，R3はダンピング抵抗を構
成する抵抗、Ｒは回路抵抗、J1，J2，J3はジヨセ
フソン接合、Ｌはインダクタンス、I0は臨界電
流、l1，l2，l3は抵抗の長さ、ｄLはループ間隔、
ｗEはベース電極幅、ｌCはセルの長さ、ｗCはセ
ルの幅、ＥBはベース電極、ＥCはカウンタ電極、
１はシリコン基板、２は熱酸化膜、３はグラン
ド・プレーン、４は酸化ニオブ膜、５及び７は一
酸化シリコン絶縁膜、６はゲート酸化膜を示す。
Figure 1 is an equivalent circuit diagram of Josephson three-junction quantum interference device, Figure 2 is its current-voltage characteristics diagram, and Figure 3 is the equivalent circuit diagram of Josephson three-junction quantum interference device.
The figures are a transparent top view A and a cross-sectional view taken along the line A-A' of a conventional three-junction quantum interference device, FIG. 4 is an equivalent circuit diagram of a conventional three-junction quantum interference device, and FIG. 5 is the same. The following equivalent circuit diagram, Figure 6 is a pattern shape diagram of the conventional structure, Figure 7 is a star-shaped damping resistor layout diagram,
FIG. 8 is an equivalent circuit diagram of the same star-shaped arrangement, FIG. 9 is a schematic top view of the same cell, and FIG. It is. In the figure, R 1 , R 2 , and R 3 are the resistances that constitute the damping resistance, R is the circuit resistance, J 1 , J 2 , and J 3 are Josephson junctions, L is the inductance, I 0 is the critical current, and l 1 , l 2 , l 3 are the lengths of the resistors, d L is the loop spacing,
w E is the base electrode width, l C is the cell length, w C is the cell width, E B is the base electrode, E C is the counter electrode,
1 is a silicon substrate, 2 is a thermal oxide film, 3 is a ground plane, 4 is a niobium oxide film, 5 and 7 are silicon monoxide insulating films, and 6 is a gate oxide film.
Claims (1)
るグランド・プレーンと、該グランド・プレーン
上に配設された絶縁皮膜と、該絶縁皮膜上に配設
され３端子の星形形状を有するダンピング抵抗
と、一部が該ダンピング抵抗の端子上に延在され
該ダンピング抵抗によりほゞ中央部と２つの開放
端部とが橋絡状に接続された超伝導体よりなるベ
ース電極と、該ベース電極の表面に配設されたゲ
ート酸化膜と、前記３つの端子に対応して該ゲー
ト酸化膜上に配設された超伝導体よりなるカウン
タ電極とを備えてなることを特徴とするジヨセフ
ソン集積回路素子。1. A substrate, a ground plane made of a superconductor disposed on the substrate, an insulating film disposed on the ground plane, and a three-terminal star shape disposed on the insulating film. a base electrode made of a superconductor, a portion of which extends over a terminal of the damping resistor, and a substantially central portion and two open ends are connected in a bridge-like manner by the damping resistor; It is characterized by comprising a gate oxide film disposed on the surface of the base electrode, and a counter electrode made of a superconductor disposed on the gate oxide film corresponding to the three terminals. Josefson integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58008774A JPS59135782A (en) | 1983-01-24 | 1983-01-24 | Josephson integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58008774A JPS59135782A (en) | 1983-01-24 | 1983-01-24 | Josephson integrated circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59135782A JPS59135782A (en) | 1984-08-04 |
| JPS6256675B2 true JPS6256675B2 (en) | 1987-11-26 |
Family
ID=11702231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58008774A Granted JPS59135782A (en) | 1983-01-24 | 1983-01-24 | Josephson integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59135782A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62214681A (en) * | 1986-03-14 | 1987-09-21 | Nec Corp | Josephson gate |
| US6642608B1 (en) * | 2002-07-31 | 2003-11-04 | Northrop Grumman Corporation | MoNx resistor for superconductor integrated circuit |
-
1983
- 1983-01-24 JP JP58008774A patent/JPS59135782A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59135782A (en) | 1984-08-04 |
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