JPH0225265B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a Josephson integrated circuit device having a Josephson junction.

(b) Background of the technology The direct current required for Josephson integrated circuit devices operating in cryogenic environments, such as those immersed in liquid helium, was supplied through electrical wires from power supplies at room temperature. However, the required current is several tens of A.
If the value is as large as this, the heat generated from the electrical resistance of the power supply will be several tens of watts or more, and the amount of evaporation of the refrigerant such as liquid helium will be too large. On the other hand, when high-voltage, low-current alternating current is supplied from a room-temperature device through an electric wire, the heat generated from the electric wire is reduced, but a rectifier that operates in an extremely low temperature environment is required.

Such a rectifier is shown in FIG.

An AC power supply is connected to the primary side of the superconducting transformer 1, and four sets of Josephson element arrays J ₁ to 1 are connected to the secondary side of the superconducting transformer 1.
Connect rectifier circuit 2 with bridge connection of _J4 . 1
The set of Josephson element arrays is made up of, for example, four Josephson elements connected in series, and the resistance in the voltage state is on the order of several ohms. A common offset current is passed through the control lines. 4 sets of offset currents
IC ₁ to _{IC 4} are in the direction shown in the figure. This rectifier circuit 2
When an LC smoothing circuit consisting of an inductance 3 and a capacitance 4 is connected to the capacitance 4, and the load circuit 5 is a Josephson logic circuit or the like in parallel with the capacitance 4, a low impedance load of about 1Ω is obtained.

During a half cycle of AC, if the direction of the current flowing from the secondary side of the transformer into the bridge is from the upper end of the bridge to the lower end as shown in Figure 2a, then J ₁ and
Since the critical current value of J ₄ is a small value, it transitions to a voltage state and becomes equivalent to a resistance of several Ω. At this time J ₂ ,
J ₃ remains in the zero voltage state since the critical current is a large value. In the other half cycle, the current flows from the lower end of the bridge to the upper end, so that J ₂ and J ₃ are in a voltage state, and J ₁ and J ₄ are in a zero voltage state, as shown in FIG. 2b. When the critical current values of J ₁ and J ₄ are approximated to zero, the bridge output voltage V ₀ (t) has a full-wave rectified waveform as shown in FIG. 2c.

The ripple content after passing through a smoothing circuit is 0.48/
(4πfs) given by ² LC. Here, fs is the AC frequency, which in this example is 300MHz. When the ripple content is 1%, the LC product is 3.3×10 ⁻¹⁸ sec ² .

(c) Prior art and problems In this case, if the inductance L is 10000PH, the capacitance C is 3.3×10 ^-10 F.
Therefore, if this is made as an integrated circuit, the inductance L will be 1 mm x 1 mm, and the capacitance C will be 1 mm.
The area is approximately 2 mm, and the smoothing circuit is 2 mm.
occupies an area of x2mm. When the chip size of Josephson integrated circuit device is 6 mm x 6 mm, the smoothing circuit occupies a considerably large area in the entire chip area, which has the disadvantage that the area where memory circuits and logic circuits are formed becomes small. Ta.

(d) Object of the Invention The object of the present invention is to solve the above-mentioned drawbacks and to enable a circuit having a Josephson junction, such as a memory circuit or a logic circuit, to occupy a sufficiently large area on a chip.

(e) Structure of the Invention The present invention to achieve the above object comprises a substrate, a superconductor layer provided on the substrate, and a superconductor layer provided on the superconductor layer via a first insulator. The circuit includes a ground plane and a Josephson junction provided on the ground plane via a second insulator, and the circuit and the superconductor layer are connected to the ground plane and the first and second insulators. It is characterized by being electrically connected through a window provided in an insulator.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the present invention, in which a is a top view of the chip and b is a sectional view taken along line A-A' of a.

In FIG. 3a, the superconducting transformer 1, rectifier circuit 2, and load circuit 5 of FIG. 1 are shown as blocks for simplicity. Further, the inductance 3 is formed in a meandering pattern as shown.

The inductance 3 and the capacitor are connected through a window 9.

The capacitor is shown in detail in Figure 3b. The substrate 8 made of silicon contains niobium (Nb).
A first ground plane 10 consisting of a silicon oxide (SiO) film 1 formed by vapor deposition is provided.
1 through a superconductor layer 12, e.g. Pb-In-Au
A lead-based alloy layer such as

Furthermore, a second ground plane 14 made of niobium (Nb) is provided via a SiO film 13 (first insulating film), and an inductance 3 is provided on this via an SiO 15 (second insulating film). It is being

A window 9 is provided in these SiO films 13, 15 and the ground plane 14, and an inductance 3
are connected to the superconductor layer 12 via a conductor 16.

In such a structure, a capacitor is formed between the superconductor layer 12 and the ground planes 10 and 12, and the capacitors formed above and below are connected in parallel. Therefore, a large capacity can be obtained.

As is clear from the figure, there is no capacitor on the surface where the circuit such as inductance 3 is formed, but the capacitor is formed below this circuit, so even if the area of the capacitor is large, the capacitor formed above There is no need to reduce the area of the circuit to be used. Taking a memory circuit as an example, a large capacity memory can be constructed.

Specifically, when the thickness of the SiO film was 1500 Å and the size was 5 mm x 5 mm, the capacitance C was 8.3 x 10 ^-9 F.

In this example, two capacitors connected in parallel were constructed using the first and second ground planes, but the ground plane 10 and the SiO film 11 were eliminated, and the superconductor layer 12 was provided directly on the substrate 8. It may also be a structure.

(g) Effects of the Invention As explained above, according to the present invention, since the capacitor is formed in the layer below the circuit in which the Josephson junction is formed, the area occupied by the circuit on the chip can be increased. , it is possible to increase the memory capacity and the number of logic gates.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a rectifying device related to the present invention,
FIG. 2 is a diagram explaining the operation, and FIG. 3 is a diagram showing an embodiment of the present invention. 2: rectifier circuit, 3: inductance, 8: substrate, 9: window, 12: superconductor layer, 13: first insulating film, 14: ground plane, 15: second insulating film, 16: conductor.

Claims (1)

[Claims] 1. A substrate, a superconductor layer provided on the substrate, a ground plane provided on the superconductor layer via a first insulator, and a second insulator provided on the ground plane. a circuit including a Josephson junction provided therein, and the circuit and the superconductor layer are electrically connected through windows provided in the ground plane and the first and second insulators. Josephson integrated circuit device characterized by: