JPS626390B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a keyed AGC (automatic gain control) circuit used in a video intermediate frequency (VIF) circuit of a television receiver.

A receiver that receives negatively modulated waves from television.
Peak value type AGC is normally used for AGC, but with this method, if large impulsive noise enters from the outside during the period between two horizontal synchronization signals, it will also operate due to that noise. Therefore, the gain of the receiver changes. In order to eliminate this effect, only the period of the horizontal synchronization signal is selected.
Keyed AGC is used for AGC and does not operate during other periods.

A conventional circuit of this kind is shown in Fig. 1. In the figure, IN ₁ is an input terminal to which a negative horizontal pulse is applied, IN ₂ is an input terminal to which a video signal is applied, and OUT is an AGC output terminal. This is the output terminal obtained. Q ₁ and Q ₂ are first and second transistors, whose emitters are connected in common, and these constitute a differential amplifier circuit, and the second transistor Q ₂
The video signal from the input terminal IN ₂ is applied to the base of the first transistor Q 1, and the power supply Vcc is applied to the base of the first transistor Q ₁ .
a resistor R ₁ and a resistor connected in series between and ground
A comparison potential is applied by a variable voltage circuit consisting of VR and resistor _R2 . and the first and second
By comparing the signal potentials applied to the bases of the second transistors Q ₁ and Q ₂ , an output can be taken out from the collector of the second transistor Q ₂ .

At this time, of the video signal applied to the base of the second transistor Q ₂ , the pedestal portion of the horizontal retrace period, horizontal synchronization signal period, or horizontal retrace period (hereinafter, these three types of periods are referred to as horizontal pulse periods). The first transistor Q 1 of the second transistor Q ₂ is forced only outside the horizontal pulse period in order to compare the potential of only the potential of the second transistor Q ₂ with the comparison signal applied to the base of the first transistor Q ₁ and output terminal
In order to clamp the AGC output obtained at OUT to a low potential level or a high potential level, a third transistor _Q3 is provided to short-circuit the emitter and collector of the second transistor _Q2 . each second transistor
Commonly connected to the emitter and collector of Q ₂ and horizontal pulse (period) to the base of the third transistor Q ₃
Apply. Here, in Fig. 1, a negative horizontal pulse is applied to the input terminal IN ₁ , and the resistors R ₃ and R ₄
The third transistor _Q3 is turned off only during the horizontal pulse period by the Zener diode ZD.

_Q4 is a fourth constant current source that supplies the differential amplifier circuit consisting of the first and second transistors _Q1 and _Q2 .
transistor, _R5 is a constant current source resistor inserted between the emitter of the fourth transistor _Q4 and ground, _R6 is a bias resistor, D is a bias diode, and _R7 is a bias resistor. It is. _R8 is a load resistor connected between the collector of the second transistor _Q2 and the power supply Vcc, E is the ground on the circuit, and S is the ground on the bipolar monolithic integrated circuit (hereinafter abbreviated as IC) structure. Substrate, or ground symbol.

However, such a circuit has the following drawbacks.

That is, when the circuit shown in FIG. 1 is configured with an IC, the base potential of the third transistor _Q3 is clamped to the potential determined by the resistor _R4 and the Zener diode ZD during periods other than the horizontal pulse period, while the AGC circuit Due to the output dynamics range requirement, there is a demand for a large potential drop across the resistor _R8 , so the potential at the output terminal OUT becomes lower than the potential at point a, and the voltage between the base and collector of the third transistor _Q3 is A vertically oriented pnp transistor is generated, with the substrate layer from the IC structure described later as the collector, the base of the third transistor Q ₃ as the emitter, and the collector of the third transistor Q ₃ as the base. An unnecessary current was flowing from Vcc through the resistor _R4 , the base of the transistor _R3 , and the substrate layer of the transistor _Q3 .

In view of the above points, the present invention has been made to eliminate such drawbacks, and its purpose is to provide a keyed AGC circuit that can eliminate the aforementioned drawbacks and simplify the circuit configuration.

In order to achieve such an objective, the present invention
A variable voltage for AGC adjustment is applied to the base of a first transistor that configures a differential amplifier circuit by connecting the emitters of a pair of transistors in common, and a detected composite video signal is applied to the base of a second transistor. , and a third transistor at the base of the first transistor.
Connect the collector or emitter of the transistor, connect the emitter or collector of the third transistor to ground or power line, and connect the horizontal sync pulse or horizontal pulse for keyed AGC through the resistor to the base of the third transistor. Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the keyed AGC circuit according to the present invention. In Figure 2, the same numbers as in Figure 1 indicate corresponding parts, IN ₁₁ is the input terminal to which the horizontal synchronizing pulse or horizontal pulse is applied, and IN ₁₂ is the input terminal to which the detected composite video signal is applied. be. Here, input terminals IN ₁₁ and
IN ₁₂ corresponds to input terminals IN ₁ and IN ₂ shown in FIG. 1, respectively. Of the first and second transistors Q ₁₁ and Q ₁₂ whose emitters are commonly connected to form a differential amplifier circuit, the collector of the first transistor Q ₁₁ is connected to the power supply Vcc, and the base is connected to the power supply Vcc.
It is connected to the mover of the variable resistor VR of a variable voltage circuit consisting of a resistor _R1 , a variable resistor VR, and a resistor _R2 connected in series between Vcc and ground, and the variable voltage (comparison potential) for AGC adjustment is connected to the movable element of the variable resistor VR. is configured to be applied. In addition, the collector of the second transistor _Q12 is connected to the output terminal OUT and also to the power supply Vcc via the resistor _R8 , and the base is connected to the input terminal _IN12 to which the detected composite video signal is applied. has been done.

On the other hand, the collector of the third transistor _Q13 is connected to the base of the second transistor Q12, and the collector of the third transistor _Q13 is connected to the base of the second transistor Q12.
The emitter of the transistor Q ₁₃ is grounded, and the base is connected via a resistor R ₃ to the input terminal IN ₁₁ to which the horizontal synchronization pulse or horizontal pulse is applied.

Further, the collector of the fourth transistor _Q14 for a constant current source supplied to the differential amplifier circuit is connected to the common connection point of the emitters of the first and second transistors _Q11 and _Q12 , The emitter of ₁₄ is grounded through resistor _R5 , and the base is a resistor inserted in series between the power supply Vcc and ground.
It is connected to the connection point between resistor R ₆ and diode D of a bias circuit consisting of R ₆ , diode D, and resistor R ₇ .

In the circuit configured in this way, a video signal and a comparison potential are applied to the bases of the second and first transistors Q ₁₂ and Q ₁₁ , respectively, and the first and second
By comparing the signal potentials applied to the transistors Q ₁₁ and Q ₁₂ , an output can be taken out from the collector of the second transistor Q ₁₂ or the first transistor Q ₁₁ . At the same time, a negative or positive horizontal pulse is applied to the base of the third transistor _Q13 via the resistor _R3 , and the potential at point b is constrained by grounding (or power supply potential) or by the third transistor _Q13 . keyed by avoiding
AGC can be achieved.

FIG. 3 is a diagram for explaining the operation of FIGS. 1 and 2, and shows the IC structure of a third transistor Q ₁₃ corresponding to the third transistor Q ₃ shown in FIG. 1. In Figure 3, NEDB is the N-type emitter diffusion layer, E is its electrode, PBDB is the P-type base diffusion layer, B is its electrode, NCEB is the N-type collector epitaxial layer, C is its electrode, and PSDB is the P-type isolation layer. The diffusion layer, S is its electrode, and PSSB is the P-type substrate layer. This P-type substrate layer PSSB is structurally connected to the P-type isolation diffusion layer PSDB with the same conductivity type, and is electrically isolated from the elements on other ICs. IOM is an insulating oxide film used to configure ICs. Here, electrode C,
E and B correspond to the collector, emitter, and base of the third transistor _Q13 , respectively.

In normal operation of an IC configured in this way, an N-type emitter diffusion layer NEDB, a P-type base diffusion layer PBDB, and an N-type collector epitaxial layer are formed.
NCEB is the emituta, base, and collector respectively.
As the npn transistor _Q13 , the emitter E maintains the lowest potential, the base B maintains a forward potential approximately 0.7 V higher than the emitter E, and the collector C maintains a sufficiently higher potential than the emitter E, thereby operating normally. However, when the transistor _Q13 is saturated and the potential of the collector C approaches the potential of the emitter E, the potential of the base B becomes higher than that of the collector C, and when this value becomes around 0.7V, the base B to collector C will move in the forward direction. It becomes a bias, and the P-type isolation diffusion layer PSDB and the P-type substrate layer PSSB are used as the collector layer, the P-type base diffusion layer PBDB is the P-type emitter layer, and the N-type collector epitaxial layer NCEB is the N-type base layer.
Transistor occurs.

Now, when the present invention is applied to an IC, the third transistor _Q13 is saturated and a parasitic PNP occurs with the base of the transistor _Q13 as the emitter and the substrate as the collector, and current flows from the base of the transistor _Q13 to the substrate. flows, but this means that the horizontal pulse signal is connected to the base of the third transistor _Q13 ~
This is part of the current that drives the emitter in the forward direction, and this current can be adjusted to any desired current by resistor _R3 , eliminating unnecessary current flowing from the power supply Vcc of the circuit shown in Figure 1. be able to.

As is clear from the above description, according to the present invention, unnecessary current can be eliminated and the function of keyed AGC can be achieved with a simple circuit configuration without using complicated means. Therefore, the practical effect is extremely large. Further, it is extremely effective in reducing costs due to the simplification of the configuration, reducing power consumption, and improving the performance and reliability of a television receiver using the present invention.

As described above, the present invention has significant effects compared to conventional circuits of this type, and is unique as a keyed AGC circuit used in the VIF circuit of a television receiver.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of a conventional keyed AGC circuit, Fig. 2 is a circuit diagram showing an embodiment of a keyed AGC circuit according to the present invention, and Fig. 3 is an explanation of the operation of Figs. 1 and 2. FIG. Q ₁₁ to _{Q 14} ...Transistor, _R1 to _R8 ...Resistor, VR...Variable resistor.

Claims (1)

[Claims] 1 A variable voltage for AGC adjustment is applied to the base of the first transistor, which configures a differential amplifier circuit by connecting the emitters of a pair of transistors in common, and
A detected composite video signal is applied to the base of the transistor, and the collector or emitter of a third transistor is connected to the base of the first transistor, and the emitter or collector of the third transistor is connected to ground or a power supply line. connect to,
A keyed AGC circuit characterized in that a horizontal synchronizing pulse or a horizontal pulse for keyed AGC is supplied to the base of the third transistor via a resistor.