JPS632161B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selective amplification circuit, and more particularly to a push-pull amplification circuit that selectively amplifies two or more input signals.

It is often necessary to selectively amplify two or more input signals with electrically different properties, for example, a broadband signal of 400 MHz or more and a low frequency signal, using a common amplifier circuit. For such an amplifier circuit, it is particularly important to amplify a wideband input signal without loss. Conventionally, there is a method of selectively amplifying two or more signals with a wideband amplifier circuit by inserting a switch in series in the signal path or connecting two or more signal paths in parallel, but the bandwidth is not necessarily high enough. This has the disadvantage that it is not sufficient and the circuit configuration becomes complicated.

Therefore, an object of the present invention is to provide a selective amplifier circuit that selectively amplifies two or more input signals with a simple circuit configuration while retaining the functions of a wideband amplifier circuit.

Another object of the present invention is to provide a selective amplifier circuit that does not employ the conventional circuit configuration of inserting a switch in series in a signal path or connecting two or more signal paths in parallel.

Before explaining the selective amplifier circuit according to the present invention, as an example to which the present invention is applied, a newly designed oscilloscope having a waveform storage function will be explained with reference to the block diagram of FIG. In FIG. 1, an input signal applied to an input terminal 10 is transmitted through an input circuit 11 consisting of a step attenuator, etc., an input buffer amplifier circuit 12, a vertical axis (hereinafter simply referred to as "vertical") amplifier circuit 13, and a vertical switch. circuit 14, delay circuit 15,
and is applied to a vertical deflection plate (not shown) of a cathode ray tube (CRT) 17 via a vertical output amplification circuit 16. The sawtooth wave generator 19 is connected to the buffer amplifier circuit 1
Internal signal from 2 or external trigger input terminal 1
A sawtooth wave signal is generated in synchronization with an external signal from 8. The sawtooth signal is generated on the horizontal time axis (hereinafter referred to as
The signal is applied to a vertical deflection plate (not shown) of the CRT 17 via a buffer amplifier circuit 20 (simply assumed to be horizontal), a horizontal switch circuit 21, and a horizontal output amplifier circuit 22. A part of the output signal of the vertical amplifier circuit 13 is
Vertical sampling circuit 25 via amplifier circuit 23
At the same time, a part of the output signal of the horizontal buffer amplifier circuit 20 is applied to the horizontal sampling circuit 26 via the amplifier circuit 24. The pulse generation circuit 27 applies a sampling pulse to the vertical sampling circuit 25 and also to the horizontal sampling circuit 26 via the delay circuit 28 . The sample signals output from the vertical and horizontal sampling circuits 25 and 26 are multiplexed by a switch circuit (or multiplexer) 29, converted into digital data by an analog-to-digital converter (ADC) 30, and then converted into digitized horizontal time signals. It is stored in a predetermined position of the storage device 31 determined by the axis data. The waveform information stored in the storage device 31 is read out at any time, converted into analog by a digital-to-analog converter (DAC) 32, and then
The signals are applied to vertical and horizontal output amplifiers 16 and 22 via switch circuits 33 and 34, respectively. Note that the switch circuits 14, 21, 33, and 34 are controlled by a switch control logic circuit 35.

A normal oscilloscope has circuits 11, 12, 1
3, 15, 16, 19, 20, 22 and CRT1
7, and displays the input signal applied to the input terminal 10 on the display screen of the CRT 17.
On the other hand, digital waveform storage devices using CRT are
Circuits 11, 12, 16, 19, 20, 22, 2
3, 24, 25, 26, 27, 28, 29, 3
0, 31, 32, 33, 34, 35 and CRT1
Consists of 7. In addition to being able to operate independently, the oscilloscope and digital waveform storage device described above can also:
Input signals can be displayed in real time and stored input signals can be displayed in a time-division manner.

The oscilloscope portion of FIG. 1 is well known to those skilled in the art and will not be described in detail. Vertical and horizontal sampling circuits 25 and 26 constituting the digital waveform storage device respectively sample the input signal and the sawtooth wave signal under the control of the pulse generator 27, and store the sampled signals in respective storage circuits (not shown).
Temporarily held in a capacitor (usually a small capacitor). The sample signals from the sampling circuits 25 and 26 are multiplexed at a constant speed (for example, with a period of 1 μs) in the switch circuit 29, and then sent to the ADC.
After digital conversion in step 30, the data are sequentially stored in appropriate storage locations in the storage device 31. The digital data in the storage device 31 is read out when necessary, converted into vertical and horizontal analog signals in the DAC 32, and then applied to the vertical and horizontal output amplifiers 16 and 22, respectively. Although not shown in the figure, the analog signal from the DAC 32 is transmitted to the CRT using a vector generator at multiple points (dots) or multiple short line segments.
displayed on 17 screens.

In the time division mode, the input signal is simultaneously displayed on the CRT 17 in real time along with the stored input signal.
The switch control logic circuit 35 includes the switch circuit 1
4, 21 and another switch circuit 33, 34 are alternately switched. That is, the period during which the input signal is displayed in real time is determined by the switch circuits 33 and 34.
Bypassing the output of DAC32 to the ground side,
Open switch circuits 14 and 21. On the other hand, during the period in which the waveform stored in the storage device 31 is displayed, the switch circuits 14 and 21 are closed, and the switch circuits 33 and 34 are switched to apply the output of the DAC 32 to the output amplifiers 16 and 22. The delay circuit 15 is
In the real-time mode, the leading edge of a high-speed pulse waveform is displayed on the CRT 17, and in the stored waveform display mode, a delay circuit 28 is provided for the same purpose.

The vertical axis output amplification circuit 16 shown in FIG.
It is necessary to selectively amplify a real-time wideband signal containing a frequency component of 500 MHz or more and a relatively low-speed signal applied from the storage device 31 via the DAC 32. It is very convenient to use it in the output amplification circuit 16 of
FIG. 2 shows an example in which the present invention is applied to the amplifier circuit 16 of FIG.

The amplifier circuit 16 shown in FIG.
-26899). A first pair of transistors (hereinafter referred to as TR) 44, 45 and a second pair of TRs 46, 47 constitute an Ft doubler amplifier circuit, and are connected to the bases of the first TRs 44, 46 via input terminals 40, 41, respectively. Each half of the applied push-pull first input signal is amplified. The bases of the first TRs 44 and 46 are connected to the positive voltage source V+ via resistors 48 and 49, respectively.
On the other hand, the bases of the second TRs 45 and 47 are directly connected to the positive voltage source V+. 1st TR vs. 44,4
The emitter of 5 is connected through resistor 50, and TR
The emitter 44 is grounded via a resistor 52. The emitters of the second TR pair 46 and 47 are connected through a resistor 51, and the emitter of the TR 46 is grounded through a resistor 53. 1st TR vs. 44,
45 and the collectors of the second TR pair 46, 47 are in phase so as to add the collector outputs, and the collectors of the output terminal 4
It is cross-connected to 2,43.

The emitters of the second TRs 45, 47 are connected to the collectors of the third TR pair 54, 55 via resistors 56, 57, respectively, and the emitters of the third TR pair 54, 55 are connected via a resistor 58, respectively. It is connected to a negative voltage source V- via resistors 59 and 60. The base of the TR 54 is connected to the second input terminal 61 to which a second input signal, which is a single-ended input signal in this embodiment, is applied, and the base of the TR 55 is grounded. The second input terminal 61 is connected to a known switch 3 made of, for example, a field effect type TR.
It is grounded via 3. The switch 14 is the first
It has diodes 62 and 63 connected in series between the input terminals 40 and 41, and the connection point of the diodes 62 and 63 is connected to the switch drive TR 64 and the resistor voltage divider 68.
Connected to 69. A control signal from the switch control logic circuit 35 of FIG. 1 is applied to a control terminal 65 connected to the base of the drive TR 64.

The operation of the circuit shown in FIG. 2 will be explained below.
The third TR pair 54, 55 operates as a pair of constant current sources that flow a constant current to the emitters of the second TRs 45, 47 when the switch 33 is on. Voltage sources V+, V- and resistors 52, 53, 59, 60
The resistance values of are determined so that substantially equal currents flow through each of the resistors 52, 53, 56, and 57. When applying the input signals applied to the first input terminals 40 and 41 to the first TRs 44 and 46, a low voltage or negative voltage control signal is applied to the control terminal 65 to turn off the drive TR 64. Keep switching diodes 62, 63 off. As the input signal voltage applied to the first input terminal 40 increases, the collector current of the TR 44 flowing into the TR 45 via the resistor 50 increases, so the collector current of the TR 45 decreases. Since the signals input to the first input terminals 40 and 41 are push-pull input signals, the signal voltage applied to the input terminal 41 becomes lower as the signal voltage applied to the input terminal 40 becomes higher. Therefore,
The collector current of TR46 decreases and the collector current of TR47 increases. In other words, when the above-mentioned collector current is added as shown in FIG. 2, the collector current obtained from the output terminal 42 increases by a factor of two,
On the other hand, since the collector current from the output terminal 43 decreases by a factor of 2, the output current gain of this amplifier circuit is 1.
The bandwidth of the amplifier circuit, ie, Ft, is approximately doubled. For details of the operation of the Ft doubler explained in FIG. 2, please refer to the aforementioned Japanese Patent Publication No. 50-26899.

By the way, if the voltage of the control signal applied to the control terminal 65 becomes high (or positive) and the switch 33
When the switch drive TR 64 and the switching diodes 62 and 63 are turned on, the first input terminals 40 and 41 are shorted and the second input signal applied to the second input terminal is applied to the base of the TR 54. The third TR pair 54, 55 converts the second input signal into a push-pull collector output, and the TR
The collector outputs of 54 and 55 are TR45 and 47, respectively.
It is supplied to the emitsuta of. In this case, TRs 44 to 47 are all on, but resistors 50,
Due to the presence of TR 51 and the low emitter impedance of TRs 45, 47, the collector current of the third TR pair 54, 55 is taken directly from output terminals 43, 42 via TRs 45, 47, respectively.
In the above state, the TRs 54, 55, 45, and 47 constitute a well-known cascode-connected amplifier circuit.

In this way, the amplifier circuit 16 of FIG. 2, ie, the selective amplifier circuit according to the present invention,
The first input signal and the second input signal of the push-pull can be selectively amplified under the control of the push-pull. The selective amplification circuit according to the present invention includes the first TR pair 44, 45 and the first TR pair 44, 45.
Ft with 2TR pairs 46, 47 and other passive elements
Since a doubler circuit is configured, the first input signal having a wide bandwidth can be amplified without loss. Note that, if necessary, it is also possible to simultaneously amplify the first and second input signals.

FIG. 3 is a circuit diagram showing another embodiment of the selective amplification circuit according to the present invention. According to this embodiment, three input signals can be selectively amplified. In order to avoid complication, circuit elements in FIG. 3 that are the same as those in FIG. 2 are given the same reference numerals as in FIG. 2. The circuit of FIG. 3 includes the third TR pair 54 of FIG.
The circuit is similar to the circuit shown in FIG. 2 except that an amplifier circuit 72 is newly provided in front of the circuit 55. Amplification circuit 7
2 is the third input terminal 73, the control terminal 74, and TR7.
5 to 79, resistors 80 to 101, potentiometer 102, and the like. TR75 is a controllable current source, and TR76-79 act as a two-stage differential amplifier for the third input signal applied to the third input terminal 73. The third and second input signals are, in this example, an auxiliary vertical signal and an analog signal that is the output of the DAC 32 of FIG. 1, respectively.

A control signal is applied to the control terminal 74 to determine which of the second input signal and the third input signal is selectively amplified. When the control signal applied to control terminal 74 goes high, the emitter voltage of TR 75 becomes substantially zero, so that TRs 76 and 77 remain inactive. Therefore, the third input signal does not reach the subsequent TRs 78, 79, 54, 55 and the Ft doubler amplifier circuit. However, in order to amplify the second input signal, TR75 is in a conductive state and the second input signal is amplified.
A bias voltage is applied to the bases of the 3TR pair 54 and 55. The potentiometer 102 is for adjusting the center level of the amplification circuit that amplifies the second input signal, and the variable resistor 99 is a resistive attenuator that controls the level of the second input signal appearing at the output terminals 42' and 43'. It forms part of the On the other hand, when the control signal applied to the control terminal 74 becomes low level, the TRs 76, 7
7 becomes operational and amplifies the third input signal, and switch 33 is turned on to bypass the second input signal to ground. The reason why the collectors of the third TR pair 54 and 55 are grounded via capacitors 103 and 104, respectively, is to set the frequency characteristics of the amplifier circuit to desired values for the second and third input signals.
Resistor 56, capacitor 103, and resistor 57
The upper limit cutoff frequency of the amplifier circuit is determined by the time constant of the capacitor 104 and the time constant of the capacitor 104. TR70 and 71, which are directly connected to the base in the Ft doubler amplifier circuit, are
This is a summing amplifier that adds the collector currents of TRs 44 to 47, and its collector voltage is maintained at a constant value regardless of changes in the applied input signal.

As is clear from the above description, the selective amplification circuit according to the present invention adds a new amplification circuit to the Ft doubler amplification circuit, and maintains the broadband amplification characteristics of the Ft doubler amplification circuit while handling two or more input signals. It is also possible to selectively amplify the three input signals by providing another amplifier circuit before the additional amplifier circuit described above. The frequency response characteristics of the input signal applied to the added amplifier circuit can be easily modified by inserting a passive component network into the added amplifier circuit. Therefore, the selective amplification circuit of the present invention is very advantageous for selectively amplifying broadband signals and one or more other low frequency signals.

Although the preferred embodiments of the present invention have been described above, those skilled in the art can make modifications to the above-described embodiments depending on the application.

[Brief explanation of the drawing]

FIG. 1 is a simplified block diagram of an oscilloscope with a digital waveform storage function to which the selective amplifier circuit of the present invention is applied, FIG. 2 is a circuit diagram showing an embodiment of the selective amplifier circuit of the present invention, and FIG. FIG. 3 is a circuit diagram showing another embodiment of the selective amplification circuit of the invention. 44, 45...first transistor pair, 46, 4
7...Second transistor pair, 54, 55...Third
Transistor pair.

Claims (1)

[Scope of Claims] 1 includes a first, second, third and fourth transistor, the emitters of the first and second transistors are interconnected via an emitter resistor, and the emitters of the third and fourth transistors are interconnected via an emitter resistor; The bases of the second and third transistors are connected to a reference voltage source, the bases of the first and fourth transistors are connected to each other via a resistor, and the bases of the first and fourth transistors are used as first input terminals to which a first differential input signal is input. an amplifier in which the collectors of the first to fourth transistors are connected to a pair of output terminals in an in-phase relationship; the collectors are connected to the emitters of the second and third transistors, respectively; The fifth emitter connection made with the input terminal
and a sixth transistor, and first and second switch means connected to the first and second input terminals, respectively, for bypassing a signal that is not selected from the first or second input signal. selection amplification circuit.