JPS6322668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile recording device in which the recording surface cannot be directly viewed, such as a facsimile recording device using a solid-state recording head.
The present invention relates to a phase matching device for a facsimile recording device in broadcasting where no phase signal is sent out or facsimile broadcasting in a receiving state where no phase signal can be detected.
Conventionally, this type of equipment uses primary colored paper that allows the recording state to be directly viewed, because the reception conditions are unstable due to the short wave band used, and because some broadcasting stations do not transmit phase signals. The belt was rotated by a motor and a recording needle attached to the belt recorded. This method has the advantage of being able to directly see the recording location, so the phase position can be seen directly, but since the recording needle is scanned by a motor, there is a synchronization pull-in time when the motor starts rotating, and phase alignment is instantaneous. I couldn't call it. In other words, even if the motor is stopped and the motor is rotated when the phase signal reaches the phase matching position, the motor will not rotate synchronously immediately, so when it is drawn into synchronous rotation, the phase will not be matched.
Therefore, if you slightly change the frequency at which the motor is actually rotated, for example, if a motor that is rotating at 60Hz is rotated at 62.4Hz, the frequency will change by 4%, resulting in one line scanning (hereinafter referred to as "scanning"). ), the phase position is shifted by 4%. In this case, it takes 25 scans to return to the original phase position, so the time required for phase matching is a maximum of 24 scans. Furthermore, during this time, manually press a switch, etc. to achieve phase matching, visually check how the phase position shifts, and when the phase position shifts to the phase matching position, turn off the switch and return to the original frequency. It is necessary to return to 60Hz, which requires a lot of time and effort. As described above, the conventional phase matching method has drawbacks such as being limited to recording paper on which the recording area can be directly viewed, requiring a long time, and being troublesome to operate.

This invention solves these drawbacks and makes it possible to easily complete phase matching within one scan even in solid-state recording, etc., which is a recording method in which the recorded location cannot be seen directly. will be described in detail with reference to the accompanying drawings.

In Fig. 1, 1 is a scanning speed changeover switch S ₁
3 is a memory address designation counter to which a memory address designation clock signal is applied from the output terminal C of the clock generation circuit 2; A read/write memory for facsimile signals, 5 a recording paper fast forwarding information detection circuit into which the output signal of the recording paper fast forwarding switch _S2 is input via an inverter _I1 , and 6 a frequency dividing circuit 1 that is independent of the position of the switch _S1 . A paper feed clock supply circuit to which a constant frequency signal outputted from the output terminal B and an output signal from the recording paper fast-forward information detection circuit 5 are applied. Pulse motor drive circuit that drives motor 8, 9 is switch S ₃ for inputting a 1-digit value
The output of 10 is a decimal counter for one digit whose output is input via inverter I ₂ and NAND gate G ₁ , and the output of switch S ₄ is input via inverter I ₄ and NAND gate G ₄ . Decimal counter for 10 digits input by
The output of _S5 is inputted via the inverter _I3 , and a phase matching execution information holding circuit holds the input level. 12 is the start of each scan from the output of this holding circuit 11 and the output terminal E of the clock generation circuit 2. A phase matching start information supply circuit that receives a one-pulse phase setting clock signal generated at
The output signal of this supply circuit 12 is an AND gate G ₂
and G ₃ are applied to each one input. The other input of AND gate _G2 is clock generator circuit 2.
A clock signal for phase matching is applied from the output terminal D of the gate G2, and the output signal of this gate _G2 is a NAND gate.
applied to the other input of _G1 . And Gate G ₃
The output signal of the 1-digit decimal counter 9 is applied to the other input of the gate G3, and the output signal of the gate _G3 is applied to the other input of the NAND gate _G4 . 13
is a 7-segment display for displaying a one-digit numerical value driven by the output of the decimal counter 9 for one digit, 14
is a 7-segment display for displaying a 10-digit numerical value driven by the output of a 10-digit decimal counter 10. The outputs of counters 9 and 10 are also AND gates
_G5 , and the output of this gate _G5 is applied to the memory address designating counter 3, the phase matching implementation information holding circuit 11, and the phase matching start information supplying circuit 12, respectively.

Next, the basic operation will be explained. First, facsimile signals received and demodulated by a receiving section (not shown) are sequentially stored in each address of the memory 4 designated by the address designation counter 3. At this time,
The scale S shown in Fig. 2 shows where the signal corresponding to the phase position of the facsimile signal for one scan is stored (this is a scale in the line scanning direction near the recording paper outlet (not shown) of the main body of the facsimile recording device. (located in parallel with). That is, the facsimile signals stored in the memory 4 for one scan are sequentially read out according to designated addresses, and are recorded on the recording paper P shown in FIG. 2 by a recording section (not shown). Therefore, the address of the memory 4 can be replaced with the recording position on the recording paper P. From this, it can be seen that the phase matching state only requires phase positions at both ends of the recording paper P, so it is sufficient to store the phase positions in the upper and lower addresses of the memory 4. . Therefore, it is only necessary to check the phase position at which address it is stored, using the scale S, and move it so that it is stored in the upper and lower addresses of the memory 4. The number of divisions of the scale S can be set arbitrarily as it only determines how much the memory address should be divided, but it is usually assumed that the phase signal being sent is 5% of one scan. Considering this, it is preferable to divide it into 20 or more, and in this embodiment, it is divided into 32 as shown in FIG. Further, the numbers displayed on the scale S may be displayed from the right side or the left side, as will be described later.

Next, specific operations will be explained. In the case of reception conditions such as a facsimile signal without a phase signal or a phase signal that cannot be detected, automatic synchronization cannot be performed. Recording is being done. However, since the recording area cannot be seen, it is necessary to quickly feed the recording paper to a position where it can be seen. Therefore, the paper fast forward switch _S2 is turned on. When this switch _S2 is turned on, an L level (earth information) is supplied to the inverter _I1 , and its output becomes an H level (for example, +5V). By inputting this information to the recording paper fast-forwarding information detection circuit 5, this output shifts to H level (or L level) and maintains that state. The paper feed clock supply circuit 6 includes:
A constant frequency is supplied from the output terminal B of the frequency dividing circuit 1. This means that the higher the frequency at which the pulse motor 8 is driven, the faster the paper can be fed.
On the other hand, since the torque decreases and the pulse motor 8 cannot be driven, the frequency is fixed to the highest possible frequency that can maintain the required torque. The frequency supplied from the output terminal B of the frequency dividing circuit 1 is divided by a counter in the paper feed clock supply circuit 6, and a frequency for driving the pulse motor 8 is created therein. For example, let the frequency be 500Hz. When recording under normal reception conditions, only 8 pulses or 16 pulses at a frequency of 500 Hz are sent to the pulse motor drive circuit 7 in accordance with the cooperation coefficient for each scan.
supply to. This is to improve the paper feeding accuracy, and the paper is fed by dividing the distance that the paper must be fed for each scan into 1/8 or 1/16 with one pulse. Therefore, this can be done with any number of pulses.
In order to extract such a pulse, it is easy to extract it by resetting this counter at a terminal 4 or 5 stages after the stage from which 500 Hz is extracted from the counter in the paper feed clock supply circuit 6. be able to. A stage that can supply H level (or L level) transition information from the output of the recording paper fast feed information detection circuit 5 to such a circuit, and supply pulses according to the paper feeding distance without having to reset at the 4th or 5th stage. By resetting the recording paper fast-feeding information detection circuit 5 at , the normal paper-feeding speed can be restored. If the speed during fast forwarding is a scanning speed of 60 RPM and a cooperation coefficient of 576, the paper will be sent out at about 62.5 times the speed since normal recording will have 8 pulses per second and 500 pulses during fast forwarding. The phase position can be determined by visually observing the recorded portion sent out in this manner. In other words, if there is no phase signal, only the part corresponding to the phase position is not recorded, and if a phase signal is output but cannot be detected, only the part corresponding to the phase position has a higher phase width than other parts. This is because the corresponding width is recorded in black. Therefore, the numerical value of the scale to be compared with this position is input by switches S ₃ and S ₄ for inputting 1-digit and 10-digit numerical values.
Input the numerical value of the scale S corresponding to the phase position on the recording paper P. For example, if the phase position is 15 when compared to the scale S, press the 1-digit value input switch _S3 5 times, and press the 10-digit value input switch _S4 once.
Press twice. This operation performs the following operations.
When the one-digit value input switch _S3 is pressed five times, the input is provided to the NAND gate _G1 through the inverter _I2 each time. The input is a signal that transitions from L level to H level five times. Nand Gate G ₁ is H
Every time the level is input, an H level is output. At this time, the input from the AND gate _G2 is at L level, so five signals are input to the 1-digit decimal counter 9, which is counted and sent to the 7-segment display 13 for 1-digit numerical display. Display the number 5 on the screen. Next, turn the 10-digit numerical input switch _S4 to 1.
When pressed twice, it is input to NAND gate _G4 through inverter _I4 . The input from AND gate G ₃ to NAND gate G ₄ is a 1-digit decimal counter 10.
This is a carry input, but since this is at L level, the signal input from switch S ₄ for 10-digit numerical input is output from NAND gate G ₄ ,
One signal is input to the decimal counter 10, which is counted and the number 1 is displayed on the 7-segment display 14 for displaying 10-digit numerical values. Next, phase matching is completed by pressing the phase setting switch _S5 , and its operation will be explained below. By pressing the phase set switch _S5 , the inverter _I3
The H level information is stored in the phase matching implementation information holding circuit 1.
1, its output transitions to H level (or L level) and maintains that state. The phase matching start information supply circuit 12 receives the phase set clock signal, which is a pulse generated at the start of each scan, supplied from the output terminal E of the clock generation circuit 2 by being supplied with this transposed input. When this signal is input, the output of the phase matching start information supply circuit 12 shifts to H level (or L level) and maintains that state. As a result, the phase matching clock signal from the output terminal D of the clock generation circuit ₂ , which is input to the AND gate G2, is outputted from the AND gate _G2 . The phase matching clock signal is generated between the phase set clock signals, that is, for each scan, the number of phase matching clock signals is generated by the number of divisions of the scale. For example, if the scanning speed is 60 RPM, one scan is 1 second, so the phase matching clock at this time is 32 Hz, and if the scanning speed is 240 RPM, one scan is 1 second.
Since it is 0.25sec, it is set to 128Hz, and the clock signal is always supplied at the same frequency as the scale division. next,
The clock input from the AND gate _G2 is input to the one-digit decimal counter 9 through the NAND gate _G1 and starts counting. As mentioned above,
Switch S ₃ for inputting 1-digit and 10-digit numerical values in advance,
Since the number 15 is entered by S ₄ ,
Add to this and start counting from 16 with the first clock pulse. When there is a carry in the 1-digit decimal counter 9, it is output from the AND gate _G3 opened by the phase matching start information supply circuit 12,
It is input to a 10-digit decimal counter 10 through a NAND gate _G4 . Continuing to count up in this way, when the display on the 1-digit decimal counter 9 is 2 and the display on the 10-digit decimal counter 10 is 3,
In other words, when 32 is displayed, the AND gate
Through _G5 , clock generation circuit 2, memory 4,
Memory address specification counter 3, 1 digit and 10
To the digit decimal counters 9 and 10, the phase matching implementation information holding circuit 11, and the phase matching start information supply circuit 12,
Apply a reset. This completes phase matching.

Also, if the numbers are written in the opposite direction to the scale shown in Figure 2, that is, from the left, the decimal counters 9 and 10 should not count up, but count down and reset when the count reaches 0. Bye. To explain this using the scale S in Figure 2, since the number 15 has been input in advance, when this is counted up, it will be reset to 32, so the input phase matching clock will be
There are 17 pieces. Therefore, one scan, e.g. 60 RPM
In the case of , it is 1sec, so you will have to wait for 17/32 seconds. At this time, the phase position has moved to the address in the memory 4 corresponding to both ends of the recording paper P, so the clock generation circuit 2 and the memory address designation counter 3 are instantly reset, and the facsimile is started again from here. The signal may be written into the memory 4. This means that when the phase set switch _S5 is turned on and the phase set clock signal output from the output terminal E of the clock generation circuit 2 is input, phase matching is completed within one scan.

Moreover, if the numbers are written in the opposite direction to the scale S in FIG. 2, the number corresponding to 15 in FIG. 2 becomes 17.
Therefore, if you count down this number, the number of phase matching clocks becomes 0 at 17, so it can be seen that the same operation is performed.

Furthermore, it is easy to understand that the present invention can be applied as is, even if the recorded area is visible, if the recording method is electronic scanning, there is no need for fast forwarding.

As is clear from the description of the embodiments described above, according to the present invention, phase matching can be easily and instantaneously performed even in a recording method in which the recording location cannot be viewed directly. It can be used safely even in situations where the electric field is unstable, such as. Further, there are advantages such as increasing the utility value of recording paper other than conventional recording paper (recording paper on which the recorded area can be seen directly).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the fed recording paper and the scale. 1... Frequency dividing circuit, 2... Clock generation circuit, 3
...Memory address designation counter, 4...Memory, 5...Paper fast-forward information detection circuit, 6...Paper feed clock supply circuit, 7...Pulse motor drive circuit, 8...Pulse motor, 9...1 Decimal counter for digits, 10... Decimal counter for 10 digits, 11...
Phase matching implementation information holding circuit, 12...Phase matching start information supply circuit, 13...7 segment display for 1-digit numerical display, 14...7 segment display for 10-digit numerical display, _S1 ...Scanning speed switching Switch, S ₂ ...
...Chart paper fast forward switch, S ₃ ...Switch for 1-digit numerical value input, S ₄ ...Switch for 10-digit numerical value input, S ₅ ...
...Phase setting switch, _I1 to _I4 ...Inverter, _G1 to _G5 ...Gate, P...Recording paper, S...
scale.

Claims (1)

[Claims] 1. In a facsimile recording device in which a facsimile signal received and demodulated by a receiving unit is recorded on a recording paper by a recording unit, a scale formed at equal intervals parallel to the line scanning direction near the output port of the recording paper is used. a multi-digit numerical input switch to which a numerical value is set by reading the phase position recorded in advance on the recording paper for several lines on the scale of the scale; and a multi-digit numerical input switch for counting and storing the set numerical value. a decimal counter, a memory for storing the facsimile signal for at least one line scan, and a memory address designating counter that receives a memory address designation clock signal generated by a clock generation circuit and writes and reads data into the memory; A phase setting switch that sets phase matching implementation, a phase matching implementation information holding circuit that holds information indicating that the phase matching implementation is set, and a line scan using the held phase matching implementation information and the clock generation circuit. A phase matching start information supply circuit receives a phase set clock signal generated at the start and commands the start of phase matching, and the clock generating circuit determines the number of graduations of the scale during one line scanning period based on the phase matching start information. a first gate that outputs a signal to the multi-digit decimal counter to add (or subtract) the phase matching clock signal generated by the multi-digit decimal counter to the numerical value set and stored by the multi-digit numerical input switch; and a second gate circuit that generates a reset signal when the multi-digit decimal counter finishes counting for one line scan, and resets the memory address designation counter with the reset signal. A phase matching device in a facsimile recording apparatus, characterized in that the facsimile signal read from the memory is recorded on a recording paper by the recording section after performing phase matching.