JPS632486B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a capacitive coupling circuit for capacitively coupling input and output terminals of two circuits.

[Technical background of the invention]

There are various restrictions when attempting to increase the integration of semiconductor integrated circuits. In particular, there are significant restrictions on the number of pins on the package and permissible power. Semiconductor integrated circuit packages are generally standardized, with a fixed number of pins (for example, a 24-pin package or a 28-pin package), as well as a fixed allowable power.
Although it is possible to create a package with any number of pins and allowable power, this would be a special package and would be expensive. Therefore, it is usually necessary to design a circuit within a limited number of pins and allowable power.

By the way, when trying to increase circuit functions, the number of circuits and elements generally increases, and the number of pins and allowable power also increase. Therefore, if the number of pins and allowable power of a package are predetermined, the number of pins and allowable power of the required circuit may exceed the predetermined number of pins and allowable power. In some cases, it may not be possible to increase circuit functionality.

In cases where the number of pins on a package is predetermined, it is conceivable to directly connect each circuit instead of capacitively coupling each circuit in order to increase circuit functionality. That is, by directly connecting each circuit, the number of pins for connecting coupling capacitors can be reduced. However, when the circuits are directly connected, the DC drift component of the preceding circuit is transmitted to the subsequent circuit. Therefore, it becomes necessary to design the subsequent stage circuit in consideration of the influence of the DC drift component of the previous stage circuit, which makes it impossible to perform sufficient signal amplification or process large-amplitude signals.

In this way, if you try to reduce the number of pins on a package, you have to sacrifice circuit performance.
If you try to improve the performance of a circuit, the number of pins will increase. Therefore, in order to satisfy both the number of pins and the circuit performance, it is necessary to form the coupling capacitor within the semiconductor integrated circuit. However, when forming a coupling capacitor in a semiconductor integrated circuit, it is difficult to create a coupling capacitor with a large capacitance because parasitic capacitance is inserted in series with the coupling capacitor, and as a result, the coupling capacitor has a considerable impedance. I end up having one. Therefore, as shown in Figure 1, a coupling capacitor is usually used.
Emitter follower transistor on the input/output side of _C11
Q ₁₁ and Q ₁₂ are provided to reduce impedance. That is, the output signal of the previous stage circuit is first applied to the base of the emitter follower transistor _Q11 from the input terminal ₁₁ , and then supplied to the base of the emitter follower transistor _Q12 on the output side via the capacitor C11. Ru. And this transistor
It is supplied from the emitter of _Q12 to the subsequent circuit via the output terminal 12. In addition, in the figure, Vcc is the power supply, E ₁
is the output DC voltage of the previous circuit, R ₁₁ and R ₁₂ are the emitter resistances of transistors Q ₁₁ and Q ₁₂ , respectively, and 1
3 is a terminal to which the base bias voltage E ₂ of the transistor Q ₁₂ is applied, and R ₁₃ is the base bias resistance of the transistor Q ₁₂ .

[Problems with background technology]

However, the capacitive coupling circuit having the above structure has a problem in that the chip area of the semiconductor integrated circuit becomes large due to the formation of the coupling capacitor _C11 in the semiconductor integrated circuit. Another disadvantage is that the power consumption of the entire circuit increases by the power consumption proportional to the current flowing through the emitter follower transistors Q ₁₁ and Q ₁₂ . This emitter follower transistor
The power consumption due to Q ₁₁ and Q ₁₂ may not be much of a problem when the number of circuits is small, but when the number of circuits increases due to high integration, a capacitive coupling circuit as shown in Figure 1 may also be used. Therefore, even if the absolute value of the power consumption of each emitter follower transistor Q ₁₁ and Q ₁₂ is small, the total power becomes large. As a result, circuit design is greatly affected in terms of allowable power. Considering the above points,
In semiconductor integrated circuits that are becoming highly integrated, it is important to reduce the power consumption of individual circuits as much as possible. That is, even if the reduction in power consumption of each individual circuit is small, since a highly integrated semiconductor circuit has a large number of circuits, the total power consumption that is reduced from the viewpoint of the entire circuit becomes large. As a result, if it is necessary to design a circuit around the limit of exceeding or not exceeding the allowable power, the circuit design will be subtly affected.

[Purpose of the invention]

This invention was made in order to deal with the above-mentioned circumstances, and is capable of reducing power consumption and contributing to a reduction in the chip area of a semiconductor integrated circuit when integrated circuits, and is a capacitive coupling suitable for integrated circuits. The purpose is to provide circuits.

[Summary of the invention]

Therefore, if the present invention is explained using the circuit shown in FIG. 2, for example, a transistor Q ₂₁ has a base to which the output signal of the previous stage circuit is applied, a collector is connected to the emitter of the transistor Q ₂₁ , and the emitter is connected to the output signal of the latter stage circuit. Transistor Q ₂₂ connected to the input side of the circuit and grounded via resistor R ₂₂
and the emitter of transistor Q ₂₁ and the transistor
By providing a capacitor C ₂₁ inserted between the base of Q ₂₂ , transistors Q ₂₁ and Q ₂₂ can be driven with a common drive current, and
The structure is such that the capacitance of the capacitor _C21 can be reduced by the junction capacitance generated between the collector and base of the transistor _Q22 .

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In Figure 2, the transistor
The base of Q ₂₁ is provided with an input terminal 21 to which the output signal of the previous stage circuit is applied. The collector of this transistor _Q21 is connected to the power supply Vcc, and the emitter is connected to the collector of the transistor _Q22 and to the base of the transistor _Q22 via the capacitor _C21 . transistor
The base of Q ₂₂ is connected via a resistor R ₂₁ to a terminal 22 to which a base bias voltage E ₂ is applied.
The emitter of the transistor _Q22 is connected to the output terminal 23 and grounded via a resistor _R22 . Note that the input DC level of the subsequent circuit is determined by the base bias voltage _E2 .

According to the above configuration, the output signal of the previous stage circuit is
Applied to the base of transistor _Q21 . This output signal is output from the emitter of transistor Q ₂₁ and applied to the base of transistor Q ₂₂ via capacitor C ₂₁ . The output signal applied to this base is output from the emitter of transistor _Q22 and supplied to the subsequent circuit.

According to this embodiment described in detail above, the following effects are achieved. First, in the circuit shown in Figure 1, if a current of 1 mA were to flow through each transistor Q ₁₁ and Q ₁₂ , the total drive current of transistors Q ₁₁ and Q ₁₂ would be 2 mA, but as shown in Figure 2. In this circuit, a completely common drive current flows through transistors Q ₂₁ and Q ₂₂ , so the total drive current is 1 mA, half of the conventional one.
Therefore, the power consumption will be halved. Further, the coupling capacitor is a parallel capacitance between the capacitor C ₂₁ and the base-collector junction capacitance of the transistor Q ₂₂ . Therefore, the capacitance value of capacitor _C21 is Ca,
If the capacitance value of the junction capacitor is Cb, the capacitance value of the coupling capacitor is Ca+Cb. This changes the capacitance value of capacitor C ₂₁ to capacitor C ₁₁ shown in Figure 1.
The capacitance value can be reduced by Cb, and the chip area of the semiconductor integrated circuit can be reduced.

As described above, the capacitive coupling circuit of this embodiment can reduce power consumption by half compared to the circuit shown in FIG. In this case, even if the absolute value of the power consumption that can be reduced is very small compared to the power consumption of the entire circuit, if the number of circuits is large, such as in highly integrated semiconductor integrated circuits, the power consumption that can be reduced is Total power increases. As a result, it becomes very effective when designing a circuit in a manner where the power consumption of the entire circuit exceeds or does not exceed the allowable power. This also applies to the reduction in chip area due to capacitor _C21 . That is, even if the absolute value of the chip area that can be reduced by each capacitive coupling circuit is small, the total area becomes very large and can greatly contribute to reducing the chip area.

FIG. 3 is a circuit diagram showing a second embodiment of the invention. In the previous embodiment, 1
A capacitive coupling circuit in which two subsequent circuits are connected has been described. On the other hand, FIG. 3 shows the configuration of a capacitive coupling circuit in which, for example, two subsequent circuits are capacitively coupled to a preceding circuit. In this case, one more transistor Q ₂₃ is added in addition to the transistors Q ₂₁ and Q ₂₂ . Transistor Q ₂₂ and
The collector-emitter current paths of Q ₂₃ are connected in cascade, the collector-emitter of transistor Q ₂₂ is connected to the emitter of transistor Q ₂₁ , and the collector-emitter of transistor Q ₂₃
The emitter of is grounded through resistor _R23 .
Emitter of transistor Q ₂₁ and transistor Q ₂₃
A capacitor C ₂₂ is inserted between the bases of.
Further, the emitter of the transistor _Q23 is provided with an output terminal 24 connected to a subsequent circuit different from the subsequent circuit to which the emitter of the transistor _Q22 is connected. Further, the base of the transistor Q ₂₃ is connected via a resistor R ₂₄ to a terminal 25 to which a base bias voltage E ₃ is applied.

In the above configuration, the output signal of the previous stage circuit is output from the emitter of the transistor Q ₂₁ and transmitted to the transistors Q ₂₂ and Q ₂₃ via the respective capacitors C ₂₁ and C ₂₂ .
supplied to the base of And the transistor
The signals are supplied from the emitters of Q ₂₂ and Q ₂₃ to the corresponding subsequent circuits via output terminals 23 and 24.

The power consumption in the above configuration is the same as the power consumption in the circuit shown in FIG. Therefore, power consumption can be reduced by at least 1/3 compared to the case where a circuit having the same function as that shown in FIG. 3 is configured using the conventional configuration. Also, capacitors C ₂₁ and C ₂₂
The capacitance value for two capacitors C11 is (2Cb) smaller than the capacitance value for two capacitors _C11 , and can greatly contribute to reducing the chip area of semiconductor integrated circuits.

Note that when three or more subsequent circuits are capacitively coupled in parallel to the preceding circuit, the collector-emitter current paths of three or more transistors are similarly connected in cascade, and the cascade-connected collector-emitter current paths are An emitter current path can be inserted between the emitter of transistor Q ₂₁ and ground. And the transistor
A capacitor may be inserted between each emitter of a plurality of transistors in which the emitter of Q ₂₁ and the collector-emitter current path are connected in cascade.

FIG. 4 shows, for example, in the circuit shown in FIG.
This is a circuit diagram configured so that the subsequent circuit connected to the output terminal 23 is also driven with the same drive current as the drive current of the transistors Q ₂₁ and Q ₂₂ . The circuit shown in the latter stage is, for example, a delay circuit, and is a transistor
It is composed of Q ₃₁ , resistors R ₃₁ , R ₃₂ , and capacitor C ₃₁ . In this case, the collector-emitter current path of transistor Q ₃₁ is connected in cascade with the collector-emitter current path of transistor Q ₂₂ , and a base bias voltage is applied from the emitter side of transistor Q ₂₂ via resistor R ₃₁ .

According to the above configuration, the output signal of the previous stage circuit is supplied to the delay circuit via the capacitive coupling circuit including transistors Q ₂₁ , Q ₂₂ , capacitor C ₂₁ and the like. Then, it is delayed by resistor R ₃₁ and capacitor C ₃₁ ,
It is led to the output terminal 31 from the emitter of the transistor _Q31 . In addition, transistor Q ₃₂ and resistor R ₃₃
constitutes a buffer circuit.

By the way, FIG. 5 is a circuit diagram showing a conventional configuration of the circuit shown in FIG. 4. Furthermore, in Figure 5,
Components having the same functions as those in FIGS. 1 and 4 are given the same reference numerals.

Comparing the circuit in Figure 4 and the circuit in Figure 5, we find that
In the circuit shown in the figure, transistors Q ₂₁ , Q ₂₂ , and Q ₃₁ can be driven with a common current, so the sum of the driving currents of transistors Q ₂₁ , Q ₂₂ , and Q ₃₁ is equal to the sum of the driving currents of transistor Q ₁₁ in FIG. , Q ₁₂ , and Q ₃₁ , and the power consumption is also approximately 1/3.

〔Effect of the invention〕

As described above, the present invention provides a capacitive coupling circuit that consumes less power, can contribute to reducing the chip area of a semiconductor integrated circuit when integrated, and is suitable for integrating a circuit. be able to.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional capacitive coupling circuit, Fig. 2 is a circuit diagram showing an embodiment of the capacitive coupling circuit according to the present invention, and Fig. 3 is a circuit diagram showing a second embodiment of the present invention. , FIG. 4 is a circuit diagram showing a third embodiment of the present invention, and FIG. 5 is a circuit diagram in which a circuit having the same function as that in FIG. 4 is constructed using the circuit shown in FIG. 1. . Q ₂₁ , Q ₂₂ , Q ₂₃ ... transistor, C ₂₁ , C ₂₂ ... capacitor, R ₂₁ to R ₂₄ ... resistor.

Claims (1)

[Claims] 1. A first transistor whose base is connected to the output end of a preceding circuit, and whose emitters are connected to respective input ends of corresponding N (N≧1) subsequent circuits. Along with
N second transistors (N≧1) in which collector-emitter current paths are cascade-connected, and the cascade-connected collector-emitter current paths are inserted between the emitter of the first transistor and a reference potential; N (N≧1) capacitors are inserted between the emitter of the first transistor and the bases of the N second transistors, and the N capacitors are connected to the output terminal of the preceding stage circuit and the N capacitors. A capacitive coupling circuit characterized in that the circuit is capacitively coupled to an input terminal of a subsequent circuit.