JPS6329828B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density integrated circuit device, and more particularly to a high-density semiconductor integrated circuit device using a polycrystalline silicon layer.

As is well known, integrated circuit devices have conventionally been constructed by connecting a plurality of circuit elements, each of which is insulated and separated within a semiconductor substrate, through a metal wiring path provided on the surface of the semiconductor substrate. Here, the circuit elements were connected to the metal wiring paths through contact holes, that is, openings provided in the insulating coating covering the surfaces of the circuit elements.

However, with this conventional configuration method, when aiming for high-density and large-scale integration of integrated circuit devices, it is necessary to provide a huge number of minute contact holes, which is extremely difficult to achieve. This required advanced fine pattern processing technology.

An object of the present invention is to provide a new integrated circuit device structure suitable for high-density and large-scale integration.

The feature of the present invention is that an insulator is buried on one surface,
a semiconductor substrate in which a single crystal region is partially exposed between the insulators; a polycrystalline silicon layer that is adhered to the single crystal region and whose surroundings are converted into an oxide to form a shape; and the polycrystalline silicon layer. circuit elements such as resistors and diodes formed within the
selectively provided on the polycrystalline silicon layer,
For example, a circuit element formed in a single crystal region and a circuit element formed in a polycrystalline silicon layer are connected to a polycrystalline silicon layer provided with a high conductivity material layer such as metal silicide. It is in a semiconductor device connected by a part. Here, the planar shape of the circuit element within the polycrystalline silicon layer can be defined by the high conductivity material layer and the oxide. Furthermore, a PN junction in the polycrystalline silicon layer that is not used as a diode can be short-circuited using the high conductivity material.

Accordingly, the present invention eliminates the need for conventional contact holes and significantly reduces the total number of patterns required to form a device.

Further, according to the present invention, since the pattern self-shrinking phenomenon can be applied, a high-density integrated circuit device can be easily obtained without using advanced fine pattern processing technology.

Next, in order to better understand the present invention, examples will be given and explained.

A transistor element 1, resistance elements 2 and 3, and a diode element 4, shown in an electrical equivalent circuit in FIG.
An embodiment in which the present invention is applied to realize a gate circuit configured by connecting 5 and 6 in an integrated circuit structure will be described with reference to FIGS. 2 to 8.
First, referring to FIG. 2, a high impurity concentration channel stock is deposited on a desired region of a silicon P-type single crystal substrate 11 with a specific resistivity of 10 ohm-cm by a selective diffusion method using a well-known silicon oxide film as a mask. A P-type single crystal region 12 for the transistor is provided in a ring shape surrounding the area where the transistor is to be formed, a silicon nitride film 14 is provided on the surface of the area where the transistor is to be formed, and selective oxidation is applied using this as a mask.
A micron-thick silicon oxide film 13 is buried and formed in the element forming portion of the semiconductor substrate 11. At this time, as is well known, the oxidation of silicon also progresses in the lateral direction, so the silicon oxide film 13 is formed by penetrating a certain amount from the lateral direction into the transistor area covered with the silicon nitride film 14. Therefore, the area 15' of the silicon single crystal exposed region obtained by later removing the silicon nitride film 14 is smaller than the area of the original mask pattern. In this embodiment, since the penetration is about 1 micron, if a slit pattern with a width of 4 microns is used, a single crystal exposed area of about 2 microns wide can be obtained. Next, as shown in FIG. 3, an N-type impurity element is implanted over the entire surface of the substrate by ion implantation, and heat treatment is performed to form an N-type single crystal region 15 in a portion where a transistor is to be formed. In the case of this example, in which a silicon nitride film with a thickness of 0.1 microns was used to form a silicon oxide film with a thickness of approximately 2 microns, the implantation energy was
After injecting phosphorus at 200KeV and a dose of 4×10 ¹³ ,
It is preferable to perform the heat treatment in a nitrogen atmosphere at 1150°C for 10 hours. This treatment reduces the layer resistance to approximately 300
An N-type single crystal region of Ω/□ and a depth of about 5 microns is formed. Next, as shown in FIG. 4, the silicon nitride film 14 is removed and the surface 1 of the N-type single crystal region 15 is
After exposing 5', a silicon polycrystalline film 16 with a thickness of 0.5 microns is formed on the entire surface, the surface is thermally oxidized and covered with a silicon oxide film 17 with a thickness of about 0.05 microns, and a photoresist 18 is placed on top of the N-type region. 15 and the silicon polycrystalline film 16 to cover the intended collector surface area and the intended collector lead wiring part of the silicon polycrystalline film 16. Using this photoresist 18 as a mask, a P-type impurity element is implanted into the silicon polycrystalline film 16 by ion implantation. selectively introduced into At this time, boron is implanted with an energy of 100 KeV and a dose of 1×
Injection at 10 ¹⁴ is preferred. Next, after removing the photoresist film 18, a 0.2 micron thick silicon nitride film is formed over the entire surface of the substrate.
The silicon nitride film is selectively etched using photoresist, and the silicon nitride film 19 is left to cover the portion of the silicon polycrystalline film 16 where the connecting body is to be formed, as shown in FIG. 5, and the substrate is thermally oxidized. A connected body consisting of silicon polycrystalline films separated from each other by selectively converting the exposed portions of the silicon polycrystalline film 16 into silicon oxide 20 (including circuit elements, electrodes to the elements, and wiring in this embodiment) form. In this example, it is preferable to perform the heat treatment in an oxygen atmosphere at 1000° C. for 6 hours. At this time, boron that had been selectively implanted into the silicon polycrystalline is activated and the layer resistance value of the silicon polycrystalline film increases to approximately 4KΩ/
At the same time, a P-type semiconductor region 21 with a depth of about 0.4 microns is formed by diffusion of boron in the portion bonded to the N-type single crystal region 15 of the substrate. Furthermore, as described above, due to the pattern area reduction phenomenon that occurs during selective oxidation, the pattern width of the resulting interconnected body made of polycrystalline silicon film is reduced by about 1 micron compared to the original mask pattern width.

Next, as shown in FIG. 6, the silicon nitride film 19 covering the surface of the N-type region portion of the connector (in this example, the portion where the emitter and collector electrode wiring of the transistor and the diode formation portion are planned) is selectively removed. Then, using the remaining silicon nitride film as a mask, a high concentration N-type impurity element is introduced into a desired portion of the connector. In this example, it is preferable to diffuse and introduce phosphorus at 950° C. for 20 minutes by a well-known thermal diffusion method. At this time, phosphorus is introduced into the silicon polycrystalline film in the area intended for N-type, giving it the characteristics of an N-type semiconductor with a layer resistance value of approximately 20Ω/□. Phosphorus is also diffused into the single crystal region at the portions bonded to the respective planned portions of the collector contact, forming high concentration N-type single crystal regions 22 and 23 with a depth of approximately 0.4 microns. Through the above manufacturing process, the N type single crystal region 15 is used as the collector region, the P type single crystal region 21 is used as the base region, and the high concentration N type single crystal region 22 is used as the emitter region.
A link body was formed consisting of an NPN transistor and polycrystalline silicon having P-type or N-type semiconductor properties connected to each region of the transistor. Next, short-circuit unnecessary parts of the PN junction formed in the connector, and connect the parts of the connector that constitute the resistor, the anode and cathode of the diode,
In order to increase the electrical conductivity of the electrode/wiring portions other than the portions constituting the PN junction, the metallization process described below is performed. In other words, as shown in FIG. 7, the desired portion of the insulating coating 19 remaining on the surface of the connecting body, that is, the portion that protects the necessary resistance element and PN junction, is left, and the insulating coating of the other portions is removed to connect. The surface of the body is exposed, a metal thin film is applied over the entire surface of the substrate, heat treatment is performed to form metal silicide 24 on the exposed surface of the connector, and the remaining metal thin film is removed. In this example, a 0.1 micron thick platinum film was deposited and heat treated at 600° C. for 30 minutes in a nitrogen atmosphere to form a platinum silicide layer. After the heat treatment, the remaining platinum is removed by immersing the substrate in aqua regia to form platinum silicide having a layer resistance of about 5 Ω/□ on the exposed portion of the connector. Finally, as shown in FIG. 8, an insulating film 25 is applied to the entire surface of the substrate, and openings reaching the metal silicide are formed in desired areas, and connections are made to the metal silicide within these openings. Insulating film 25
A metal film extending upward is formed to form a desired electrode wiring terminal 1.
01 to 105. At this time, since there are insulators 20 on both sides of the connecting body, the openings may be outside the width of the connecting body or may be wider than the width of the connecting body. Therefore, it is possible to provide a loose alignment margin for the openings. Further, the metal films 101 to 105 may be used as external terminals or as wiring with other circuit elements, or may be replaced with a connecting body using polycrystalline silicon similar to the first layer connecting body. Good too. Through the above manufacturing process, the NPN transistor 1 formed in the single crystal region of the substrate, the resistance elements 2, 3 formed in the polycrystalline silicon thin film region,
and PN junctions (diodes) 4, 5, 6 are connected by a metal silicide layer 24, and electrode terminals 101, 102, 103, 104, 10 are connected by the metal film, respectively.
5 is taken out, and the gate circuit shown in FIG. 1 is completed.

Although the embodiments have been described above, the main part of the present invention is that circuit elements are manufactured in a state in which they are connected to each other using a connecting body made of polycrystalline silicon as a medium, and the effect of the present invention is that By eliminating contact holes for connection and incorporating the self-shrinking effect of the pattern, the area of the circuit element itself can be reduced and high-density integration can be achieved.

Therefore, the technical scope of this invention is not limited to the above embodiments, and the rights of this invention extend to all devices shown in the claims.

[Brief explanation of the drawing]

FIG. 1 is an electrical equivalent circuit diagram to be realized as an integrated circuit structure according to an embodiment of the present invention, and FIGS. 2 to 8 are structures at each step of a method for manufacturing an integrated circuit structure according to an embodiment of the present invention. In the figure showing the second
A in Figure A and Figures 4 to 8 is A in B of each figure.
- A cross-sectional view along line A'; Figure 3 is a cross-sectional view;
Figure B and B in Figures 4 to 8 are plan views. In the figure, 1...transistor, 2, 3...
Resistor, 4, 5, 6... Diode, 11... Semiconductor substrate, 13, 20... Oxide, 16... Polycrystalline silicon layer.

Claims (1)

[Claims] 1. A semiconductor substrate in which an insulator is buried in one surface and a single crystal region is partially exposed between the insulators;
A polycrystalline silicon layer formed in a predetermined shape and adhered to the single crystal region, a circuit element formed in the polycrystalline silicon layer, and a high conductivity material selectively provided on the polycrystalline silicon layer. having a layer;
The high conductivity material layer defining one end of the element region of a circuit element formed in the polycrystalline silicon remains in the polycrystalline silicon up to the point where the polycrystalline silicon layer is connected to the circuit element in the single crystal region. A semiconductor device characterized by extending over a layer. 2. The element region of the circuit element formed in the polycrystalline silicon layer is defined by the polycrystalline silicon oxide and the high conductivity material layer. The semiconductor device described in . 3. The circuit element in the polycrystalline silicon layer includes a diode, and the diode has a region of one conductivity type and a region of opposite conductivity provided in the polycrystalline silicon layer as an anode region and a cathode region, respectively, and both of these regions are 3. A semiconductor device according to claim 2, wherein the semiconductor device is defined by an oxide and the layer of high conductivity material. 4. The circuit element within the polycrystalline silicon layer includes a resistor, the width of which is defined by the oxide, and at least one length of which is defined by the layer of high conductivity material. A semiconductor device according to claim 2, characterized in that: 5. A plurality of circuit elements are present in the polycrystalline silicon layer, and predetermined circuit elements are connected by the high conductivity material layer. A semiconductor device according to claim 1. 6. A P-N junction is formed in the circuit element non-forming region of the polycrystalline silicon layer, and this P-N junction is short-circuited by a high conductivity material layer on the polycrystalline silicon layer. A semiconductor device according to any one of claims 1 to 5. 7. The semiconductor device according to any one of claims 1 to 6, wherein the high conductivity material layer includes a metal silicide layer.