JPH0413862B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density integrated circuit device having bipolar transistors, and more particularly to a high-density bipolar transistor type semiconductor integrated circuit device using a polycrystalline silicon layer.

Conventionally, an integrated circuit device has been constructed by connecting a plurality of circuit elements, each of which is insulated and separated within a semiconductor substrate, with a metal wiring path provided on the surface of the semiconductor substrate. Here, the connection of the circuit element to the metal wiring path was made through a contact hole, that is, an opening provided in an insulating film covering the surface of the circuit element.

However, with this conventional configuration method, when aiming for high-density and large-scale integration of integrated circuit devices, it is necessary to provide a huge number of minute contact holes, which is extremely difficult to achieve. This required advanced fine pattern processing technology.

An object of the present invention is to provide a new bipolar transistor type integrated circuit device structure suitable for high-density and large-scale integration.

A feature of the present invention is that one principal surface of the semiconductor substrate is exposed in a planar rectangular shape extending in one direction;
Its periphery is surrounded by an insulating film buried in the semiconductor substrate, a collector region of one conductivity type of the bipolar transistor is surrounded by the insulating film on its entire periphery, and a base region of the opposite conductivity type of the transistor is provided. is provided inside the collector region with three sides in contact with the insulating film and the remaining one side is exposed on the one main surface, and an emitter region of one conductivity type of the transistor is provided in the first and second A polycrystalline polycrystalline material of one conductivity type, which is provided in the base region in such a manner that its sides are in contact with the portion of the insulating film that is in contact with the long sides of the rectangle, and the remaining third and fourth sides are exposed on the one main surface. A silicon conductor is connected between the first and second sides of the emitter region and extends over the insulating film in a direction perpendicular to the one direction, and a plurality of bipolar transistors in this configuration are arranged to form a semiconductor. The semiconductor integrated circuit device is provided on a substrate, and the emitter regions of each bipolar transistor are commonly connected by the polycrystalline silicon conductor.

Next, in order to better understand the present invention, examples will be given and explained.

First, techniques related to the present invention will be explained with reference to FIGS. 1 to 8.

A transistor element 1, resistance elements 2 and 3, and a diode element 4, shown in an electrical equivalent circuit in FIG.
Examples of techniques related to the present invention for realizing a gate circuit configured by connecting 5 and 6 in an integrated circuit structure will be described with reference to FIGS. 2 to 8. First, referring to FIG. 2, a high impurity concentration channel stock is deposited on a desired region of a silicon P-type single crystal substrate 11 with a specific resistivity of 10 ohm-cm by a selective diffusion method using a well-known silicon oxide film as a mask. A P-type single crystal region 12 for transistors is provided in an annular shape surrounding the area where the transistor is to be formed, and a silicon nitride film 14 is provided on the surface of the area where the transistor is to be formed, and using this as a mask, selective oxidation is applied to a thickness of approximately 2 microns. silicon oxide film 13 on the semiconductor substrate 11
It is formed by embedding it in the non-element forming part. At this time, as is well known, the oxidation of silicon also progresses in the lateral direction, so the silicon oxide film 13 is formed by penetrating a certain amount from the lateral direction into the transistor area covered with the silicon nitride film 14. Therefore, the area 15' of the silicon single crystal exposed region obtained by later removing the silicon nitride film 14 is smaller than the area of the original mask pattern. In this example, the penetration is about 1 micron, so if a 4 micron wide slit pattern is used, an exposed area of the single crystal about 2 microns wide will be obtained. Next, as shown in FIG. 3, an N-type impurity element is implanted over the entire surface of the substrate by ion implantation, and heat treatment is performed to form an N-type single crystal region 15 in a portion where a transistor is to be formed. In this example, a 0.1 micron thick silicon nitride film was used to form an approximately 2 micron thick silicon oxide film. After phosphorus was implanted at an implantation energy of 200 KeV and a dose of 4 x 10 ¹³ , it was implanted in a nitrogen atmosphere at 1150°C. It is preferable to carry out the heat treatment for 10 hours. This process forms an N-type single crystal region with a layer resistance of about 300 Ω/□ and a depth of about 5 microns.
Next, as shown in FIG. 4, after removing the silicon nitride film 14 to expose the surface 15' of the N-type single crystal region 15, the silicon polycrystalline film 1 with a thickness of 0.5 microns is removed.
6 is formed on the entire surface, and the surface is thermally oxidized to approximately 0.05
It is covered with a micron silicon oxide film 17, and a photoresist 18 is selectively provided thereon so as to cover the portion of the N-type region 15 where the collector surface region is planned and the portion of the silicon polycrystalline film 16 where the collector lead wiring is planned. A silicon polycrystalline film 16 is formed by ion implantation using a P-type impurity element as a mask.
selectively introduced within. In this case, it is preferable to implant boron at an implant energy of 100 KeV and a dose of 1×10 ¹⁴ . Next, after removing the photoresist film 18, a 0.2 micron thick silicon nitride film is formed over the entire surface of the substrate. The silicon nitride film is selectively etched using photoresist, and the silicon polycrystalline film 1 is etched as shown in FIG.
The silicon nitride film 19 is left so as to cover the portion where the connecting body 6 is to be formed, and the substrate is subjected to thermal oxidation treatment to selectively convert the silicon oxide 20 into the exposed portion of the silicon polycrystalline film 16 to separate them from each other. A connected body (including circuit elements, electrodes to the elements, and wiring in this example) is formed from the silicon polycrystalline film. In this example, it is preferable to perform the heat treatment in an oxygen atmosphere at 1000°C for 6 hours. At this time, the boron that had been selectively implanted into the silicon polycrystal is activated, giving the silicon polycrystalline film the electrical characteristics of a P-type semiconductor with a layer resistance value of about 4KΩ/□, and at the same time In the part bonded to the single crystal region 15, due to the diffusion of boron, approximately
A 0.4 micron deep P-type semiconductor region 21 is formed. Furthermore, as described above, due to the pattern area reduction phenomenon that occurs during selective oxidation, the pattern width of the resulting interconnected body made of a silicon polycrystalline film is reduced by about 1 micron compared to the original mask pattern width.

Next, as shown in FIG. 6, the silicon nitride film 19 covering the surface of the N-type region of the connector (in this example, the transistor's emitter and collector electrode wiring and the diode formation portion) is selectively removed. Then, using the remaining silicon nitride film as a mask, a high concentration of N-type impurity element is introduced into a desired portion of the connector. In this example, it is preferable to introduce phosphorus by diffusion at 950° C. for 20 minutes using the well-known thermal diffusion method.
At this time, phosphorus is introduced into the silicon polycrystalline film in the area intended for N-type, giving it the characteristics of an N-type semiconductor with a layer resistance value of approximately 20Ω/□. Phosphorus is also diffused into the single crystal region at the portions bonded to the respective planned portions of the collector contact, forming high concentration N-type single crystal regions 22 and 23 with a depth of approximately 0.4 microns. Through the above manufacturing process, the N-type single crystal region 15 is a collector region, the P-type single crystal region 21 is a base region, and a high concentration N
A connected body consisting of an NPN transistor having the shaped single crystal region 22 as an emitter region and polycrystalline silicon having P-type or N-type semiconductor characteristics connected to each region of the transistor was formed. Next, short-circuit unnecessary parts of the PN junction formed in the connector, and then short-circuit the parts that constitute the resistor in the connector, the anode and cathode of the diode, and the electrodes and wiring parts other than the parts that constitute the PN junction. In order to increase the electrical conductivity of the material, the metallization process described below is performed. In other words, as shown in FIG. 7, the desired portion of the insulating coating 19 remaining on the surface of the connecting body, that is, the portion that protects the necessary resistance element and PN junction, is left, and the insulating coating of the other portions is removed to connect. The surface of the body is exposed, a metal thin film is applied over the entire surface of the substrate, heat treatment is performed to form metal silicide 24 on the exposed surface of the connector, and the remaining metal thin film is removed. In this example, a 0.1 micron thick platinum film was deposited and heated at 600℃ in a nitrogen atmosphere.
Heat treatment was performed for 30 minutes to form a platinum silicide layer. After heat treatment, the board is immersed in aqua regia to remove the remaining platinum, and the exposed part of the connector has a layer resistance of approximately 5Ω/
□ Platinum silicide is formed. Finally, the 8th
As shown in the figure, an insulating film 25 is deposited on the entire surface of the substrate, and openings reaching the metal silicide are provided at desired portions. A stretchable metal film is formed to form desired electrode wiring terminals 101 to 105. At this time, since there are insulators 20 on both sides of the connecting body, the openings may be outside the width of the connecting body or may be wider than the width of the connecting body. Therefore, it is possible to provide a loose alignment margin for the openings. Further, the metal films 101 to 105 may be used as external terminals or as wiring with other circuit elements, or may be replaced with a connecting body using polycrystalline silicon similar to the first layer connecting body. Good too. Through the above manufacturing process, a
The NPN transistor 1, the resistance elements 2 and 3 formed in the region of the polycrystalline silicon thin film, and the PN junctions (diodes) 4, 5, and 6 form the metal silicide layer 2.
4, each connected to an electrode terminal 10 by a metal film.
1, 102, 103, 104, and 105 are extracted to complete the gate circuit shown in FIG.

Next, an embodiment of the present invention will be described with reference to FIGS. 9 to 11.

This embodiment realizes a CML gate circuit with an emitter follower as shown in FIG. 9 in a high-density integrated circuit structure, and transistors 1a to 1 in FIG.
1f and the transistors 1a to 1f in the circuit consisting of resistors R ₁ to R ₃ and the resistors taken out for illustration.
The portion 200 including R ₁ and R ₂ will be explained with reference to FIGS. 10 and 11. Resistors R ₁ to R ₅ including R ₁ and R ₂ and wiring terminals 201 to 208 (power terminals 201, 202, input terminals 203 to 205,
reference voltage terminal 206, output terminals 207, 208)
The resistors R ₁ and R ₂ , which are included as examples, are omitted from Figures 10 and 11 because they can be placed as appropriate in consideration of connections with other circuits. .

The plan view of FIG. 10 and the cross-sectional view of FIG. 11 showing the integrated circuit structure are the plan view of FIG. 7B and the cross-sectional view of FIG.
The first stage corresponds to the stage of the cross-sectional view of
Portions that are functionally equivalent to those in FIGS. 1-8 are designated by the same reference numerals as in FIGS. 1-8. The device of this embodiment is manufactured in the same manner as shown in FIGS.
The portions where R ₁ and R ₂ are to be formed are covered with a silicon nitride film, and the substrate surface is selectively oxidized to form an oxide film 13 embedded in the surface surrounding the portions where each circuit element is to be formed. Although it is preferable to previously provide a P ⁺ type channel stopper region 12 on the substrate surface surrounding the portion where each circuit element is to be formed, it may be omitted in some cases. Next, N-type impurities are ion-implanted to form an N-type region 1 in the area where the element is to be formed.
form 5. To form the N-type region 15, a thermal diffusion method may be used instead of ion implantation, or an oxide that reaches the substrate may be provided in advance on a P-type substrate having an N-type epitaxial layer by selective oxidation. Therefore, an N-type region 15 may be formed in the portion where the element is planned. Next, the single crystal region (in this case, the surface of the N-type region 15) in the portion where the element is to be formed is exposed, and polycrystalline silicon is applied over the entire substrate surface, that is, covering all the exposed single crystal regions and the surface of the insulator 13. layer 1
6 is provided, and a predetermined portion thereof is doped with a P-type impurity. This doped portion is connected to transistors 1a to 1.
The polycrystalline silicon portion is at least in contact with the planned base portion of f and the planned resistor region portions of resistors R ₁ and R ₂ , but the portion in contact with the latter is partially doped (into a portion that will later be converted into oxide). It is desirable to reduce the amount. Of course, it is also possible to dope parts that will not interfere with later processes. Next, the polycrystalline silicon layer 16 is thermally oxidized except for the portions that are to become the connecting bodies constituting the electrode wiring of each circuit element to form oxides 20 and 20', and P-type impurities are removed from the polycrystalline layer to form N-type impurities. The single crystal region 15 is doped to form a P-type region 22 which becomes a base in a portion where a transistor is to be formed and a resistance region in a resistor portion. A portion of the P-type impurity-doped polycrystalline silicon in contact with these regions is also converted into oxide 20'.
Next, by masking a predetermined portion of the remaining polycrystalline silicon layer and exposing the other portion, N-type impurities are introduced into the polycrystalline silicon layer and the single crystal region in contact with it.
What is exposed here are the polycrystalline silicon portions in contact with the intended emitter portions and the intended collector contact portions of transistors 1a to 1f. As a result, an N type emitter region 22 is formed in the base region 21 of each transistor, and an N ^{+ type} emitter region 22 is formed in the surface region of the collector 15.
A mold collector contact region 23 is formed respectively. Then, the unnecessary
A layer 24 of a highly conductive material such as metal silicide is provided on the surface of the polycrystalline silicon layer in order to neglect the PN junctions 31, 32, 33 and obtain an ohmic connection between the devices. This layer 24 may be provided only in the vicinity of unnecessary PN junctions, or may not be provided in connected bodies without unnecessary PN junctions, but in order to reduce signal loss in the connected body, it is necessary to It is preferable to provide the entire necessary portion. Figures 10 and 11 show the structure at this stage, but if necessary, a protective film may be provided on this surface, or an insulating film with openings may be placed on the surface as shown in Figures 1 to 8. Alternatively, a second wiring layer may be provided.

In the structure shown in FIGS. 10 and 11 formed in this way, four transistors 1a to 1d whose emitters are commonly connected are arranged in parallel, and a polycrystalline silicon connection body serving as a common emitter wiring is connected to each transistor. intersects the exposed surface area of the transistor,
An emitter 22 is formed at the intersection of each exposed surface area (see also FIG. 11A). Further, emitter follower transistors 1e and 1f are arranged in parallel with these transistors 1a to 1d, respectively, and a connected body serving as a common collector output terminal of gate transistors 1a to 1c is connected to each exposed surface area of the gate transistors and to the output transistor 1e. The N-type collector contact region 23 extends across the exposed surface region of the gate transistor and extends across the exposed surface region of the gate transistor.
A P-type base region 21 is formed in the surface exposed region of the output transistor 1e, and the resulting unnecessary PN junction 32 is shot to enable ohmic connection of the common collector output to the output transistor base. The same applies to the connection between the collector of the reference transistor 1d and the base of the output transistor 1f. (No. 11 above)
(see Figure B). As a result, each transistor 1a~
The dimensions of 1f and the spacing are extremely reduced, allowing the realization of high-density integrated circuit structures. In addition, the first
In FIG. 0, the connections of each part including the connections of input terminals 203 to 205 are made as shown in FIG.

In this example, the resistors included as an example
The width of R ₃ is defined by the buried oxide film 13, the length is defined by the selective oxide film 20' (conversely speaking, the polycrystalline silicon connections at both ends), and the depth is defined by the P into the N-type region 15. It is a semiconductor single crystal resistor defined by the doping depth of the type impurity, and the resistance _R2 has the width and depth defined by the width and depth of the P-type impurity doped into the N-type region 15, and the length. Although the resistors R ₁ to R ₃ in FIG. 9 are defined by the polycrystalline silicon connectors at both ends, the resistors R 1 to R 3 in FIG. It may be realized by a structure similar to.

Although the embodiments have been described above, the main part of the present invention is that circuit elements are connected to each other using a connecting body made of polycrystalline silicon as a medium, and the effects of the present invention are as follows. contact·
By eliminating holes and incorporating the self-shrinking effect of the pattern, the area of the circuit element itself can be reduced and high-density integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is an electrical equivalent circuit diagram of a circuit to be realized by the technology related to the present invention, FIGS. 2 to 8 are diagrams showing the structure at each step of the manufacturing method according to this technology of the present invention, and The figure is a sectional view, B in Fig. 2B and Figs. 4 to 8 is a plan view, and A in Fig. 2A and Figs. It is a sectional view of the ivy. FIG. 9 is an equivalent circuit diagram of an integrated circuit realized by an embodiment of the present invention, FIG. 10 is a partial plan view of an integrated circuit device according to an embodiment of the present invention,
11A is a sectional view taken along line A-A' in FIG. 10, FIG. 11B is a sectional view taken along line BB' in FIG. 10, and FIG. 11C is a sectional view taken along line A-A' in FIG. FIG. Main symbols in the figure 1, 1a to 1f...Transistor, 2, 3, _R1 to _R3 ...Resistor, 4 to 6...Diode, 11...P type semiconductor substrate, 12...P ⁺ type channel stopper region, 13 ...Buried oxide film, 15...
N-type region, 16... polycrystalline silicon layer, 20... selective oxide film, 20'... selective oxide film after P-type doping, 2
1... P type region, 22... N type emitter region, 23...
N ⁺ type collector contact region, 24...metal silicide layer.

Claims (1)

[Claims] 1 One principal surface of a semiconductor substrate is exposed in a planar shape as a rectangle extending in one direction, and is surrounded by an insulating film buried in the semiconductor substrate, with a collector region of one conductivity type covering the entire circumference. A base region of opposite conductivity type is provided surrounded by the insulating film, and is provided inside the collector region with three sides thereof in contact with the insulating film and one remaining side exposed to the one main surface. A conductive type emitter region is arranged in such a manner that its first and second sides are in contact with a portion of the insulating film that is in contact with the long side of the rectangle, and the remaining third and fourth sides are exposed on the one main surface. A plurality of bipolar transistors provided in the base region are provided in parallel so that the long sides of the exposed rectangle are parallel to each other,
A semiconductor integrated circuit characterized in that emitter regions of each bipolar transistor are commonly connected by a polycrystalline silicon conductor extending linearly in a direction perpendicular to the one direction.