JPH0121625B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density integrated circuit device, and more particularly to a high-density semiconductor integrated circuit device using a polycrystalline silicon layer.

Conventionally, an integrated circuit device has been constructed by connecting a plurality of circuit elements, each of which is insulated and separated within a semiconductor substrate, with a metal wiring path provided on the surface of the semiconductor substrate. Here, the connection of the circuit element to the metal wiring path was made through a contact hole, that is, an opening provided in an insulating film covering the surface of the circuit element.

However, with this conventional configuration method, when aiming for high-density and large-scale integration of integrated circuit devices, it is necessary to provide a huge number of minute contact holes, which is extremely difficult to achieve. This required advanced fine pattern processing technology. Further, a preferred circuit configuration could not be obtained in the semiconductor layer on the semiconductor substrate.

An object of the present invention is to provide a new integrated circuit device structure that eliminates the above-mentioned drawbacks and is suitable for high-density and large-scale integration.

The present invention is characterized by a polycrystalline silicon pattern bonded to one principal surface of a semiconductor substrate partially exposing a single crystal region and extending over an insulating film provided on the semiconductor substrate; a low resistance thin film selectively provided on the upper surface of the pattern, a PN junction diode element and a resistance element are formed in the polycrystalline silicon pattern, and an element region where these elements are formed is formed by the low resistance thin film. It is located in a partitioned semiconductor integrated circuit device. Here, the low resistance thin film is formed continuously from a portion of the polycrystalline silicon pattern connected to the semiconductor substrate to one end of the diode element formation region, and from the other end of the diode element formation region to one end of the resistance element formation region. It is preferable to form the layer continuously up to one end from the viewpoint of lowering the resistance as a wiring layer and reliably dividing the element region. Further, the PN junction not used as a diode is short-circuited by a low resistance thin film.

Next, in order to better understand the present invention, examples will be given and explained.

First, embodiments of the present invention will be described with reference to FIGS. 1 to 8.

A transistor element 1, resistance elements 2 and 3, and a diode element 4, shown in an electrical equivalent circuit in FIG.
An embodiment in which the present invention is applied to realize a gate circuit configured by connecting 5 and 6 in an integrated circuit structure will be described with reference to FIGS. 2 to 8.
First, referring to FIG. 2, a channel stock with a high impurity concentration is deposited on a desired region of a silicon P-type single crystal substrate 11 having a specific resistivity of 10 ohm-cm by a selective diffusion method using a well-known silicon oxide film as a mask. A P-type single crystal region 12 for the transistor is provided in a ring shape surrounding the area where the transistor is to be formed, a silicon nitride film 14 is provided on the surface of the area where the transistor is to be formed, and selective oxidation is applied using this as a mask.
A micron-thick silicon oxide film 13 is formed by embedding it in a portion of the semiconductor substrate 11 where no element is formed. At this time, as is well known, the oxidation of silicon also progresses in the lateral direction, so that the silicon oxide film 13 is formed by penetrating a certain amount from the lateral direction into the transistor area covered with the silicon nitride film 14. Therefore, the area 15' of the silicon single crystal exposed region obtained by later removing the silicon nitride film 14 is smaller than the area of the original mask pattern. In this embodiment, the penetration is about 1 micron, so if a slit pattern with a width of 4 microns is used, a single crystal exposed area of about 2 microns wide can be obtained. Next, as shown in FIG. 3, an N-type impurity element is implanted over the entire surface of the substrate by ion implantation, and heat treatment is performed to form an N-type single crystal region 15 in the area where the transistor is to be formed.
form. In this example, in which a 0.1 micron thick silicon nitride film was used to form a silicon oxide film approximately 2 microns thick, the implantation energy was
After injecting phosphorus at 200KeV and a dose of 4×10 ¹³ ,
It is preferable to perform the heat treatment in a nitrogen atmosphere at 1150°C for 10 hours. This treatment reduces the layer resistance to approximately 300
An N-type single crystal region of Ω/□ and a depth of approximately 5 microns is formed. Next, as shown in FIG. 4, the silicon nitride film 14 is removed and the surface 1 of the N-type single crystal region 15 is
After exposing 5', a silicon polycrystalline film 16 with a thickness of 0.5 microns is formed on the entire surface, the surface is thermally oxidized and covered with a silicon oxide film 17 with a thickness of about 0.05 microns, and a photoresist 18 is placed on top of the N-type region. The photoresist 18 is selectively provided so as to cover the intended collector surface region of the silicon polycrystalline film 15 and the intended collector lead wiring part of the silicon polycrystalline film 16. Using this photoresist 18 as a mask, a P-type impurity element is implanted into the silicon polycrystalline film 16 by ion implantation. selectively introduced into At this time, boron is implanted with an energy of 100 KeV and a toes amount of 1×
Injection at 10 ¹⁴ is preferred. Next, after removing the photoresist film 18, a 0.2 micron thick silicon nitride film is formed over the entire surface of the substrate.
The silicon nitride film is selectively etched using photoresist, and the silicon nitride film 19 is left to cover the portion of the silicon polycrystalline film 16 where the connecting body is to be formed, as shown in FIG. 5, and the substrate is thermally oxidized. The exposed portion of the silicon polycrystalline film 16 is selectively converted into silicon oxide 20 to form a connected body (including circuit elements, electrodes to the elements, and wiring in this embodiment) made of the separated silicon polycrystalline films. do.
In this example, it is preferable to perform the heat treatment in an oxygen atmosphere at 1000° C. for 6 hours. At this time, the boron that had been selectively implanted into the silicon polycrystal is activated and gives the silicon polycrystalline film the electrical characteristics of a P-type semiconductor with a layer resistance value of approximately 4KΩ/□.
In the part bonded to the P-type single crystal region 15, a P-type semiconductor region 21 with a depth of approximately 0.4 microns is formed due to boron diffusion.
is formed. Furthermore, as described above, due to the pattern area reduction phenomenon that occurs during selective oxidation, the pattern width of the resulting interconnected body made of polycrystalline silicon film is reduced by about 1 micron compared to the original mask pattern width.

Next, as shown in FIG. 6, the silicon nitride film 19 covering the surface of the N-type region portion of the connector (in this example, the portion where the emitter and collector electrode wiring of the transistor and the diode formation portion are planned) is selectively removed. Then, using the remaining silicon nitride film as a mask, a high concentration N-type impurity element is introduced into a desired portion of the connector. In this example, it is preferable to diffuse and introduce phosphorus at 950° C. for 20 minutes by a well-known thermal diffusion method. At this time, phosphorus is introduced into the silicon polycrystalline film in the N-type portion to give it the characteristics of an N-type semiconductor with a layer resistance value of 20Ω/□, and at the same time, this N-type portion becomes the emitter of the single crystal region of the substrate Phosphorus is also diffused into the single crystal region in the areas bonded to each planned collector contact area, resulting in a high concentration of N at a depth of approximately 0.4 microns.
Single crystal regions 22 and 23 are formed. Through the above manufacturing process, an NPN in which the N-type single crystal region 15 is the collector region, the P-type single crystal region 21 is the base region, and the high concentration N-type single crystal region 22 is the emitter region.
A link body consisting of a transistor and polycrystalline silicon having P-type or N-type semiconductor properties connected to each region of the transistor was formed. Next, short-circuit unnecessary parts of the PN junction formed in the connector, and then short-circuit the parts that constitute the resistor in the connector, the anode and cathode of the diode, and the electrodes and wiring parts other than the parts that constitute the PN junction. In order to increase the electrical conductivity of the material, the metallization process described below is performed. In other words, as shown in FIG. 7, the desired portion of the insulating coating 19 remaining on the surface of the connecting body, that is, the portion that protects the necessary resistance element and PN junction, is left, and the insulating coating of the other portions is removed to connect. The surface of the body is exposed, a metal thin film is applied over the entire surface of the substrate, heat treatment is performed to form metal silicide 24 on the exposed surface of the connector, and the remaining metal thin film is removed. In this example, a 0.1 micron thick platinum film was deposited and
A platinum silicide layer was formed by heat treatment at ℃ for 30 minutes. After heat treatment, the board is immersed in aqua regia to remove the remaining platinum, and the exposed part of the connector has a layer resistance of about 5.
Platinum silicide of Ω/□ is formed. lastly,
As shown in Figure 8, an insulating coating 2 is applied to the entire surface of the substrate.
After forming openings reaching the metal silicide at desired portions, a metal film extending over the insulating film 25 is formed by connecting to the metal silicide within these openings to form a desired electrode wiring terminal 101. ~105
shall be. At this time, since there are insulators 20 on both sides of the connecting body, the openings may be outside the width of the connecting body or may be wider than the width of the connecting body. Therefore, it is possible to provide a loose alignment margin for the openings.
Further, the metal films 101 to 105 may be used as external terminals or as wiring with other circuit elements, or may be replaced with a connecting body using polycrystalline silicon similar to the first layer connecting body. Good too. Through the above manufacturing process, the NPN transistor 1 formed in the single crystal region of the substrate, the resistance elements 2 and 3 formed in the polycrystalline silicon thin film region, and the PN junctions (diodes) 4, 5, and 6 are connected to the metal silicide layer. 2
4, each connected to an electrode terminal 10 by a metal film.
1, 102, 103, 104, and 105 are extracted to complete the gate circuit shown in FIG.

Although the embodiments have been described above, the present invention connects circuit elements to each other using a connecting body made of polycrystalline silicon as a medium, and the effect of the present invention is that the conventional contact hole for connecting circuit elements By eliminating this and incorporating the self-shrinking effect of the pattern, the area of the circuit element itself can be reduced and high-density integration can be achieved.

[Brief explanation of drawings]

FIG. 1 is an electrical equivalent circuit diagram of a circuit to be realized in an embodiment of the present invention, FIGS. 2 to 8 are diagrams showing the structure at each step of the manufacturing method according to an embodiment of the present invention, and FIG. B in FIG. 2B and FIGS. 4 to 8 is a plan view, and A in FIG. It is a diagram. Main symbols in the diagram 1...transistor, 2, 3...
Resistor, 4 to 6... Diode, 11... P type semiconductor substrate, 12... P ⁺ type channel stopper region, 13
... Buried oxide film, 15... N type region, 16... Polycrystalline silicon layer, 20... Selective oxide film, 21... P type region, 22... N type emitter region, 23... N ⁺ type collector contact region, 24... Metal silicide layer.

Claims (1)

[Claims] 1. A polycrystalline silicon pattern bonded to one main surface of a semiconductor substrate partially exposing a single crystal region and extending over an insulating film provided on the semiconductor substrate; The polycrystalline silicon pattern has an oxide film formed by selective oxidation of polycrystalline silicon to be deposited, and a low-resistance thin film selectively provided on the upper surface of the polycrystalline silicon pattern, and the polycrystalline silicon pattern is partitioned in the width direction by the oxide film. A PN junction diode element and a resistance element are formed that are partitioned in the length direction by the low resistance thin film, and the low resistance thin film extends from above the portion of the polycrystalline silicon pattern connected to the semiconductor substrate to above one end of the diode element formation region. connection of the polycrystalline silicon pattern formed continuously from above the other end of the diode element formation region to above one end of the resistance element formation region, and comprising the low resistance thin film; A semiconductor integrated circuit device characterized in that a metal terminal electrode having a width wider than the width of the connecting portion extends over the oxide film and is connected to the polycrystalline silicon pattern over the entire width of the connecting portion. .