JPS6333303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an inverted insulated gate field effect transistor and a method of manufacturing the same.

The general structure of an inverted insulated gate field effect transistor (hereinafter referred to as an inverted MOSFET) is, for example, as shown in the cross-sectional view of the device in FIG. and a drain region 3, a source electrode 4 and a drain electrode 5 are provided in both regions, and a gate electrode 7 is formed between the source and drain regions with an insulating film 6 interposed therebetween, and a voltage is applied to the gate electrode 7. By applying , the conductivity type of the gate region 8 is inverted, and the current flowing therein is controlled by the gate voltage. Inverted MOSFETs with such a structure are currently widely put into practical use using Si.

However, when GaAs is used as the semiconductor material, there are problems in that the above structure is difficult to manufacture or it is difficult to obtain an inverted MOSFET with excellent characteristics. That is, diffusion technology or ion implantation technology is generally used to form the source region 2 and drain region 3, but in the case of GaAs, such diffusion technology has not been established due to the lack of suitable n-type impurities. In addition, the ion implantation method requires high-temperature heat treatment after implantation.
There was a problem in that the interface state between GaAs and the insulating film was susceptible to thermal deterioration.

Therefore ^, in the case of GaAs, for example, as shown in the cross ^- sectional view of the device in FIG. A structure in which the n ⁺ type semiconductor layer 11 is etched away until it reaches the p ^- type semiconductor layer 10, a gate electrode 13 is formed there through an insulating film 12, and a source electrode 14 and a drain electrode 15 are formed on both sides of the gate electrode 13. inverted type of
MOSFET is proposed. According to this structure, the disadvantages caused by using diffusion regions or ion-implanted regions as the source and drain regions can be eliminated, but microfabrication is difficult due to the formation of steps on the surface, and the insulating film formation method is Depending on the type of MOSFET, the disadvantage is that it is difficult to manufacture a good MOSFET due to the step difference. for example,
Methods that allow the formation of an insulating film with good interfacial properties for GaAs include a method in which vacuum-deposited Al is anodized until the oxidation of Al is completed (hereinafter referred to as the Al anodization method), and a method using a spinner. In Ga
A method is known in which an alcoholic solution of SiO 2 containing SiO ₂ is applied and then heat treated (hereinafter referred to as the spinner method). This makes it difficult to anodize only Al over the entire gate region. Therefore, partially
There was a problem in that there were regions where even GaAs was anodized, making it difficult to obtain good interface properties. Further, the spinner method has a problem in that it is difficult to form an insulating film with a uniform thickness due to surface steps.

The present invention improves these conventional drawbacks, and its purpose is to use highly impurity-containing epitaxially grown semiconductor layers as the source and drain regions and to flatten the device surface.
The object of the present invention is to enable the formation of an insulating film having a good interface with the active layer and to facilitate high-precision processing. Examples will be described in detail below.

FIG. 3 is an element cross-sectional view showing an example of an inverted MOS FET manufactured by the manufacturing method of the present invention, in which 16 is a semi-insulating GaAs substrate, 17 is a p ^- type
GaAs epitaxial layer, 18 is n ⁺ type GaAs epitaxial layer, 19 is an insulating film, 20 is a source electrode, 21 is a drain electrode, 22 is a gate electrode, 2
3 is a striped protrusion.

The inverted MOSFET shown in FIG. 3 consists of a semi-insulating GaAs substrate 16 in which a striped protrusion 23 with a trapezoidal cross-section is provided approximately in the center of the element, and a striped protrusion 23 on the striped protrusion 16. The p ^- type GaAs epitaxial layer 17 formed on
A flat layer was formed on a semi-insulating GaAs substrate 16 to cover both sides of the p ^-type GaAs epitaxial layer.
n ⁺ type GaAs epitaxial layer 18 and the p ^- type
A gate electrode 22 is formed on the GaAs epitaxial layer 17 with an insulating film 19 in between, and a source electrode 20 is formed on the n ⁺ type GaAs epitaxial layer 18 on opposite sides of the gate electrode 22.
and a drain electrode 21. semi-insulating
The p ^- type GaAs epitaxial layer 17 formed on the striped protrusion 23 of the GaAs substrate 16 becomes an active layer, and the n ⁺ type GaAs epitaxial layer 18 becomes a source region and a drain region.

As described above, since the source region and the drain region are epitaxially grown semiconductor layers containing high concentration impurities, a heat treatment step is not required in the manufacturing process, so that the surface of the p ^- type GaAs epitaxial layer 17 is not subject to thermal deterioration. will all disappear. Furthermore, since the element surface is flat, the aforementioned Al anodic oxidation method or spinner method can be employed when forming the gate insulating film, making it possible to form an insulating film with good interfacial properties. Furthermore, since the element surface is flat, highly fine processing can be easily performed.

4A to 4F are manufacturing process diagrams for explaining an example of a method for manufacturing an inversion type MOSFET according to the present invention. For example, a p ^- type film with a thickness of 2 to 3 μm and a carrier density of 1×10 ¹⁶ cm ⁻³ is disposed on the substrate 16.
A GaAs epitaxial layer 17 is grown (FIG. 4A), followed by an anisotropic etchant such as NH ₄ OH:
Using a mixture of H ₂ O ² :H ₂ O=3:1;50, p ^- type
The GaAs epitaxial layer 17 and the substrate 16 are etched to a depth of, for example, 4 μm to form striped protrusions 23 having a trapezoidal cross section and an operating layer thereon (FIG. 4B).

Next, the n ⁺ type is grown by liquid phase epitaxial growth method.
The GaAs epitaxial layer 18 is heated to a thickness of, for example, 5 mm until the p ^- type GaAs epitaxial layer 17 is completely buried.
It is grown to a thickness of ~6 μm and a carrier density of 1×10 ¹⁹ cm ⁻³ . At this time, as shown in Figure 4C, n ⁺
Although the type GaAs epitaxial layer 18 is grown on a trapezoidal structure, its surface is flat.

Next, the n ⁺ type GaAs epitaxial layer 18 and the p ^- type GaAs epitaxial layer 17 are layered until the thickness of the p ^- type GaAs epitaxial layer 17 and its exposed length L (corresponding to the gate length) reach the desired length. is etched (FIG. 4D), and an insulating film 19 is formed over the entire surface (FIG. 4E). As an insulating film formation method,
For example, the two methods mentioned above are employed. In this case, when using the Al anodic oxidation method, for example, Al is vacuum-deposited to a thickness of about 800 Å on the element surface, and then this is finished using a mixture of tartaric acid, ethylene glycol, and water until the Al is easily oxidized. For example, anodize at a current _density of 0.5 mA/cm ² until
Heat treatment is performed in an atmosphere at, for example, 400° C. for 30 minutes. In addition, when using the spinner method, for example, 5 g of SiO ₂ in 100 c.c. of alcohol,
After applying a GaCl ₃ -containing SiO ₂ alcohol solution prepared by mixing 2.5 g of GaCl ₃ to the element surface using a spinner,
For example, 150℃ for 30 minutes, 400℃ in _N2 atmosphere
An insulating film with a thickness of about 800 Å is formed by heat treatment at 600° C. for 30 minutes and 60 minutes at 600° C.

Next, parts of the insulating film 19 on opposite sides of the p ^- type GaAs epitaxial layer 17 are removed, and a source electrode 20 and a drain electrode 21 made of, for example, AuGeNi are formed therein, and the p ^- type GaAs epitaxial layer 17 is removed. A gate electrode 22 made of, for example, Al is formed so as to cover the region in contact with the insulating film 19 of No. 17 (FIG. 4F).

According to this manufacturing method, since the n ⁺ type GaAs epitaxial layer 18, which becomes the source region and the drain region, is formed using the liquid phase epitaxial growth method, even if it is grown on a trapezoidal structure. Regardless, since the surface becomes flat, the element surface can be easily flattened by subsequent etching. Furthermore, since the Al anodic oxidation method and spinner method, which are effective insulating film formation methods for GaAs, are employed, an insulating film with good interfacial properties can be easily formed.

Furthermore, in this embodiment, the substrate 16 and p ^- type GaAs
The epitaxial layer 17 is etched to form a protrusion with a triangular cross section (FIG. 4B), and the n ⁺
Step of etching the type GaAs epitaxial layer 18 and the p ^- type GaAs epitaxial layer 17 (fourth step)
In Figure D), the n ⁺ type GaAs epitaxial layer 17
By setting the exposed length L to 1 μm or less, it becomes possible to manufacture a MOSFET with a short gate length that exceeds the limits of conventional ring graph technology. In other words, the minimum pattern width that can be formed with good reproducibility and high yield using photolithography technology using ultraviolet or deep ultraviolet light is approximately 1 μm, and in principle, electron beam exposure is capable of forming fine patterns of 1 μm or less. In terms of technology, for reasons such as the lack of good resist materials, the pattern width that can be obtained with good reproducibility and high yield in practice at this stage is still about 1 μm, but with the above method, it is possible to control the etching depth. By adjusting the exposed length L of the p ^- type GaAs epitaxial layer 17, a MOSFET having a gate length of 1 μm or less, for example, about 0.3 μm, can be manufactured with good reproducibility and high yield.

As can be seen from the above description, in the present invention, the epitaxially grown semiconductor layer containing high concentration impurities, which is formed to cover the side surface of the semiconductor layer serving as the active layer, is used as the source region and the drain region. Unlike conventional devices in which the implanted regions are the drain and source regions, there is no risk of thermal deterioration of the active layer, and the flattening of the device surface facilitates microfabrication, and it is easier to use for GaAs. Al is an effective insulating film formation method.
Since an anodic oxidation method or a spinner method can be employed, an insulating film having good interfacial properties can be easily formed. Further, since the source and drain regions are thicker than the active layer due to the striped protrusions provided on the substrate, there is an advantage that the source resistance can be sufficiently reduced. Furthermore, since the source and drain regions are formed using the liquid phase epitaxial growth method, there is an advantage that the device surface can be easily flattened even though there are steps on the substrate.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways. For example, the semiconductor material is not limited to GaAs, but may also be InP or the like.

[Brief explanation of the drawing]

1 and 2 are device cross-sectional views showing the structure of a conventional inversion-type MOSFET, FIG. 3 is a device cross-sectional view showing the structure of an inversion-type MOSFET manufactured by the manufacturing method of the present invention, and FIG. 4 3 is a manufacturing process diagram used to explain an example of the manufacturing method of the device shown in FIG. 16 is a semi-insulating GaAs substrate, 17 is a p ^- type GaAs
Epitaxial layer, 18 is n ⁺ type GaAs epitaxial layer, 19 is an insulating film, 20 is a source electrode, 21
2 is a drain electrode, 22 is a gate electrode, and 23 is a striped protrusion.

Claims (1)

[Claims] 1. A step of forming a semiconductor layer having one conductivity type on a semi-insulating semiconductor substrate, and etching away a portion of the semiconductor layer and the semi-insulating semiconductor substrate to form a striped protrusion having the semiconductor layer on the upper surface. forming an epitaxially grown semiconductor layer containing high concentration impurities of a different conductivity type from the semiconductor layer by a liquid phase epitaxial growth method until the semiconductor layer on the striped protrusion is completely filled; etching the entire surface of the epitaxially grown semiconductor layer containing high concentration impurities until at least the semiconductor layer is exposed; and forming an insulating film on the exposed surface of the semiconductor layer and the epitaxially grown semiconductor layer containing high concentration impurities. and forming a gate electrode on the insulating film on the upper part of the semiconductor layer, and removing part of the insulating film on the epitaxially grown semiconductor layer containing high concentration impurities on opposite sides of the gate electrode. A method for manufacturing a semiconductor device, comprising the step of forming a source electrode and a drain electrode in the removed portion.