JPS6333304B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an inverted insulated gate field effect transistor and a method of manufacturing the same.

The general structure of an inverted insulated gate field effect transistor (hereinafter referred to as an inverted MOS FET) is as follows:
For example, as shown in the cross-sectional view of the device in FIG. 1, a source region 2 and a drain region 3 of different conductivity types are formed on a semiconductor substrate 1 of one conductivity type, and a source electrode 4 and a drain electrode 5 are provided in both regions. Further, a gate electrode 7 is formed between the source and drain regions via an insulating film 6, and by applying a voltage to the gate electrode 7, the conductivity type of the gate region 8 is reversed.
The current flowing through this is controlled by the gate voltage. Inverted MOS with this structure
FETs are currently widely realized using Si.

However, when GaAs is used as the semiconductor material, there are problems in that the above structure is difficult to manufacture or it is difficult to obtain an inversion type MOS FET with excellent characteristics. That is, diffusion technology or ion implantation technology is generally used to form the source region 2 and drain region 3, but in the case of GaAs, such diffusion technology has not been established due to the lack of suitable n-type impurities. In addition, the ion implantation method requires high-temperature heat treatment after implantation.
There was a problem in that the interface state between GaAs and the insulating film was susceptible to thermal deterioration.

Therefore, in the case of GaAs, a p ^- type semiconductor layer 10 and an n ⁺ type semiconductor layer 11 are grown on a semi-insulating GaAs substrate 9, as shown in the cross-sectional view of the device in FIG. A structure in which the n ⁺ type semiconductor layer 11 is etched away until it reaches the p ^- type semiconductor layer 10, a gate electrode 13 is formed there through an insulating film 12, and a source electrode 14 and a drain electrode 15 are formed on both sides of the gate electrode 13. Inverted MOS
FET has been proposed. Although this structure eliminates the problems caused by using diffusion regions or ion-implanted regions as the source and drain regions, it is difficult to perform microfabrication due to the formation of steps on the surface, and it also Depending on the type, the disadvantage is that it is difficult to manufacture good MOS FETs due to the difference in level. For example, as a method that allows the formation of an insulating film with good interfacial properties for GaAs, vacuum-deposited Al is directly replaced with Al.
The method of anodic oxidation until the oxidation of
(referred to as Al anodization method) and a spinner containing Ga.
A method is known in which an alcoholic solution of SiO ₂ is applied and then heat treated (hereinafter referred to as the spinner method), but in the Al anodizing method, due to the step on the surface, the thickness of the Al film is different between near the step and at the center of the gate. Because it differs in
It becomes difficult to anodize only Al over the entire gate region. As a result, there are regions where GaAs is partially anodized, making it difficult to obtain good interface properties. Further, the spinner method has a problem in that it is difficult to form an insulating film with a uniform thickness due to surface steps.

The present invention improves these conventional drawbacks, and its purpose is to use highly impurity-containing epitaxially grown semiconductor layers as the source and drain regions and to flatten the device surface.
The object of the present invention is to enable the formation of an insulating film having a good interface with the active layer and to facilitate high-precision processing. Examples will be described in detail below.

FIG. 3 is a cross-sectional view of an inverted MOS FET manufactured by the manufacturing method of the present invention, in which 16 is a semi-insulating GaAs substrate, 17 is an n ⁺ type
18 is a striped groove, 19 is a p ^- type GaAs epitaxial layer, 20 is an insulating film, 21 is a gate electrode, 22 is a source electrode,
23 is a drain electrode.

The inverted MOS FET shown in Figure 3 is semi-insulating.
GaAs substrate 16 and n ⁺ type formed on it
GaAs epitaxial layer 17 and this n ⁺ type GaAs
A striped groove 18 having a V-shaped cross section that penetrates the epitaxial layer 17 and reaches the semi-insulating GaAs substrate 16, a p ^- type GaAs epitaxial layer 19 buried in the striped groove 18, and a p ^- type GaAs epitaxial layer 19 buried in the striped groove 18.
A gate electrode 21 is formed on the GaAs epitaxial layer 19 with an insulating film 20 in between, and a source electrode 22 is formed on the n ⁺ type GaAs epitaxial layer 17 on opposite sides of the gate electrode 21.
and a drain electrode 23. The p ^- type GaAs epitaxial layer 19 buried in the striped groove 18 becomes an active layer, and the n ⁺ type GaAs epitaxial layer 17 becomes a source region and a drain region.

As described above, since the source region and the drain region are epitaxially grown semiconductor layers containing high concentration impurities, a heat treatment step is not required in the manufacturing process, so that the surface of the p ^- type GaAs epitaxial layer 19 is not subject to thermal deterioration. will all disappear. Furthermore, since the element surface is flat, the aforementioned Al anodic oxidation method or spinner method can be employed when forming the gate insulating film, making it possible to form an insulating film with good interfacial properties. Furthermore, since the element surface is flat, highly fine processing can be easily performed.

FIGS. 4A to 4F are manufacturing process diagrams for explaining an example of the method for manufacturing the inverted MOS FET of the present invention. On the ^GaAs substrate 16, for example, ^{an n}
A GaAs epitaxial layer 17 is grown (FIG. 4A), followed by an anisotropic etchant such as NH ₄ OH:
Using a mixture of H ₂ O ₂ :H ₂ O=3:1:50, n ⁺ type
The GaAs epitaxial layer 17 and the substrate 16 are etched to form striped grooves 18 with a V-shaped cross section that reach the substrate 16 (FIG. 4B).

Next, p ^- type was grown by liquid phase epitaxial growth method.
For example, the GaAs epitaxial layer 19 is of n ⁺ type until the n ⁺ type GaAs epitaxial layer 17 is completely filled.
The GaAs epitaxial layer 17 is grown at a carrier density of 5×10 ¹⁵ cm ⁻³ , for example, so that the thickness on the flat surface is about 2 to 3 μm. At this time, Fig. 4C
As shown in the p ^- type GaAs epitaxial layer 19
Although grown on a V-shaped structure, its surface is flat. Furthermore, since the striped grooves 18 have a V-shaped cross section, compared to a rectangular cross section with the same groove width, the p ^- type must be grown until the element surface becomes flat.
The GaAs epitaxial layer 19 has the advantage of being thin. This is due to the difference in the growth rate of the epitaxial layer due to the difference in the radius of curvature.As a result, the epitaxial growth time can be shortened, and the buried semiconductor layer can be exposed in later processes such as etching. This makes the process easier. It goes without saying that the cross section may be rectangular.

Next, n ⁺ in the area other than the striped groove portion 18
p ^- until the type GaAs epitaxial layer 17 is exposed.
The GaAs epitaxial layer 19 is etched (FIG. 4D), and an insulating film 20 is formed over the entire surface (FIG. 4E). As the method for forming the insulating film, for example, the two methods described above are employed. In this case, when using the Al anodic oxidation method, for example, Al is vacuum-deposited to a thickness of about 800 Å on the element surface, and then this is finished using a mixture of tartaric acid, ethylene glycol, and water until the Al is easily oxidized. Anodic oxidation is performed at a current density of, for example, 0.5 mA/ ^cm.sup.2 , and then heat treatment is performed at, for example, 400.degree. C. for 30 minutes in a _N.sub.2 atmosphere. Also, when using the spinner method, for example, add 5g of SiO ₂ to 100cc of alcohol,
After applying a GaCl ₃ -containing SiO ₂ alcohol solution prepared by mixing 2.5 g of GaCl ₃ to the element surface using a spinner,
e.g. 150℃ for 30 minutes, 400℃ in _N2 atmosphere
An insulating film with a thickness of about 800 Å is formed by heat treatment at 600° C. for 30 minutes and 60 minutes at 600° C.

Next, ^parts of the insulating film 20 on opposite sides of the p ^- type GaAs epitaxial layer 19 are removed, and a source electrode 22 and a drain electrode 23 made of, for example, AuGeNi are formed thereon. A gate electrode 22 made of, for example, Al is formed so as to cover the region of the layer 19 that is in contact with the insulating film 20 (FIG. 4F).

According to this manufacturing method, p ^- becomes the gate region.
Since the GaAs type epitaxial layer 19 is formed using a liquid phase epitaxial growth method, its surface is flat even though it is grown on a V-shaped structure, so it is difficult to process it by subsequent etching. This has the effect of easily flattening the element surface. Also,
Since the Al anodic oxidation method and spinner method, which are effective insulating film formation methods for GaAs, are employed, an insulating film with good interfacial properties can be easily formed.

As can be seen from the above description, the present invention involves cutting an epitaxially grown semiconductor layer containing high concentration impurities formed on a semi-insulating substrate into stripes to form a source region and a drain region, respectively, and cutting the epitaxially grown semiconductor layer containing high concentration impurities formed on a semi-insulating substrate into stripes to form a source region and a drain region. A semiconductor layer of a different conductivity type is embedded in the device so that the surface of the device is flat, and this is used as the active layer, unlike conventional devices in which the diffusion region and ion implantation region are used as the drain and source regions. There is no risk of thermal deterioration of the active layer, and the flattening of the element surface facilitates microfabrication, and allows for the Al anodization method and spinner method, which are effective insulating film formation methods for GaAs. Since it can be adopted, an insulating film having good interfacial properties can be easily formed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways. For example, the semiconductor material is not limited to GaAs, but may also be InP or the like.

[Brief explanation of the drawing]

Figures 1 and 2 are conventional inverted MOS FETs.
3 is an element sectional view showing the structure of an inverted MOS FET manufactured by the manufacturing method of the present invention, and FIG. 4 illustrates an example of the manufacturing method of the device shown in FIG. 3. This is a manufacturing process diagram used for this purpose. 16 is a semi-insulating GaAs substrate, 17 is n ⁺ type GaAs
epitaxial layer, 18 is a striped groove, 1
9 is a p ^- type GaAs epitaxial layer, 20 is an insulating film, 21 is a gate electrode, 22 is a source electrode, 23
is the drain electrode.

Claims (1)

[Claims] 1. Forming a highly doped epitaxially grown semiconductor layer of one conductivity type on a semi-insulating semiconductor substrate, and etching away a portion of the semiconductor layer and the semi-insulating semiconductor substrate to form striped grooves. a step of forming a semiconductor layer of a conductivity type different from the epitaxially grown semiconductor layer containing high concentration impurities by liquid phase epitaxial growth until the striped grooves are completely filled and the surface is flat; a step of etching the entire surface of the semiconductor layer to expose the epitaxially grown semiconductor layer containing high concentration impurities in a region other than the striped grooves; a step of forming an insulating film on the exposed surface and the semiconductor layer; A gate electrode is formed on the insulating film on the upper layer, and a part of the insulating film on the epitaxially grown semiconductor layer containing high concentration impurities on opposite sides of the gate electrode is removed, and a source is provided in the removed part. 1. A method for manufacturing a semiconductor device, comprising the step of forming an electrode and a drain electrode.