JPS6237889B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a manufacturing method thereof;
In particular, it relates to the structure of a bulk conduction type insulated gate field effect transistor and its manufacturing method.

A bulk conduction type insulated gate field effect transistor (hereinafter referred to as a bulk conduction type MOSFET) has, for example, a source electrode 3 and a semiconductor layer 2 of one conductivity type provided on a semi-insulating semiconductor substrate 1, as shown in FIG. It has a structure in which a drain electrode 4 is provided, and a gate electrode 6 is formed on the semiconductor layer 2 between both electrodes via an insulating film 5, and the source electrode 3 and the drain electrode 4 are connected by the voltage applied to the gate electrode 6. This is to control the current flowing through the semiconductor layer 2 between them. Inversion type MOSFETs, which are widely used in Si and other materials, use surface electrical conduction, so their mobility can only be smaller than the mobility in the bulk, whereas bulk conduction type MOSFETs with the above structure use carrier transfer. Since the semiconductor layer 2, which has a high conductivity, is used as the active layer, high-speed operation is possible, and even if the gate length is shortened, short channel effects such as punch-through, which are observed in inverted MOSFETs, do not occur. Furthermore, unlike shot gate type FETs, gate current does not flow even when a positive voltage is applied to the gate electrode, so the logic amplitude can be increased, making it an element suitable for high-speed operation. In order to enable higher-speed operation, it is theoretically advantageous to use GaAs, which has a higher carrier mobility than Si, as a semiconductor material, so research and development of bulk conduction MOSFETs using GaAs has been conducted in recent years. It's being pushed forward.

By the way, the thickness and carrier density of the semiconductor layer 2, which is the active layer in a bulk conduction type MOSFET, are determined by the required pinch-off voltage, drain breakdown voltage, etc., and are usually about 1×10 ¹⁷ cm ^-3 . A carrier density of about 0.2 μm is used. For this reason, if the source electrode 4 and drain electrode 5 are provided directly on the semiconductor layer 2, it will be difficult to obtain good ohmic electrodes. Forming a high concentration impurity region is practiced. However, when using GaAs as a semiconductor material, its diffusion technology has not been established due to the lack of suitable n-type impurities.
Further, since the ion implantation technique and the diffusion technique involve a heat treatment process, there is a problem that the surface of the semiconductor layer 2 is easily subject to thermal deterioration, making it difficult to obtain a good operating layer.

Furthermore, the structure shown in FIG. 1 has the disadvantage that the source resistance is large because the thickness of the semiconductor layer 2 in the source and drain portions is thin. Bulk conduction type MOSFETs are also known that have a structure in which the gate area is made thinner by etching, etc., but this type of structure has height differences on its surface, which reduces photolithography accuracy and requires high-fine processing. Moreover, depending on the method used to form the insulating film, this step makes it difficult to manufacture a good MOSFET. In other words, a method that allows the formation of an insulating film with good interfacial properties for GaAs is a method in which vacuum-deposited Al is anodized until the oxidation of Al is completed (hereinafter referred to as the Al anodization method). A method is known in which an alcohol solution of SiO ₂ containing Ga is applied using a spinner and then heat treated (hereinafter referred to as the spinner method). However, in the Al anodizing method, the thickness of the Al film is close to the step due to surface steps. and the center of the gate, making it difficult to anodize only Al over the entire gate region, and creating areas where GaAs is partially anodized, making it difficult to obtain good interface characteristics. become. Further, the spinner method has a problem in that it is difficult to form an insulating film with a uniform thickness due to surface steps.

The present invention has improved such conventional drawbacks, and its purpose is to use epitaxially grown semiconductor layers containing high concentration impurities in the source and drain regions and to flatten the device surface.
The purpose of this invention is to enable formation of a good insulating film and active layer, high-quality processing, and to reduce source resistance. Examples will be described in detail below.

FIG. 3 is an element cross-sectional view showing an embodiment of the bulk conduction type MOSFET of the present invention, and 7 is a semi-insulating MOSFET.
GaAs substrate, 8 is n-type GaAs epitaxial layer, 9
is an n ⁺ type GaAs epitaxial layer, 10 is an insulating film,
11 is a source electrode, 12 is a drain electrode, 13 is a gate electrode, and 14 is a striped protrusion.

As shown in the figure, the bulk conduction type MOSFET of this embodiment includes a semi-insulating GaAs substrate 7 having a striped protrusion 14 with a trapezoidal cross section approximately at the center of the main surface, and The n-type GaAs epitaxial layer 8 formed on the
An n ⁺ type layer formed flat on a semi-insulating GaAs substrate 7 so as to cover both sides of a GaAs epitaxial layer 8
A GaAs epitaxial layer 9, a gate electrode 13 formed on the n-type GaAs epitaxial layer 8 via an insulating film 10, and an n ⁺ -type GaAs epitaxial layer on opposite sides with the gate electrode 13 in between. A source electrode 11 and a drain electrode 12 are formed on the electrode 9 . n-type formed on the striped protrusion 14 of the semi-insulating GaAs substrate 7
The GaAs epitaxial layer 8 becomes the active layer and is of n ⁺ type.
The GaAs epitaxial layer 9 becomes a source region and a drain region.

In this way, the striped protrusions 14 are provided on the semi-insulating GaAs substrate 7, and the source and drain regions are thick relative to the thickness of the active layer, so the source resistance is sufficiently small, and the element surface is Since it is flat, highly fine processing can be easily carried out, and since the above-mentioned Al anodization method and spinner method can be employed, it is possible to form an insulating film having good interfacial properties. Furthermore, since the source and drain regions are epitaxial layers rather than conventional ion-implanted layers or diffusion layers,
The manufacturing process does not require a heat treatment process,
Therefore, the n-type GaAs epitaxial layer 8, which serves as the active layer, is completely free from thermal deterioration.

Figures 4A to 4F are bulk conductivity types of the present invention.
This is a manufacturing process diagram used to explain an example of a method for manufacturing a MOSFET.
On the substrate 7, a thickness of 1 to 2 μm, a carrier density of 1×
A 10 ¹⁷ cm ^-3 n-type GaAs epitaxial layer is grown (Figure 4A) and then an anisotropic etchant e.g.
The n-type GaAs epitaxial layer 8 and the substrate 7 are etched to a depth of, for example, 4 μm using a mixed solution of NH ₄ OH:H ₂ O ₂ :H ₂ O=3:1:50 to form striped protrusions with a trapezoidal cross section. A portion 14 and an operating layer thereon are formed (FIG. 4B).

Next, by liquid phase epitaxial growth method, n ⁺
The type GaAs epitaxial layer 9 has a thickness of, for example, 5μ.
m, and the carrier density is 1×10 ¹⁹ cm ⁻³ . At this time, as shown in Figure 4C, n ⁺ type
Although the GaAs epitaxial layer 9 is grown on a trapezoidal structure, its surface is flat.

Next, the n + -type GaAs epitaxial layer 9 and the n ^- type GaAs epitaxial layer 8 are etched until the n-type GaAs epitaxial layer 8 has a desired thickness, for example, 0.2 μm (FIG. 4D). Then, an insulating film 10 is formed over the entire surface of the element (FIG. 4E). As the insulating film forming method, for example, the two methods described above are employed. In this case, when using the Al anodic oxidation method, for example, Al
was vacuum-deposited to a thickness of approximately 800 Å, and this was coated with tartaric acid,
Al using a mixture of ethylene glycol and water
For example, the current density until the oxidation tends to end
Anodic oxidation is carried out at 0.5 mA/cm ² and heat treatment is performed at 400° C. for 30 minutes in a N ₂ atmosphere. When using the spinner method, for example, add 5 g of SiO ² and 2.5 g of GaCl ₃ to 100 c.c. of alcohol.
After applying a SiO ₂ alcohol solution containing GaCl ₃ mixed in the ratio _of
In an atmosphere, at 150℃ for 30 minutes, at 400℃ for 30 minutes,
For example, by heat treatment at 600℃ for 60 minutes,
This is carried out so as to form an insulating film with a thickness of .

Next, parts of the insulating film 10 on opposite sides of the n-type GaAs epitaxial layer 8 are removed, and a source electrode 11 and a drain electrode 12 made of, for example, AuGeNi are formed thereon.
A gate electrode 13 made of, for example, Al is formed on the insulating film 10 in a portion in contact with the GaAs epitaxial layer 8 (FIG. 4F).

According to this manufacturing method, the n-type
Since the thickness and carrier density of the GaAs epitaxial layer 8 and the thickness and carrier density of the source and drain regions can be selected independently, the operation is determined by the required pinch-off voltage, drain breakdown voltage, etc. The thickness of the semiconductor layer under the ohmic electrode can be increased and the carrier density can be increased without changing the layer thickness and carrier density. Therefore, a good ohmic electrode can be easily formed and the value of the source resistance can be kept sufficiently small. Also, n ⁺ becomes the source region and drain region.
Since the GaAs type epitaxial layer 9 is formed using a liquid phase epitaxial growth method, its surface becomes flat even though it is grown on a trapezoidal structure. This has the effect of easily making the element surface flat.

As can be seen from the above description, the present invention uses an epitaxially grown semiconductor layer containing high concentration impurities, which is formed to cover the side surface of a semiconductor layer serving as an active layer, as a source region and a drain region. Unlike conventional devices in which the implanted regions serve as drain and source regions, there is no risk of thermal deterioration of the active layer, and the planarization of the device surface facilitates microfabrication and is effective for GaAs. Since the Al anodic oxidation method and the spinner method, which are insulating film forming methods, can be employed, there is an advantage that an insulating film having good interfacial properties can be easily formed. Furthermore, since the source and drain regions are thicker than the active layer due to the striped protrusions provided on the substrate, there is an advantage that the source resistance is reduced. Therefore, the present invention can be applied not only to GaAs but also to InP.
Bulk conductivity type made of semiconductor materials that are difficult to use with equal diffusion technology and ion implantation technology
If applied to MOSFETs, it will be very effective in improving their characteristics.

[Brief explanation of the drawing]

Figures 1 and 2 are conventional bulk conduction type
3 is a cross-sectional view of a device showing the structure of a MOSFET, FIG. 3 is a cross-sectional view of a device showing the structure of a bulk conduction type MOSFET according to an embodiment of the present invention, and FIG. 4 is a manufacturing process diagram used to explain the manufacturing method of the device shown in FIG. It is. 7 is a semi-insulating GaAs substrate, 8 is an n-type GaAs epitaxial layer, 9 is an n ⁺ type GaAs epitaxial layer,
10 is an insulating film, 11 is a source electrode, 12 is a drain electrode, 13 is a gate electrode, and 14 is a striped protrusion.

Claims (1)

[Scope of Claims] 1. A semi-insulating semiconductor substrate having a striped protrusion on its main surface, a semiconductor layer of one conductivity type formed on the striped protrusion of the semi-insulating semiconductor substrate, and a semiconductor layer of one conductivity type formed on the striped protrusion of the semi-insulating semiconductor substrate. an epitaxially grown semiconductor layer containing high concentration impurities and having the same conductivity type as the semiconductor layer formed on the semi-insulating semiconductor substrate so as to cover both sides; and a gate electrode formed on the semiconductor layer via an insulating film. . A semiconductor device comprising a source electrode and a drain electrode formed on the epitaxially grown semiconductor layer containing high concentration impurities on opposite sides of the gate electrode. 2. Forming a semiconductor layer having one conductivity type on a semi-insulating substrate, and etching away a portion of the semiconductor layer and the semi-insulating substrate to form a striped protrusion having the semiconductor layer on the upper surface. a step of forming an epitaxially grown semiconductor layer containing high concentration impurities of the same conductivity type as the semiconductor layer by a liquid phase epitaxial growth method until the semiconductor layer on the striped protrusion is completely filled; etching the entire surface of the epitaxially grown semiconductor layer containing a high concentration of impurities until at least the semiconductor layer is exposed; forming an insulating film on the exposed surface of the semiconductor layer and the epitaxially grown semiconductor layer containing the high concentration of impurities; A gate electrode is formed on the insulating film in contact with the semiconductor layer, and a portion of the insulating film on the epitaxially grown semiconductor layer containing high concentration impurities on opposite sides of the gate electrode is removed to form a source thereon. 1. A method for manufacturing a semiconductor device, comprising the step of forming an electrode and a drain electrode.