JPS6337987B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives orthogonally multiplexed multiple quadrature amplitude modulation (hereinafter referred to as QAM) signals via a transmission line, samples them, and converts them into analog-digital (hereinafter referred to as QAM) signals.
It is abbreviated as AD. ) transform, wave manipulation, discrete Fourier transform (hereinafter abbreviated as DFT), etc., to demodulate a plurality of source baseband (hereinafter abbreviated as baseband) signals. Regarding phase/frequency control circuits.

The orthogonal multiplex transmission method, in which multiple QAM signals are orthogonally multiplexed and transmitted, and each baseband signal is demodulated on the receiving side, enables highly efficient data transmission.Moreover, by introducing DFT into the digital signal processing process, transmission and reception are possible. It is already known that the device is considerably simplified. (See, for example, 1978 Patent Application No. 19364 and 1978 Patent Application No. 19366.)
However, conventionally, there has been no known method for demodulating carrier phase control on the receiving side of an orthogonal multiplex transmission system that has good frequency tracking characteristics and is simple.

In view of this point, the present invention provides a pilot phase/frequency control circuit in a digital processing receiving apparatus for orthogonal multiplexed signals, especially when a pilot is inserted into a predetermined channel on the transmitting side for transmission.

The present invention will be explained below using the drawings.

Figure 1 is a diagram showing the spectrum arrangement of transmission signals in the orthogonal multiplex transmission system, where 1 is the frequency ₁ .
2 is the second QAM signal modulated with a complex carrier of frequency ₂ , 3 is the complex carrier of frequency _N-1 (however, N≧3 here). (N-1)th QAM signal modulated by , 4 is the frequency
This is the pilot signal _N. However, according to the principle of orthogonal multiplex transmission system _{, k+1} − _k = _B (1≦k≦N
-1, and _B is the baud rate of each baseband signal. ) It is assumed that a relationship has been established.
On the receiving side, each QAM signal is demodulated from the signal having the spectrum arrangement shown in Fig. 1 to obtain a complex baseband signal, but in this demodulation process,
Generally, N demodulation carriers are required corresponding to N modulation carriers. However, if demodulation processing on the receiving side is performed by digital signal processing using DFT, the phase of the sampling clock is simply controlled using the phase information of the complex baseband signal obtained by demodulating the pilot signal. It is possible to equivalently control all demodulation carriers.

Now, if the received signal is y(t), y(t) is expressed as follows.

y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt } …(1) where x _o (t) is a complex baseband signal modulating a modulation carrier with frequency _o .

Let y(t) be the frequency _s (where _s = M _B ). Let the output sampled by the sampling clock be Y(z). However, z=e ^j2 〓 ^f/fs . At this time, the k-th demodulated complex baseband signal β _k (z) is expressed as β _k (z)=Y(e ^−j2 〓 ^fk/fs ·z)·G(z) (2). However, 1≦k≦N, and G(z)
is a low frequency filter with an effective band of _B /2 on one side. Here, Y(z) and G(z) are demultiplexed as follows.
That is, At this time, equation (2) is The sequence of sample values of β _k (z) every T/2 seconds (T=1/ _B ), _β˜k (z ^M/2 ), is given by the following equation.

Here, if we use the relationship _k = ₁ + (k-1) _B , _s = M _B , we get The signal processing expressed by equation (7) is as follows:
As described in No. 19366, this is realized using a preprocessing circuit, a DFT processing circuit, a polyphase circuit, etc. According to this method, the multiplication coefficient in the DFT processing circuit is
e ^-j2 〓 ^(k-1)l/M does not depend on the sampling frequency _s , and the frequency offset term e ^-j2 〓 ^f1/fs is also determined by the ratio of ₁ and _B predetermined on the transmitting side. (e ^-j2 〓 ^f1/fB ) Read-only memory (hereinafter abbreviated as ROM) as ^1/M
It would be better to store it in . Therefore, all demodulation carriers ₁ , _{2, .} . . , _N are generated from the sampling clock of frequency _s . Here, the phase shift between the k-th modulation carrier and the k-th demodulation carrier is defined as θ _k (t), and this is regarded as the phase shift of the modulation carrier with respect to the demodulation carrier. In this case, equation (1) is expressed as y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt+j 〓 ^n(t) }...(8). Here, since the pilot signal of frequency _N is inserted into the Nth channel as described above, x _N (t)=1. Therefore, the demodulated output of the Nth channel can be obtained from equations (6) and (8) as follows. (The band-limiting effect of filter G(z) is also taken into consideration).

Figure 2 shows the spectrum of β~ _N (z ^M/2 ) expressed by equation (9), where 5 is the emission line spectrum obtained as the average of the first term of equation (9), and 6 is the phase. The spectrum spread due to noise, 7, is the second equation (9).
This is the interference from adjacent channels expressed in terms. As is clear from Fig. 2, a low frequency filter having a pass characteristic as shown by 8 in Fig _.
(z ^M/2 ), the signal γ _N obtained as its output
(z ^M/2 ) is obtained by taking only the first term of equation (9),
It is expressed by the following formula.

However, φ _N (t)=e ^j 〓 ^N(t) . If φ _N (z) is the Z-transformed sample value sequence of φ _N (t) sampled every T _s seconds, then from equations (10) and (4), γ _N (z ^M/2
)
is T/2 after passing φ _N (z) through filter G(z).
It can be seen that this is a row of sample values taken every second. Here, G(z) is a low-pass filter, and the band of Φ _N (z) is usually sufficiently narrow compared to the band of G(z), so γ _N (z ^N/2 ) can be changed from Φ _N (z) in the end. It can be seen that the sample value series is obtained by extracting sample values every T/2 seconds. That is, Therefore, a sample value sequence with a phase error θ _N (t) can be obtained from the complex sample value sequence γ _N (z ^M/2 ).
By the way, it is clear from the above signal processing process that the phase shift θ _N (t) follows the phase shift θ _s (t) from the normal phase of the sampling clock, and is expressed as θ _N (t)=(f ₁ /f _s +N-1/M) θ _s (t) …(12) Therefore, the sample value of θ _N (t) is θ _s
It is proportional to the sample value of (t). Therefore γ _N (z ^M/2 )
By controlling a voltage controlled oscillator with an oscillation frequency _s using the sample value of θ _N (t) obtained from It is possible to perform phase control of all demodulation carriers. However, in this method, although the circuit configuration is extremely simple, in an equivalent phase-locked loop consisting of a voltage-controlled oscillator → sampling circuit → digital demodulator → phase difference detection circuit → voltage-controlled oscillator, the digital demodulator is Since the delay is large, the frequency tracking characteristics of the system are poor. For example, if an unstable voltage controlled oscillator is used in this system, the delay included in the system may prevent the phase-locked loop from drawing in properly, resulting in periodic oscillation frequency fluctuations. In order to improve such deterioration of frequency tracking characteristics due to delay, it is necessary to detect not only phase difference information but also frequency difference information from the output of the digital demodulator and control the voltage controlled oscillator using both of these pieces of information.

The first object of the present invention is to provide a novel pilot phase/frequency control system based on the above principle that does not require a phase comparator circuit, a frequency multiplier circuit, etc. required in a normal phase-locked circuit, and has good frequency tracking characteristics of the system. The purpose is to provide circuits.

FIG. 3 is a block diagram showing a first specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention, and 10 is a block diagram of the digital processing receiver for orthogonal multiplexed signals. input terminal, 11 is a sampling circuit, 12
is an AD converter, 13 is a digital arithmetic processing unit, 1
7 and 18 are low-pass wave generators, 19 is a phase difference detection circuit, 20 is a frequency difference detection circuit, 21 is a synthesis circuit,
22 is a voltage controlled oscillation circuit. The portion surrounded by the broken line 16 is a conventionally known processing section, and the other portions are the pilot phase/frequency control circuit according to the present invention. In Figure 3, input terminal 1
The signal received at 0 is processed by the sampling circuit 11 to
sampled by the sampling clock of _s , AD converter 1
The data is digitally encoded at step 2. Further, this digitally encoded signal undergoes demodulation processing as described above in the digital arithmetic processing section 13 and is then output at the output terminal 1.
4 and 15, β~ ₁ (z ^M/2 ) and β~ ₂ expressed by equation (7)
(z ^M/2 ) is output. On the other hand, β~ _N (z ^M/2 ) containing the demodulated complex pilot signal given by equation (9)
The real part and imaginary part are respectively low-pass wave filter 1
The complex signal γ _N expressed by equation (11) passing through 7 and 18
(z ^M/2 ). The phase difference detection circuit 19 is
The phase amount is detected from the complex signal γ _N (z ^M/2 ). Furthermore, the frequency difference detection circuit 20 is a phase difference detection circuit 19.
Detect the temporal change in the phase signal obtained in . The synthesis circuit 21 synthesizes the output of the phase difference detection circuit 19 and the output of the frequency difference detection circuit 20 using an adding means or the like, and controls the voltage controlled oscillator 22 with the output. Through this control, the sampling circuit 11 receives the phase-controlled sampling clock from the voltage controlled oscillator 2.
Supplied from 2.

4 shows a phase difference detection circuit indicated by 19 in FIG. 3, a frequency difference detection circuit indicated by 20, and 2.
FIG. 1 is a circuit diagram showing a specific example of implementation of a control signal generating section configured by a combining circuit shown in FIG. In FIG. 4, a ROM designated by 25 receives the digitally encoded γ _N input to the input terminal 24.
A digitally encoded phase difference signal θ _N (z ^M/2 ) addressed by the real part of (z ^M/2 ) and the imaginary part of γ _N (z ^M/2 ) is output. This phase difference signal θ _N
(z ^M/2 ) is input to the subtracter 27 at the same time that it is delayed by z ^-M/2 , that is, T/2 seconds, in the register 26 . In addition, the output signal z ^-M/2 θ _N (z ^M/2 ) of the register 26 is also input to the subtracter 27 , and the output signal of the subtracter 27 is [θ _N (z ^M/2 )−z ^{-M/ 2} θ _N (z ^M/2 )
]
A signal expressed as is obtained. That is, the subtractor 27
A signal corresponding to the temporal phase change is obtained at the output. Further, the adder 28 adds and synthesizes the phase difference signal obtained by the ROM 25 and the signal corresponding to the amount of phase change obtained by the subtracter 27. A digital-to-analog (hereinafter abbreviated as DA) converter 29 outputs an analog value corresponding to the thus obtained composite signal to a terminal 30. Note that 1 in Figure 4
The blocks surrounded by broken lines 9, 20, and 21 correspond to the functional blocks with the same numbers in FIG. 3, respectively. From the above explanation, the input/output transfer function of the control signal generator shown in FIG. 4 is expressed as (2-z ^-M/2 ).
A transfer function proportional to this transfer function (1-1/2・z
- ^-M/2 ) can also be realized as shown in the circuit diagram of FIG. That is, in FIG. 5, the ROM indicated by 35 has input terminals 33, 3
The phase difference signal θ _N (z ^M/2 ) is addressed by the real part and imaginary part of γ _N (z ^M/2 ) respectively input to 4.
Output. The thus obtained θ _N (z ^M/2 ) is input to the subtracter 38 on the one hand, and is multiplied by 1/2 using a 1-bit shift connection on the other hand, after which a delay of T/2 seconds is applied to the register 36. The other input terminal of the receiver subtracter 38 is reached. As the output of the subtracter 38, a digitally encoded signal (1-1/2z ^-M/2 )θ _N (z ^M/2 ) is obtained, which is passed through the DA converter 39 and output. The desired analog control signal is available at end 40.

Now, in both the implementation examples shown in Figs. 4 and 5, a control signal for a voltage controlled oscillator is obtained by linearly combining a signal corresponding to a phase difference and a signal corresponding to a frequency difference. It is also possible.
FIG. 6 is a circuit diagram showing a specific implementation example of a control signal generating section using such nonlinear combination.
In ^FIG . 6, a ROM designated by 45 is a digitally encoded phase difference signal θ _N ( _z ^M/2 ) is output.
This phase difference signal θ _N (z ^M/2 ) is delayed by T/2 seconds in a register 46 and is input to the subtracter 47 and the selector 49 at the same time as it reaches the subtracter 47 . The signal (1−z ^−M/2 )θ _N (z ^M/2 ) obtained as the output of the subtracter 47 is input to the ROM 48 and the selector 49 . The ROM 48 determines whether the absolute value of the input frequency difference information (1-z ^-M/2 )θ _N (z ^M/2 ) is larger or smaller than a predetermined value, and outputs the information to the terminal 51. Output the judgment result. selector 4
9, depending on the judgment result, if (1-z ^-M/2 )
If the absolute value of θ _N (z ^M/2 ) is greater than or equal to the predetermined value, frequency difference information (1-z ^{- M/2} ) θ _N (z ^M/2 ) is selected, and (1-
If the absolute value of θ _N (z ^{M /2} ) is less than or equal to a predetermined value, phase difference information θ _N (z ^M/2 ) is selected. Furthermore, the output of the selector 49 is converted into an analog value by a DA converter 50 and reaches an output terminal 52.

The pilot phase and
In the first specific embodiment of the frequency control circuit, the oscillation frequency of the voltage controlled oscillator is controlled by a composite signal of phase difference information and frequency difference information. Instead of obtaining a control signal using a composite signal of phase difference information and frequency difference information, the oscillation frequency of the voltage controlled oscillator is controlled using frequency difference information, and more local phase control is achieved using phase difference information. By doing so, a pilot phase/frequency control circuit with excellent frequency tracking characteristics and phase acquisition characteristics can be obtained. That is,
It is now assumed that the frequency of the sampling clock is controlled by the frequency difference information, and the steady phase shift of the sampling clock at this time is θ _s (therefore, θ _s is independent of time). At this time, the phase shift θ _k (where 1≦k≦N) between the k-th modulation carrier and the k-th demodulation carrier is θ _k = (f ₁ /f) corresponding to equation (12). _s + k-1/M) θ _s ...(13) Since the following relationship holds true, from the detected phase difference information θ _N , θ _k = f ₁ /f _s + (k-1)/M/f ₁ /f _s + (N-1)
/M·θ _N (14) θ _k is obtained as follows. Furthermore, if we use the complex quantity calculated using this θ _k , Γ _k = e ^-j 〓 ^k (15), we can calculate the phase error of the k-th demodulated complex baseband signal β ~ _k (z ^M/2 ). can be compensated.
That is, by the same process as in calculating equation (9), β ~ _k (z ^M/2 ) = [k-th channel main signal] + [interference signal from (k+1)th channel] + [(k-1)th channel main signal] + [(k-1)th channel main signal] + [(k-1)th channel main signal] ) Interference signal from the channel] However, [K-th channel main signal] [Interference signal from the (k+1)th channel] [Interference signal from the (k-1)th channel] The phase error e ^j 〓 ^k contained in the k-th channel main signal can be removed by multiplying β~ _k (z ^M/2 ) given by Γ _k defined by equation (15). can. Note that the operation of calculating Γ _k (where 1≦k≦N) from θ _N can be easily realized using a ROM or the like.

A second object of the present invention is to provide a pilot phase/frequency control circuit for a digital processing receiver for orthogonal multiplexed signals, which is based on the above principle and has good frequency tracking characteristics and phase acquisition characteristics.

FIG. 7 is a block diagram showing a second specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. In FIG. 7, the received signal input to the input terminal 60 is passed to the sampling circuit 61 at a frequency of _s.
is sampled by the sampling clock of AD converter 62.
Digitally encoded. Furthermore, this digitally encoded signal is sent to the digital arithmetic processing section 6.
Output terminals 65, 66 and 6 receive tuning processing at 3.
7 have β~ ₁ (z ^M/2 ), β~ ₂ (z ^M/2 ) and β~ _N, respectively.
( ^zM/2 )
is output. The demodulated complex baseband signals obtained in this way β~ ₁ (z ^M/2 ), β~ ₂ (z ^M/2 ), ..., β~ _N
( ^zM/2 )
are multiplied by phase difference correction signals Γ ₁ , Γ ₂ , ..., Γ _N by multipliers 68, 69, 70, etc., and output terminals 71, 72, 73 receive demodulated complex baseband signals from which stationary phase errors have been removed. I get a signal. moreover,
Of the demodulated complex baseband signals thus obtained, the real part and imaginary part of the Nth demodulated complex baseband signal corresponding to the pilot channel pass through low-pass filters 74 and 75, respectively, and unnecessary components are removed. The phase difference detection circuit 76 detects the corresponding phase difference from the outputs of the low-pass waveformers 74 and 75, and inputs the output to the frequency difference detection circuit 78 and the phase difference correction signal generation circuit 77. The phase difference correction signal generation circuit 77 receives input θ _N from (14),
Γ ₁ , Γ ₂ , ..., Γ _N are generated according to equation (15). Normally, this process is easily accomplished using ROM. On the other hand, the frequency difference detection circuit 78 detects the amount of change in phase information given as an input, and controls the oscillation frequency of the voltage controlled oscillator 79 with its output.
The voltage controlled oscillator 79 supplies the frequency-controlled sampling clock to the sampling circuit 61. In FIG. 7, a portion surrounded by a broken line 64 is a conventionally known processing section.

As explained above, according to the present invention, it is possible to obtain a pilot phase/frequency control circuit in a digitally processed receiver for orthogonal multiplexed signals that exhibits good tracking characteristics even if there is a delay in the digital arithmetic processing section. Its practical value is extremely great.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the spectrum arrangement of the transmitted signal in the orthogonal multiplex transmission system, where 1 is the frequency
_1st QAM modulated with a complex carrier of 1
signal, 2 is the second QAM signal modulated with a complex carrier of frequency ₂ , 3 is the (N- _{1)th QAM signal modulated with a complex carrier of frequency N-} 1, and 4 is the pilot signal of frequency _N. be. FIG. 2 is a diagram showing the demodulated pilot signal and the spectrum of the interference component. FIG. 3 is a block diagram showing a first specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. A conventionally known digital processing unit consisting of a converter circuit 11, an AD converter 12, a digital arithmetic processing unit 13, etc.
17 and 18 are low-pass wave generators, 19 is a phase difference detection circuit, 20 is a frequency difference detection circuit, 21 is a combining circuit, and 22 is a voltage controlled oscillator. 4 shows a phase difference detection circuit indicated by 19 in FIG. 3, a frequency difference detection circuit indicated by 20, and 2.
1 is a circuit diagram showing a specific example of implementation of a control signal generation section configured with a synthesis circuit shown in 2;
5 is ROM, 26 is register, 27 is subtracter, 2
8 is an adder, and 29 is a DA converter. FIG. 5 is a circuit diagram showing another specific implementation example of the control signal generating section similar to that in FIG.
is ROM, 36 is register, 38 is subtracter, 39
is a DA converter. FIG. 6 is a circuit diagram showing yet another specific implementation example of the control signal generating section similar to that in FIG. 49 is selector, 50 is DA
It is a converter. FIG. 7 is a block diagram showing a second specific embodiment of the pilot phase/frequency control circuit in the digital processing receiver for orthogonal multiplexed signals according to the present invention. Conventionally known processing units, 68, 69 and 70 are multipliers, 74 and 75 are low pass wave generators, 76 is a phase difference detection circuit, 77 is a phase error correction signal generation circuit, 78 is a frequency difference detection circuit, and 79 is a It is a voltage controlled oscillator.

Claims (1)

[Claims] 1. A plurality of orthogonally multiplexed orthogonal amplitude modulated signals are received via a transmission line, and a plurality of source bases are received by sampling, analog-to-digital conversion, wave manipulation, discrete Fourier transform operations, etc. In a digital processing receiver for orthogonal multiplexed signals that demodulates a band signal, a first low-pass wave is used to remove unnecessary frequency components from the real part of the demodulated complex output corresponding to a channel in which a pilot is inserted in advance on the transmitting side. a second low-pass waver for removing unnecessary frequency components from the imaginary part of the demodulated output; an output of the first low-pass waver; and an output of the second low-pass waver. a phase difference detection circuit that detects a phase error in a pilot frequency using a frequency difference detection circuit that detects a temporal change in the output of the phase difference detection circuit; Digitally processed reception of an orthogonal multiplexed signal, comprising a synthesis circuit that synthesizes the outputs of the circuits, and a power controlled oscillator whose oscillation frequency is controlled by the output of the synthesis circuit and whose output is used as the sampling clock for the sampling. Pilot phase/frequency control circuit in equipment. 2. An orthogonal multiplex signal that receives a plurality of orthogonally multiplexed amplitude modulated signals via a transmission line and demodulates a plurality of source baseband signals by sampling, analog-to-digital conversion, wave manipulation, discrete Fourier transform operations, etc. In the digital processing type receiving device,
A group of multipliers removes stationary phase errors by multiplying each of a plurality of demodulated complex outputs obtained in parallel by a phase difference correction signal. first and second low-pass waveforms that remove unnecessary frequency components from the real part and imaginary part of the complex output from which errors have been removed; a phase difference detection circuit that detects a phase error in a pilot frequency using the output of a low-pass wave generator; and a phase difference correction signal generation circuit that generates the phase difference correction signal in accordance with the output of the phase difference detection circuit. , a frequency difference detection circuit that detects a temporal change in the output of the phase difference detection circuit, and a voltage whose oscillation frequency is controlled by the output of the frequency difference detection circuit and whose output is used as a sampling clock for the sampling. A pilot phase/frequency control circuit in a digital processing receiving device for orthogonal multiplexed signals consisting of a controlled oscillator.